CN116991005A - display device - Google Patents

Abstract

The invention discloses a display device, which includes: a first substrate, a first wire layer, a first electrode, a second substrate, a display medium layer and a second electrode. The first conductor layer and the first electrode are located between the first substrate and the second substrate, the display medium layer is located between the first electrode and the second substrate, and the second electrode is located between the display medium layer and the second substrate. The first electrode includes a plurality of first lower electrode patterns and a plurality of first upper electrode patterns that are electrically separated from each other, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are electrically connected to a plurality of first conductor layers respectively. The plurality of first conductive lines has a plurality of first gaps between the plurality of first lower electrode patterns, and the plurality of first upper electrode patterns respectively overlap a plurality of first gaps.

Description

display device

Technical field

The present invention relates to an optoelectronic device, and in particular to a display device.

Background technique

Reflective LCD displays have the advantage of energy saving and environmental protection. They use the reflection or absorption of ambient light to produce bright or dark states to achieve display purposes, so there is no need to set up a backlight. Generally speaking, the liquid crystal layer of a reflective LCD can be driven by the electric field formed by the upper and lower electrodes to switch between the transmission state and the reflection state to achieve the dark state and bright state of each sub-pixel, where each The effective area of a sub-pixel is determined by the overlapping area of the upper and lower electrodes, and the area where the upper and lower electrodes do not overlap is the inactive area. However, due to the line width limit of the manufacturing process, the ratio of the ineffective area to the effective area becomes higher and higher as the pixel density (pixel per inch, PPI) increases, resulting in a significant decrease in the reflectivity of the reflective liquid crystal display.

Contents of the invention

The present invention provides a display device with improved reflectivity.

One embodiment of the present invention provides a display device, including: a first substrate, a first conductor layer, a first electrode, a second substrate, a display medium layer, and a second electrode. The first conductor layer is located on the first substrate and includes a plurality of first conductors. The first electrode is located on the first substrate and includes a plurality of first lower electrode patterns and a plurality of first upper electrode patterns that are electrically separated from each other, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively A plurality of first conductors are electrically connected, a plurality of first lower electrode patterns have a plurality of first gaps between them, and a plurality of first upper electrode patterns respectively overlap a plurality of first gaps. The first conductor layer and the first electrode are located between the first substrate and the second substrate. The display medium layer is located between the first electrode and the second substrate. The second electrode is located between the display medium layer and the second substrate.

In an embodiment of the present invention, each of the plurality of first conductors is electrically independent.

In an embodiment of the present invention, the plurality of first lower electrode patterns are separated from each other.

In an embodiment of the present invention, the plurality of first upper electrode patterns are separated from each other.

In an embodiment of the present invention, the extending directions of the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are the same.

In an embodiment of the present invention, the overlapping width of the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm.

In an embodiment of the present invention, the first upper electrode pattern and the first lower electrode pattern that overlap each other have different potentials.

In an embodiment of the present invention, the distance between adjacent first lower electrode patterns and first upper electrode patterns is greater than 0 and less than 10 μm.

In an embodiment of the present invention, the above-mentioned second electrode includes a plurality of second lower electrode patterns, and the extension direction of the plurality of second lower electrode patterns is perpendicular to the extension direction of the plurality of first lower electrode patterns.

In an embodiment of the present invention, the above-mentioned second electrode further includes a plurality of second upper electrode patterns, and the extending directions of the plurality of second upper electrode patterns and the plurality of second lower electrode patterns are the same.

In an embodiment of the present invention, there are a plurality of second gaps between the plurality of second lower electrode patterns, and the plurality of second upper electrode patterns overlap a plurality of second gaps respectively.

In an embodiment of the present invention, the above-mentioned display device further includes a second conductive line layer located between the second substrate and the display medium layer, and includes a plurality of second conductive lines, wherein a plurality of second lower electrode patterns and a plurality of The second upper electrode patterns are electrically connected to a plurality of second conductive lines respectively.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the attached drawings.

Description of the drawings

FIG. 1A is a three-dimensional schematic diagram of a display device 10 according to an embodiment of the present invention;

Figure 1B is a schematic cross-sectional view taken along section line A-A’ in Figure 1A;

FIG. 1C is a schematic top view of the first substrate 110, the first electrode 130 and the first conductor layer 150 of the display device 10 of FIG. 1A;

FIG. 1D is a schematic top view of the second substrate 120, the second electrode 140 and the second conductor layer 160 of the display device 10 of FIG. 1A;

2A to 6B are schematic cross-sectional views of the steps of a method of manufacturing the first electrode 130 of the display device 10 according to an embodiment of the present invention;

Figure 7 is a schematic top view of the first substrate 110, the first electrode 130, the first conductor layer 750 and the driving element 181 according to another embodiment of the present invention;

Figure 8 is a schematic top view of the second substrate 120, the second electrode 140 and the second conductor layer 860 according to another embodiment of the present invention;

FIG. 9 is a schematic cross-sectional view of the display device 20 according to an embodiment of the present invention.

Symbol Description

10,20:Display device

110: First substrate

111:Surface

120: Second substrate

121:Surface

130: first electrode

131: First lower electrode pattern layer

132: First upper electrode pattern layer

140: Second electrode

141: Second lower electrode pattern layer

142: Second upper electrode pattern layer

150,750: first wire layer

152,752: first conductor

160,860: Second wire layer

162,862: Second wire

170: Display media layer

181,182: Drive components

A-A’, B-B’, C-C’, D-D’, E-E’, F-F’: hatching

AF: Connector

D1: first direction

D2: second direction

E1B: First lower electrode pattern

E1T: first upper electrode pattern

E2B: Second lower electrode pattern

E2T: Second upper electrode pattern

G1,G2,G3,G4: Gap

I11, I12, I21, I22: insulation layer

IP: strip insulation pattern

PD1, PD21, PD22: pads

PN1, PN2: pin

S1, S2, S3, S4: side

V1, V2, V3: through holes

W1,W2,W3,W5,W6,W7: Width

W4, W8: spacing

Detailed ways

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout this specification, the same reference numbers refer to the same elements. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean the presence of other components between two components.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element", "component", "region", "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" or "and/or" unless the content clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprising" and/or "including" designate the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude the presence of one or more The presence or addition of other features, regions, integers, steps, operations, elements, parts and/or combinations thereof.

Additionally, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation illustrated in the figures. For example, if the device in one of the figures is turned over, elements described as "below" other elements would then be oriented "above" the other elements. Thus, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "lower" or "lower" may include both upper and lower orientations.

As used herein, "about," "approximately," or "substantially" includes the stated value and those within ordinary skill in the art, given the specific amount of error associated with the measurement in question (i.e., the limitations of the measurement system). An average within a range of acceptable deviations for a specific value determined by a person. For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms "approximately", "approximately", or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties, or other properties, and one standard deviation does not apply to all. nature.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. Accordingly, variations in the shape of the illustrations, for example as a result of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, regions shown or described as flat may typically have rough and/or non-linear characteristics. Additionally, the acute angles shown may be rounded. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to show the precise shapes of the regions and are not intended to limit the scope of the claims.

FIG. 1A is a schematic three-dimensional view of a display device 10 according to an embodiment of the present invention. Figure 1B is a schematic cross-sectional view taken along section line A-A' in Figure 1A. FIG. 1C is a schematic top view of the first substrate 110 , the first electrode 130 and the first conductor layer 150 of the display device 10 of FIG. 1A . FIG. 1D is a schematic top view of the second substrate 120 , the second electrode 140 and the second conductor layer 160 of the display device 10 of FIG. 1A .

Referring to FIGS. 1A to 1D , the display device 10 may include a first substrate 110 and a second substrate 120 . In some embodiments, the first substrate 110 overlaps the second substrate 120 . In some embodiments, the first substrate 110 is opposite to the second substrate 120 , and the surface 111 of the first substrate 110 faces the surface 121 of the second substrate 120 . In some embodiments, the first substrate 110 and the second substrate 120 are transparent substrates. For example, the substrate 110 and the substrate 120 are made of glass, organic polymer or other suitable materials.

In some embodiments, the display device 10 further includes a first electrode 130 , and the first electrode 130 is disposed on the first substrate 110 . In some embodiments, the first electrode 130 is located between the first substrate 110 and the second substrate 120 . The first electrode 130 may include a plurality of strip electrodes separated from each other. In some embodiments, the multiple strip electrodes of the first electrode 130 do not entirely belong to the same film layer. In some embodiments, the plurality of strip electrodes of the first electrode 130 are distributed in two film layers.

For example, the first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132 . In some embodiments, the display device 10 further includes an insulating layer I12, and the insulating layer I12 separates the first lower electrode pattern layer 131 and the first upper electrode pattern layer 132.

In some embodiments, the first lower electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the plurality of first lower electrode patterns E1B are separated from each other. In some embodiments, the first lower electrode pattern E1B has a stripe pattern, and the plurality of first lower electrode patterns E1B extend in parallel with each other along the first direction D1. In some embodiments, there are a plurality of gaps G1 between the plurality of first lower electrode patterns E1B, and the widths W1 of the plurality of gaps G1 along the second direction D2 are substantially the same. In some embodiments, the first direction D1 is perpendicular to the second direction D2. In some embodiments, the width W1 of the gap G1 is approximately 10 μm.

In some embodiments, the first upper electrode pattern layer 132 is located on the first lower electrode pattern layer 131 , and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T separated from each other. In some embodiments, the first upper electrode pattern E1T has a stripe pattern, and the extending direction of the first upper electrode pattern E1T is the same as the extending direction of the first lower electrode pattern E1B. In some embodiments, the plurality of first upper electrode patterns E1T extend in parallel with each other along the first direction D1. In some embodiments, there are a plurality of gaps G2 between the plurality of first upper electrode patterns E1T, and the widths W2 of the plurality of gaps G2 along the second direction D2 are substantially the same. In some embodiments, the width W2 of the gap G2 is approximately 10 μm.

In some embodiments, the plurality of first upper electrode patterns E1T respectively partially overlap the plurality of first lower electrode patterns E1B. In some embodiments, the overlapping width W3 of the first lower electrode pattern E1B and the first upper electrode pattern E1T is about 1.5 μm to 3 μm. In some embodiments, the potentials of the first upper electrode pattern E1T and the first lower electrode pattern E1B that overlap each other are different. In some embodiments, the voltage of the first upper electrode pattern E1T is about 80% to 95% of the voltage of the mutually overlapping first lower electrode pattern E1B.

In some embodiments, the plurality of first upper electrode patterns E1T respectively partially overlap the plurality of gaps G1 between the plurality of first lower electrode patterns E1B. In some embodiments, the side S1 of the first upper electrode pattern E1T in a direction (ie, the second direction D2) perpendicular to its extension direction (ie, the first direction D1) partially overlaps the first lower electrode pattern E1B, and the first The side S2 of the upper electrode pattern E1T opposite to the side S1 does not overlap the first lower electrode pattern E1B. In some embodiments, the distance W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B is greater than 0 and less than 10 μm. That is to say, each first upper electrode pattern E1T only partially overlaps a corresponding first lower electrode pattern E1B, and does not overlap the remaining first lower electrode patterns E1B to avoid generating parasitic capacitance. In some embodiments, the distance W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B can be further reduced to about 2 μm to 5 μm, using To reduce the ineffective area of each sub-pixel. In some embodiments, the distance W4 is the minimum distance between the first upper electrode pattern E1T and the non-overlapping first lower electrode pattern E1B.

In some embodiments, the display device 10 further includes a first wire layer 150 , and the first wire layer 150 is located on the first substrate 110 . In some embodiments, the display device 10 further includes an insulating layer I11, and the insulating layer I21 separates the first conductive layer 150 and the first electrode 130. In some embodiments, the first conductive layer 150 is located between the first substrate 110 and the second substrate 120 . In some embodiments, the first conductor layer 150 includes a plurality of first conductors 152, and each of the plurality of first conductors 152 is electrically independent. In some embodiments, the plurality of first conductors 152 are physically separated from each other. In some embodiments, the plurality of first lower electrode patterns E1B and the plurality of first upper electrode patterns E1T of the first electrode 130 are electrically connected to a plurality of first conductive lines 152 respectively.

In some embodiments, the display device 10 further includes a driving element 181 , and the plurality of first conductive lines 152 of the first conductive line layer 150 are electrically connected to the driving element 181 . In some embodiments, the driving element 181 is disposed on the first substrate 110 . In some embodiments, the display device 10 further includes a plurality of pads PD1, and the plurality of pads PD1 are electrically connected to the plurality of first conductive lines 152 and the driving element 181 respectively. In this way, the driving element 181 can provide signals to the plurality of first lower electrode patterns E1B and the plurality of first upper electrode patterns E1T respectively.

In some embodiments, the display device 10 further includes a display medium layer 170 , and the display medium layer 170 is located between the first electrode 130 and the second substrate 120 . In some embodiments, the first upper electrode pattern layer 132 of the first electrode 130 is located between the first lower electrode pattern layer 131 and the display medium layer 170 . In some embodiments, the display medium layer 170 includes display medium molecules, such as cholesteric liquid crystal (CLC) molecules. In some embodiments, cholesteric liquid crystal molecules can switch between a focal conic state, a homeotropic state, and a planar state. When the cholesteric liquid crystal molecules are in the focal conic state or the vertical state, the display medium layer 170 may exhibit a transmission state. When the cholesteric liquid crystal molecules are in a planar state, the display medium layer 170 may be in a reflective state to reflect incoming light, and the wavelength of the reflected light may be determined by the helical pitch of the cholesteric liquid crystal molecules.

In some embodiments, the display device 10 further includes a second electrode 140 , and the second electrode 140 is located between the display medium layer 170 and the second substrate 120 . In some embodiments, the display medium layer 170 is located between the first electrode 130 and the second electrode 140 . The second electrode 140 may include a plurality of strip electrodes separated from each other, and the extension direction of the second electrode 140 intersects the extension direction of the first electrode 130 . In this way, the overlapping area of the first electrode 130 and the second electrode 140 can drive the display medium molecules in the display medium layer 170 to change directions, thereby serving as an effective area for individual sub-pixels of the display device 10 . In some embodiments, the multiple strip electrodes of the second electrode 140 do not entirely belong to the same film layer. In some embodiments, the plurality of strip electrodes of the second electrode 140 are distributed in two film layers.

For example, the second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142 . In some embodiments, the second upper electrode pattern layer 142 of the second electrode 140 is located between the second lower electrode pattern layer 141 and the display medium layer 170 . In some embodiments, the display device 10 further includes an insulating layer I22, and the insulating layer I22 separates the second lower electrode pattern layer 141 and the second upper electrode pattern layer 142.

In some embodiments, the second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, and the plurality of second lower electrode patterns E2B are separated from each other. In some embodiments, the second lower electrode pattern E2B has a stripe pattern, and the plurality of second lower electrode patterns E2B extend parallel to each other along the second direction D2. In some embodiments, the extending direction of the second lower electrode pattern E2B intersects the extending direction of the first lower electrode pattern E1B. In some embodiments, there are a plurality of gaps G3 between the plurality of second lower electrode patterns E2B, and the widths W5 of the plurality of gaps G3 along the first direction D1 are substantially the same. In some embodiments, the width W5 of the gap G3 is approximately 10 μm.

In some embodiments, the second upper electrode pattern layer 142 is located on the second lower electrode pattern layer 141 , and the second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T separated from each other. In some embodiments, the second upper electrode pattern E2T has a stripe pattern, and the extending direction of the second upper electrode pattern E2T is the same as the extending direction of the second lower electrode pattern E2B. In some embodiments, the plurality of second upper electrode patterns E2T extend parallel to each other along the second direction D2. In some embodiments, the extending direction of the second upper electrode pattern E2T intersects the extending direction of the first upper electrode pattern E1T. In some embodiments, there are a plurality of gaps G4 between the plurality of second upper electrode patterns E2T, and the widths W6 of the plurality of gaps G4 along the first direction D1 are substantially the same. In some embodiments, gap G4 has a width W6 of approximately 10 μm.

In some embodiments, the plurality of second upper electrode patterns E2T respectively partially overlap the plurality of second lower electrode patterns E2B. In some embodiments, the overlapping width W7 of the second lower electrode pattern E2B and the second upper electrode pattern E2T is about 1.5 μm to 3 μm. In some embodiments, the potentials of the second upper electrode pattern E2T and the second lower electrode pattern E2B that overlap each other are different. In some embodiments, the voltage of the second upper electrode pattern E2T is about 80% to 95% of the voltage of the mutually overlapping second lower electrode pattern E2B.

In some embodiments, the maximum electric field intensity formed in the display medium layer 170 by the mutually overlapping first upper electrode pattern E1T and the first lower electrode pattern E1B is substantially the same. In some embodiments, the maximum electric field intensity formed in the display medium layer 170 by the overlapping second upper electrode pattern E2T and the second lower electrode pattern E2B is substantially the same.

In some embodiments, the plurality of second upper electrode patterns E2T respectively partially overlap the plurality of gaps G3 between the plurality of second lower electrode patterns E2B. In some embodiments, the side S3 of the second upper electrode pattern E2T in a direction (ie, the first direction D1) perpendicular to its extension direction (ie, the second direction D2) partially overlaps the second lower electrode pattern E2B, and the second The side S4 of the upper electrode pattern E2T opposite to the side S3 does not overlap the second lower electrode pattern E2B. In some embodiments, the distance W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B is greater than 0 and less than 10 μm. That is to say, each second upper electrode pattern E2T only partially overlaps a corresponding second lower electrode pattern E2B, and does not overlap the remaining second lower electrode patterns E2B to avoid generating parasitic capacitance. In some embodiments, the distance W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B can be further reduced to about 2 μm to 5 μm, with To reduce the ineffective area of each sub-pixel. In some embodiments, the spacing W8 is the minimum spacing between the second upper electrode pattern E2T and the non-overlapping second lower electrode pattern E2B.

Since the distance W4 between the first upper electrode pattern E1T and the first lower electrode pattern E1B and the distance W8 between the second upper electrode pattern E2T and the second lower electrode pattern E2B can be further reduced, the first electrode 130 and the second lower electrode pattern E2B can be further reduced. The ratio of the ineffective area where the two electrodes 140 do not overlap with each other to the effective area where the first electrode 130 and the second electrode 140 overlap can be further reduced to improve the reflectivity of the display device 10 .

In some embodiments, the display device 10 further includes a second conductive layer 160 disposed on the second substrate 120 and located between the first substrate 110 and the second substrate 120 . In some embodiments, the second conductive layer 160 is located between the second electrode 140 and the second substrate 120 . In some embodiments, the display device 10 further includes an insulating layer I21, and the insulating layer I21 separates the second conductive layer 160 and the second electrode 140. In some embodiments, the second conductor layer 160 includes a plurality of second conductors 162, and the plurality of second conductors 162 are each electrically independent. In some embodiments, the plurality of second wires 162 are physically separated from each other. In some embodiments, the plurality of second lower electrode patterns E2B and the plurality of second upper electrode patterns E2T of the second electrode 140 are electrically connected to the plurality of second conductive lines 162 respectively. In some embodiments, the display device 10 further includes a plurality of pads PD22 disposed on the second substrate 120, and the plurality of pads PD22 are electrically connected to the plurality of second conductors 162 respectively.

In some embodiments, the material of the first lower electrode pattern layer 131, the first upper electrode pattern layer 132, the second lower electrode pattern layer 141 and the second upper electrode pattern layer 142 is a transparent conductive material, such as indium tin oxide, Indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or other suitable transparent conductive materials. In some embodiments, the material of the insulating layers I11, I12, I21, and I22 may include transparent insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, stacks of the above materials, or other suitable materials. In some embodiments, the material of the first conductive layer 150 and the second conductive layer 160 is a metal with good conductivity, such as aluminum, molybdenum, titanium, copper and other metals, or an alloy or laminate of the above metals. However, the present invention Not limited to this.

In some embodiments, the display device 10 further includes a driving element 182 , and the plurality of second conductive lines 162 of the second conductive line layer 160 are electrically connected to the driving element 182 . In some embodiments, the driving element 182 is disposed on the first substrate 110 , and the driving elements 181 and 182 are respectively disposed on different sides of the first substrate 110 . In some embodiments, the display device 10 further includes a plurality of pads PD21, and the plurality of pads PD21 are electrically connected to the plurality of second conductive lines 162 and the driving element 182 respectively. For example, the display device 10 further includes a plurality of connectors AF, and when the first substrate 110 and the second substrate 120 are paired to form a display structure as shown in FIG. 1B , the multiple connectors AF can be electrically connected to the first substrate AF respectively. The plurality of pads PD21 on a substrate 110 and the plurality of pads PD22 on the second substrate 120 enable the plurality of second wires 162 to pass through the plurality of pads PD22, the plurality of connectors AF and the plurality of pads PD21 respectively. and electrically connected to drive element 182 . In this way, the driving element 182 can provide signals to the plurality of second lower electrode patterns E2B and the plurality of second upper electrode patterns E2T respectively.

In some embodiments, the material of the pads PD1, PD21 and PD22 is a metal with good conductivity, such as aluminum, molybdenum, titanium, copper and other metals, or an alloy or laminate of the above metals, but the invention is not limited thereto. In some embodiments, the material of the connector AF includes anisotropic conductive film (ACF).

In some embodiments, the display device 10 includes three groups of display structures as shown in FIG. 1B . The above three groups of display structures can be stacked in the vertical direction, and the first electrode 130 and the second electrode 140 overlap in the three groups of display structures. areas overlap each other. In addition, the display medium molecules of the display medium layer 170 in each group of display structures can also be adjusted so that the reflected light wavelengths of the display medium layers 170 of each group of display structures are different. In this way, the overlapping area of the first electrode 130 and the second electrode 140 in each group of display structures can be used as a sub-pixel of the display device 10 , and the overlapping sub-pixels in the three groups of display structures can constitute a pixel of the display device 10 , so that the display device 10 can achieve full color using an "overlay type" primary color system.

Below, other embodiments of the present invention will be continued to be described using FIGS. 2A to 9 , and the component numbers and related content of the embodiments of FIGS. 1A to 1D will be used, where the same numbers are used to represent the same or similar elements, and Explanations of the same technical content are omitted. For descriptions of omitted parts, reference may be made to the embodiments of FIGS. 1A to 1D , which will not be repeated in the following description.

2A to 6B are schematic cross-sectional views of the steps of a method of manufacturing the first electrode 130 of the display device 10 according to an embodiment of the present invention. In Figures 2A to 6B, Figure 2B is a schematic cross-sectional view taken along the section line BB' of Figure 2A; Figure 3B is a schematic cross-sectional view taken along the section line CC' of Figure 3A; Figure 4B is a schematic cross-sectional view taken along the section line CC' of Figure 3A; Figure 5B is a schematic cross-sectional view taken along the cross-sectional line DD' of Figure 5A; Figure 6B is a cross-sectional schematic view taken along the cross-sectional line FF' of Figure 6A.

First, please refer to FIG. 2A and FIG. 2B to form the first conductive layer 150 on the first substrate 110 . The first conductive line layer 150 may include a plurality of first conductive lines 152, and the plurality of first conductive lines 152 are separated from each other. In some embodiments, the plurality of first conductive lines 152 extend parallel to each other and in the same direction. In some embodiments, a plurality of pads PD1 and a plurality of pads PD21 may also be formed on the first substrate 110, and a plurality of first conductors 152 are respectively connected to the plurality of pads PD1.

Next, please refer to FIG. 3A and FIG. 3B to form an insulating layer I11 on the first conductive layer 150 and the first substrate 110 . The insulating layer I11 may have a plurality of through holes V1, and the plurality of through holes V1 respectively overlap, for example, an odd number of first conductive lines 152, so that a portion of the odd number of first conductive lines 152 is exposed.

Next, please refer to FIG. 4A and FIG. 4B to form a first lower electrode pattern layer 131 on the insulating layer I11. The first lower electrode pattern layer 131 may include a plurality of first lower electrode patterns E1B, and a plurality of first lower electrode patterns E1B. E1B respectively overlaps the plurality of through holes V1 of the insulating layer I11, so that the plurality of first lower electrode patterns E1B can be electrically connected to an odd number of first conductors 152 through the through holes V1 respectively.

Next, please refer to FIG. 5A and FIG. 5B to form an insulating layer I12 on the first lower electrode pattern layer 131 and the insulating layer I11. Next, a plurality of through holes V2 are formed penetrating the insulating layer I11 and the insulating layer I12, and the plurality of through holes V2 respectively overlap an even number of first conductive lines 152, so that a portion of the even number of first conductive lines 152 is exposed. In some embodiments, when the plurality of through holes V1 of the insulating layer I11 respectively expose an even number of first conductive lines 152, the plurality of through holes V2 respectively expose an odd number of first conductive lines 152.

In some embodiments, while forming multiple through holes V2, multiple through holes V3 may also be formed. The multiple through holes V3 penetrate the insulating layer I11 and the insulating layer I12, and the multiple through holes V3 overlap multiple pads respectively. PD1 and multiple pads PD21. In other words, the plurality of through holes V3 respectively expose the plurality of pads PD1 and the plurality of pads PD21.

Next, please refer to FIG. 6A and FIG. 6B to form a first upper electrode pattern layer 132 on the insulating layer I12. The first upper electrode pattern layer 132 may include a plurality of first upper electrode patterns E1T, and a plurality of first upper electrode patterns E1T. E1T respectively overlaps a plurality of through holes V2, so that the plurality of first upper electrode patterns E1T can be electrically connected to an even number of first conductors 152 through the through holes V2 respectively.

In some embodiments, if necessary, one side of the first upper electrode pattern E1T may partially overlap the corresponding first lower electrode pattern E1B, and the other side of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B may be partially overlapped. The distance between the side and the adjacent first lower electrode pattern E1B is less than 10 μm. For example, by adjusting the relative positions of the photomask used to form the first upper electrode pattern E1T and the photomask used to form the first lower electrode pattern E1B, the first upper electrode pattern E1T can be easily changed. The minimum distance between the other side of the overlapping first lower electrode pattern E1B and the non-overlapping first lower electrode pattern E1B is less than 10 μm. For example, the minimum distance is about 2 μm to 5 μm, which is used to reduce the ineffective area of each sub-pixel.

In some embodiments, the manufacturing method of the second electrode 140 is similar to the above-mentioned manufacturing method of the first electrode 130 and will not be repeated here.

In some embodiments, the driving element 181 and the driving element 182 can also be disposed on the first substrate 110 , and the plurality of pins PN1 of the driving element 181 can respectively pass through the plurality of through holes V3 to electrically connect the plurality of pads PD1 , the plurality of pins PN2 (please refer to FIG. 1B ) of the driving element 182 can also pass through the plurality of through holes V3 to be electrically connected to the plurality of pads PD21.

FIG. 7 is a schematic top view of the first substrate 110, the first electrode 130, the first conductive layer 750 and the driving element 181 according to another embodiment of the present invention. Compared with the first conductive line layer 150 shown in FIG. 1C , the main difference of the first conductive line layer 750 shown in FIG. 7 is that the plurality of first conductive lines 752 of the first conductive line layer 750 also extend to the first The electrode 130 below the plurality of first lower electrode patterns E1B and the plurality of first upper electrode patterns E1T is used to speed up the signal transmission speed of the first lower electrode patterns E1B and the first upper electrode patterns E1T, thereby reducing the signal transmission speed of each sub-pixel. Signal delay. In some embodiments, the line width W9 of the first conductive line 752 is 5 μm to 10 μm.

FIG. 8 is a schematic top view of the second substrate 120, the second electrode 140 and the second conductive layer 860 according to another embodiment of the present invention. Compared with the second conductive line layer 160 shown in FIG. 1D, the main difference of the second conductive line layer 860 shown in FIG. 8 is that the plurality of second conductive lines 862 of the second conductive line layer 860 also extend to the second The plurality of second lower electrode patterns E2B and the plurality of second upper electrode patterns E2T below the electrode 140 are used to speed up the signal transmission speed of the second lower electrode patterns E2B and the second upper electrode patterns E2T, thereby reducing the signal transmission speed of each sub-pixel. Signal delay. In some embodiments, the line width W10 of the second conductive line 862 is 5 μm to 10 μm.

FIG. 9 is a schematic cross-sectional view of the display device 20 according to an embodiment of the present invention. The display device 20 includes: a first substrate 110, a second substrate 120, a first electrode 130, a second electrode 140, a display medium layer 170, a driving element 182, pads PD21, PD22, a connector AF, and insulating layers I11, I12. I21, I22, wherein the first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132, the first lower electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T; the second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142, and the second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, and The second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T.

Compared with the display device 10 shown in FIG. 1B , the display device 20 shown in FIG. 9 is mainly different in that the insulating layer I12 of the display device 20 only covers the first lower electrode pattern E1B and the first upper electrode pattern. The overlapping portion of E1T realizes the electrical separation of the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, the insulating layer I12 includes a plurality of strip-shaped insulating patterns IP separated from each other. In some embodiments, the extending direction of the plurality of strip-shaped insulating patterns IP is parallel to the extending directions of the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, each strip-shaped insulation pattern IP partially overlaps the corresponding first lower electrode pattern E1B, and each strip-shaped insulation pattern IP partially overlaps the corresponding first upper electrode pattern E1T.

In summary, the display device of the present invention reduces the minimum distance between the first upper electrode pattern and the non-overlapping first lower electrode pattern, and reduces the distance between the second upper electrode pattern and the non-overlapping second lower electrode pattern. The minimum spacing is to increase the ratio of the effective area where the first electrode and the second electrode overlap with each other to the ineffective area where the first electrode and the second electrode do not overlap with each other, thereby increasing the reflectivity of the display device.

Although the present invention has been disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Those of ordinary skill in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of protection of the invention shall be defined by the appended claims.

Claims (12)

1. A display device, comprising:

a first substrate;

the first wire layer is positioned on the first substrate and comprises a plurality of first wires;

the first electrode is positioned on the first substrate and comprises a plurality of first lower electrode patterns and a plurality of first upper electrode patterns which are electrically separated from each other, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively and electrically connected with the plurality of first wires, a plurality of first gaps are arranged between the plurality of first lower electrode patterns, and the plurality of first upper electrode patterns are respectively overlapped with the plurality of first gaps;

a second substrate, wherein the first wire layer and the first electrode are located between the first substrate and the second substrate;

a display medium layer positioned between the first electrode and the second substrate; and

and the second electrode is positioned between the display medium layer and the second substrate.

2. The display device of claim 1, wherein the plurality of first conductive lines are each electrically independent.

3. The display device of claim 1, wherein the plurality of first lower electrode patterns are separated from each other.

4. The display device of claim 1, wherein the plurality of first upper electrode patterns are separated from each other.

5. The display device of claim 1, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns extend in the same direction.

6. The display device of claim 1, wherein an overlap width of the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm.

7. The display device according to claim 1, wherein the first upper electrode pattern and the first lower electrode pattern overlapped with each other are different in potential.

8. The display device of claim 1, wherein a pitch between adjacent first lower electrode patterns and first upper electrode patterns is greater than 0 and less than 10 μm.

9. The display device of claim 1, wherein the second electrode includes a plurality of second lower electrode patterns, and an extension direction of the plurality of second lower electrode patterns is perpendicular to an extension direction of the plurality of first lower electrode patterns.

10. The display device of claim 9, wherein the second electrode further comprises a plurality of second upper electrode patterns, and the plurality of second upper electrode patterns and the plurality of second lower electrode patterns extend in the same direction.

11. The display device of claim 10, wherein the plurality of second lower electrode patterns have a plurality of second gaps therebetween, and the plurality of second upper electrode patterns overlap the plurality of second gaps, respectively.

12. The display device of claim 10, further comprising a second conductive line layer between the second substrate and the display medium layer, and comprising a plurality of second conductive lines, wherein the plurality of second lower electrode patterns and the plurality of second upper electrode patterns are electrically connected to the plurality of second conductive lines, respectively.