CN116978829A - Test wafer scheduling method, apparatus and semiconductor equipment - Google Patents
Test wafer scheduling method, apparatus and semiconductor equipment Download PDFInfo
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- CN116978829A CN116978829A CN202311062217.0A CN202311062217A CN116978829A CN 116978829 A CN116978829 A CN 116978829A CN 202311062217 A CN202311062217 A CN 202311062217A CN 116978829 A CN116978829 A CN 116978829A
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- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/41875—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
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Abstract
本发明提供一种半导体设备中的测试晶片调度方法、装置和半导体设备，包括：将第一预定数量的测试晶片划分为多个测试晶片组；在需要使用第二预定数量的测试晶片执行工艺时，按照预设顺序，依次对多个测试晶片组进行遍历；如果在遍历时累计得到的可用测试晶片的数量达到第二预定数量，则停止遍历，并使用遍历到的可用测试晶片执行工艺；可用测试晶片为满足使用条件的测试晶片；如果当前遍历的测试晶片组中的所有测试晶片均不满足使用条件，则更换该测试晶片组。本方案可以在机台加工晶片的过程中执行更换测试晶片的任务，不需要人工干预停机。
The invention provides a test wafer scheduling method, device and semiconductor equipment in semiconductor equipment, which includes: dividing a first predetermined number of test wafers into a plurality of test wafer groups; when it is necessary to use a second predetermined number of test wafers to perform a process , traverse multiple test chip groups in sequence according to the preset order; if the number of available test wafers accumulated during the traversal reaches the second predetermined number, the traversal will be stopped, and the traversed available test wafers will be used to perform the process; available The test chip is a test chip that meets the usage conditions; if all the test chips in the currently traversed test chip set do not meet the usage conditions, the test chip set is replaced. This solution can perform the task of replacing test wafers while the machine is processing wafers, without manual intervention and shutdown.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a test wafer scheduling method and apparatus, a semiconductor device, and a computer readable medium.
Background
During processing of semiconductor wafers, it is often necessary to place a test wafer (not a product wafer) in a process chamber to perform a process for maintaining the chamber environment unchanged. Processes performed with test wafers typically need to be performed at least once before the first wafer is processed (referred to as lot-before-lot) to clean the chamber from contamination of the chamber with the previous process; at least once after a certain number of wafers are processed (called lot) to be able to keep the chamber environment constant periodically; and, performing at least once after processing the last wafer (called lot back) to be able to clean the chamber of contamination of the present process.
The number of uses of the test wafer is limited and the test wafer after a certain number of uses needs to be replaced. However, in the prior art, the machine is required to replace the test wafer in an Idle state, if the machine is processing a wafer (product wafer) and the test wafer is insufficient, the task (Job) being executed needs to be manually ended, so that the machine can be restored to the Idle state and then the task of replacing the test wafer can be executed, which seriously reduces the utilization rate and productivity of the machine.
Disclosure of Invention
The invention aims at solving at least one of the technical problems in the prior art, and provides a test wafer scheduling method, a test wafer scheduling device, a semiconductor device and a computer readable medium, which can execute the task of replacing a test wafer in the wafer processing process of a machine, do not need manual intervention to stop, and do not interfere with the task of the current process, thereby improving the utilization rate of the machine and the productivity.
To achieve the object of the present invention, there is provided a test wafer scheduling method in a semiconductor device, comprising:
dividing a first predetermined number of test wafers into a plurality of test wafer groups;
when a process is required to be executed by using a second preset number of the test wafers, traversing the plurality of test wafer groups in sequence according to a preset sequence;
stopping traversing if the number of the available test wafers obtained through traversing reaches the second preset number, and executing a process by using the traversed available test wafers; the available test wafer is a test wafer meeting the use conditions;
and if all the test wafers in the currently traversed test wafer group do not meet the use conditions, replacing the test wafer group.
Optionally, after performing a process using the traversed available test wafer, further comprising:
adding 1 to the number of times of use of each available test wafer for executing the process;
after the use times of each available test wafer are increased by 1, if all the test wafers in the test wafer group to which the available test wafers belong do not meet the use conditions, the test wafer group is replaced.
Optionally, the available test wafers meeting the use condition are test wafers with the use times smaller than a preset upper limit value and the use matched with the process.
Optionally, after traversing all the test wafer groups, if the number of the accumulated available test wafers does not reach the second predetermined number, refusing to execute the process if at least one non-matching test wafer exists, and prompting that the non-matching test wafer exists;
the unmatched test wafer is used for a number of times smaller than a preset upper limit value, and the usage and the process are unmatched.
Optionally, the replacing the test wafer set includes:
prompting replacement of the test wafer set;
when a replacement instruction is received, analyzing and obtaining test wafer information from the replacement instruction;
Judging whether the test wafer to be replaced meets the replacement condition, if so, exchanging a new test wafer with the corresponding test wafer to be replaced according to the test wafer information;
after the test wafers to be replaced have all been exchanged, the prompt for replacing the set of test wafers is cleared.
Optionally, the determining whether the test wafer to be replaced meets the replacement condition includes:
it is determined whether a test wafer to be replaced is performing a process,
if yes, determining that the replacement condition is not met, and refusing to execute the replacement instruction;
if not, judging whether all the test wafers to be replaced belong to the same test wafer group, and if so, judging whether the number of the test wafers to be replaced is equal to the number of the test wafers contained in the test wafer group, and if so, determining that the replacement condition is met;
if the test wafers do not belong to the same test wafer group or the number of the test wafers to be replaced is not equal to the number of the test wafers contained in the test wafer group, determining that the replacement condition is not met, and refusing to execute the replacement instruction.
Optionally, the test wafer information includes a first slot number of a cassette in which a new test wafer is located, and a second slot number of a storage area of the semiconductor device in which a test wafer to be replaced is located;
And exchanging the new test wafer with the corresponding test wafer to be replaced according to the test wafer information, comprising:
after a new test wafer box is placed in a loading area of the semiconductor device, if an idle buffer area exists in the semiconductor device, transferring the test wafer to be replaced, corresponding to the second wafer slot number, in the storage area into the buffer area;
transferring a new test wafer corresponding to the first wafer slot number to the wafer slot corresponding to the second wafer slot number in the storage area;
and transferring the test wafer to be replaced in the buffer area to the wafer box of the loading area.
Optionally, after the dividing the first predetermined number of test wafers into the plurality of test wafer groups, the method further includes:
setting different priorities for a plurality of the test wafer groups;
the preset sequence is the sequence from high priority to low priority.
Optionally, after the replacing the test wafer set, the method further includes:
setting the priority of the replaced test wafer group to be the lowest, and increasing the priority of the test wafer group without prompt by one level; the priority of the test wafer group with the hint but not replaced remains unchanged.
Optionally, the priority of the replaced test wafer group is set to be the lowest, and the priority of the test wafer group without prompt is increased by one level; the priority of the test wafer group with the prompt but not replaced remains unchanged, comprising:
cycling through all test wafers stored in a storage area of the semiconductor device;
judging whether the number of the test wafer group to which each test wafer obtained through traversing belongs is the same as the number of the test wafer group after current replacement,
if the priority of the current replaced test wafer group is the same, setting the priority of the current replaced test wafer group to be the lowest;
if the test wafer groups are different, judging whether the test wafer groups of the test wafers in the storage area are prompted to be replaced, and if so, keeping the priority of the test wafer groups unchanged; if not, the priority of the test wafer group is increased by one level.
As another technical solution, the present invention further provides a test wafer dispatching apparatus for dispatching a first predetermined number of test wafers in a semiconductor device, the test wafer dispatching apparatus including at least one processor and at least one memory, the memory storing at least one program therein;
The at least one program, when executed by the at least one processor, causes the at least one processor to implement the above-described method provided by the present invention.
As another aspect, the present invention also provides a semiconductor apparatus including a plurality of process chambers and a storage area storing a first predetermined number of test wafers, further comprising:
the invention provides the test wafer dispatching device.
As another aspect, the present invention also provides a computer readable storage medium for a semiconductor processing apparatus, on which a computer program is stored, which when executed by a processor, implements the above-mentioned method provided by the present invention.
The invention has the following beneficial effects:
according to the technical scheme of the test wafer scheduling method, the device, the semiconductor equipment and the computer readable medium, the first preset number of test wafers are divided into the plurality of test wafer groups, so that the grouping use and the management of the test wafers can be realized, specifically, the plurality of test wafer groups are traversed sequentially according to a preset sequence, if the number of available test wafers obtained through traversal accumulation reaches the required number, the traversal is stopped, and the traversed available test wafers are used for executing a process; and if all the test wafers in the currently traversed test wafer group do not meet the use conditions, replacing the test wafer group. Therefore, under the condition that the number of available test wafers is enough, the process can be executed by using the traversed available test wafers, and the test wafer group which does not meet the use conditions of all the test wafers can be replaced, namely, the task of replacing the test wafers is executed in the process of machining the wafers by a machine, the machine is not required to be stopped by manual intervention, and the replacement task is not interfered with the task of the current process, so that the utilization rate of the machine can be improved, and the productivity is improved.
Drawings
Fig. 1 is a structural diagram of a semiconductor device provided in the related art;
fig. 2 is a block diagram of another semiconductor device provided in the related art;
FIG. 3 is a flowchart of a test wafer scheduling method in a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a flowchart of step S5 and step S6 in an embodiment of the present invention;
FIG. 5 is a flowchart showing a specific process of step S2 in the embodiment of the present invention;
FIG. 6 is a flowchart showing a specific process of step S22 according to an embodiment of the present invention;
FIG. 7 is a flowchart showing another specific procedure of step S22 according to the embodiment of the present invention;
FIG. 8 is a flowchart showing a specific process of step S23 in the embodiment of the present invention;
FIG. 9 is a flowchart of one embodiment of a method for scheduling test wafers in a semiconductor device according to an embodiment of the present invention;
FIG. 10 is a flowchart of another embodiment of a test wafer dispatching method in a semiconductor device according to an embodiment of the present invention;
FIG. 11 is a schematic block diagram of a test wafer handler provided in an embodiment of the present invention;
fig. 12 is a block diagram of a test wafer handler in accordance with an embodiment of the present invention.
Detailed Description
In order to better understand the technical solutions of the present invention, the following describes in detail the test wafer scheduling method, apparatus and semiconductor device and computer readable medium provided by the present invention with reference to the accompanying drawings.
Referring to fig. 1, a related art semiconductor device is provided, which includes a transfer chamber VTM, a plurality of process chambers (e.g., four process chambers PM1, PM2, PM3, PM 4) and two pre-vacuum chambers (LoadLock a, loadLock B) arranged around the transfer chamber (VTM), four buffers (Buffer 1, buffer2, buffer3, buffer 4), a storage region (Dummy Port), and a loading region (e.g., four loading regions LoadPort1, loadPort2, loadPort3, loadPort 4), and a position calibration device (Aligner) for calibrating a wafer position. In addition, a robot (not shown) is included for transferring finished or unfinished wafers (not product wafers) or test wafers (not product wafers) between the two pre-evacuated chambers and the buffer, loading and storage areas. The storage area is used for storing test wafers (not product wafers), and the capacity of the storage area is consistent with that of the wafer box, for example, 25 wafers. The buffer is used for storing wafers (wafer, product wafer) or test wafers, which are processed or unprocessed, and has a capacity corresponding to that of the cassette, for example, 25 wafers. The loading area is used for loading or unloading the cassette.
Referring to fig. 2, another semiconductor device is provided in the related art, which is not configured with a storage area, in which case one of the buffers may be designated to store a test wafer, compared to the above-described semiconductor device. When the machine is initially put into use, the test wafer is loaded into the machine in advance at a position (namely, the storage area or the buffer area) where the test wafer is stored, so that the test wafer can be directly taken out from the machine for processing in the subsequent use process. The test wafer may be reused and the upper limit of the number of uses may be set according to the specific process requirements.
In the related art, if the test wafers need to be used, available test wafers meeting the use requirement (the upper limit value of the use times is not reached) are screened out from a storage area or a cache area, and if the number of the selected available test wafers is insufficient, the machine throws out an alarm of no available test wafers, and the machine is down. When all the test wafers in the machine reach the upper limit value of the use times, the machine throws out the alarm that the test wafers reach the upper limit value of the use times to the control system, so that the automation system can call a new test wafer box to a loading area of the machine, and send a command for replacing the test wafers to the machine, if the machine is in an Idle (Idle) state, the task for replacing the test wafers is directly executed, if the machine is in a process, the program will be in error when the machine is in progress, the machine needs to be manually restored to the Idle (Idle) state from the machine end operation machine when the command is received, and then the machine starts to execute the task for replacing the test wafers when the command for replacing the test wafers, which is sent again by the control system, is received.
As can be seen from the above, the related art requires that the machine should replace the test wafer in an Idle (Idle) state, and if the machine is processing a wafer and the test wafer is insufficient, the task (Job) being performed should be manually ended, so that the machine can be restored to the Idle (Idle) state and then the task of replacing the test wafer can be performed, which seriously reduces the utilization rate and productivity of the machine.
In order to solve the above problems, referring to fig. 3, an embodiment of the present invention provides a test wafer scheduling method in a semiconductor device, including:
s1, dividing a first preset number of test wafers into a plurality of test wafer groups;
the first predetermined number is the number of test wafers stored in the storage area of the semiconductor device, and the number is consistent with the capacity of the cassette, for example, 25 wafers. Taking the first predetermined number of 25 test wafers as an example, the upper limit of the number of test wafer groups may be 4 groups, that is, 25 test wafers may be divided into 4 groups at most. The serial numbers (group IDs) of the 4 test wafer groups are sequentially 1,2,3 and 4. In the configuration, the number of test wafers in the 4-group test wafer group may be set separately, and if the number of groups of divided test wafer groups is less than the upper limit value of the number of groups, the number of test wafers in the corresponding test wafer group may be set to 0 in the order of the number of test wafer groups from back to front, for example, if the number of groups of divided test wafer groups is 3, the number of test wafers in the 4-group test wafer group may be set to 0, the number of test wafers in the other three groups may be set to more than 0, and specifically, the number of test wafers in the 1-group test wafer may be set to 10 pieces; the number of test wafers in the test wafer group numbered 2 may be set to 10; the number of test wafers in the test wafer group numbered 3 may be set to 5; the sum of the numbers of the three test chips numbered 1-3 is equal to 25. In addition, 25 test wafers are sequentially divided into groups according to the wafer number sequence, for example, test wafers numbered slot1 to slot10 are divided into test wafer groups numbered 1; dividing the test wafers numbered slot11 to slot20 into test wafer groups numbered 2; test wafers numbered slot21 through slot25 are divided into test wafer groups numbered 3. That is, the numbers of the test wafers in each test wafer group are consecutive for ease of management.
In some embodiments of the present invention, whether to group or not may also be selected according to an actual process scenario and an application requirement, if not, the number of test wafers in the test wafer group with the number of 1 may be set to the first predetermined number (for example, 25 pieces, and the number of test wafers in the remaining test wafer groups is set to 0, that is, the test wafer scheduling method has two modes, one mode is a grouping mode, and the other mode is a single group mode, in which the number of test wafers in at least two groups of test wafer groups is not zero, and in the single group mode, the number of test wafers in only one group of test wafer groups is not 0, and the number of test wafers in the remaining test wafer groups is 0.
By enabling the test wafer scheduling method to have two modes which can be selected, the two modes can coexist, more and more flexible choices are provided for a user, and the user can freely select to adopt one of the two modes according to own use habits. In addition, since in the single set mode, the alarm is thrown only when the number of available test wafers in all test wafers in the storage area (not grouped) is insufficient to perform the process, the number of alarms is small compared to the alarm thrown when all test wafers in the group of test wafers do not satisfy the use condition in the group mode. Of course, in the grouping mode, the number of alarms may also be reduced by reducing the number of groups of test wafer groups and increasing the number of test wafers in a part of the test wafer groups, for example, if 25 test wafers are divided into two groups, the number of test wafers in the test wafer group numbered 1 may be set to 20; the number of test wafers in the test wafer group numbered 2 may be set to 5. The greater the number of test wafers in the test wafer group, the fewer the number of alarms.
S2, when a process is required to be executed by using a second preset number of test wafers, traversing the plurality of test wafer groups in sequence according to a preset sequence;
in some embodiments of the present invention, before the traversing, the available test wafer sets may be searched from all the test wafer sets, the searched available test wafer sets are sorted according to a preset sequence, and after the sorting, the traversing is performed on all the available test wafer sets.
S3, stopping traversing if the number of the available test wafers obtained through traversal accumulation reaches the second preset number, and executing a process by using the traversed available test wafers;
test wafers that meet the conditions of use are referred to as usable test wafers. The test wafer group including at least one available test wafer is referred to as an available test wafer group. Alternatively, the usage conditions that can be satisfied by the test wafer are, for example, a test wafer whose usage number is smaller than a preset upper limit value and whose usage matches the process. The upper limit value of the number of uses may be, for example, the allowable maximum number of uses (referred to as level 2), or may be a preset value (referred to as level 1) smaller than the allowable maximum number of uses (referred to as level 2). If the preset value is the preset value, a certain modification redundancy can be reserved for manually modifying the upper limit value of the use times under the condition that the test wafer group is temporarily inconvenient to replace, namely, the use times can reach level1 through manually modifying the upper limit value of the use times, but the test wafer which does not reach level2 is converted to meet the use conditions, so that the test wafer group can be continuously put into use.
Specifically, the test wafers stored in the storage area are classified into three types according to different purposes, and the first test wafer is used by Dummy when a process is performed before the first wafer is processed (referred to as "before lot"); the second type of test die is Cleaning, which is used when performing a process after a certain number of wafers are processed (called lot), or when performing a process after the last wafer is processed (called lot); the third type of test die is a MIX, which can be used not only before and during lot, but also when performing the process after the last wafer is processed (called after lot). The above-mentioned three kinds of test wafers are divided into each test wafer group, and the same test wafer group may include one or more kinds of test wafers, which may be set according to actual process scenarios and application requirements.
If the current process requiring the use of the test die is before lot (before processing the first wafer), the Dummy-used test die and the MIX-used test die can be applied before lot; if the current process requiring the use of test dies is in lot (after a certain number of wafers are processed), the test dies for Cleaning and the test dies for MIX can be applied in lot; if the current process requiring the use of test dies is after lot (after the last wafer is processed), both the test dies for Cleaning and the test dies for MIX can be applied after lot. The purpose of the test wafer may be altered by setting.
The second predetermined number is set according to the number of process chambers that need to use the test wafer, for example, if 4 process chambers need to perform a process using the test wafer, the second predetermined number is 4. If the number of available test wafers accumulated in the traversal reaches the second predetermined number, that is, the number of traversed available test wafers is sufficient, the traversal is stopped and the process is performed using the traversed available test wafers.
The traversed available test wafers may belong to the same test wafer group, in which case the number of traversed available test wafers in the test wafer group with the highest priority reaches the second predetermined number. Alternatively, the traversed available test wafers may belong to a plurality of different test wafer groups, in which case the number of available test wafers traversed in the test wafer group with the highest priority is smaller than the second predetermined number, and the next-priority test wafer group needs to be traversed until the number of traversed available test wafers reaches the second predetermined number, that is, if the second predetermined number is greater than the number of available test wafers in one test wafer group, the available test wafers in the multiple groups may be used across groups.
S4, if all the test wafers in the currently traversed test wafer group do not meet the use conditions, replacing the test wafer group.
Optionally, the replacing the test wafer set may specifically include: and prompting the replacement of the test wafer group, and replacing the test wafer group to be replaced when a replacement instruction is received.
For example, currently traversing the test wafer group with the number of 1, if all 10 test wafers with the numbers of slot1 to slot10 do not meet the use conditions, for example, the use times are all greater than a preset upper limit value, prompting to replace the test wafer group, and replacing the test wafer group to be replaced when a replacement instruction is received. The above-mentioned manner of prompting replacement of the test wafer group is, for example, to throw out an alarm that the test wafer needs replacement. The test wafer sets that need to be replaced are not used any more, and the rest of the test wafer sets are continuously traversed according to the preset sequence. The prompt (such as an alarm) may be sent to a control system (such as a factory automation system), for example, and the control system receiving the prompt may automatically invoke a new test wafer box and store it in the loading area of the semiconductor device; the control system also sends a replacement instruction to the semiconductor device; when the replacement instruction is received, the test wafer group to be replaced is replaced, and the replacement task is not interfered with the task of the process in progress of the semiconductor equipment and is synchronously executed.
The grouping use and management of the test wafers can be realized by dividing the first preset number of test wafers into a plurality of test wafer groups, specifically, the plurality of test wafer groups are traversed sequentially according to a preset sequence, if the number of available test wafers obtained by accumulation in the traversal reaches the required number, the traversal is stopped, and the traversed available test wafers are used for executing the process; and if all the test wafers in the currently traversed test wafer group do not meet the use conditions, prompting to replace the test wafer group, and replacing the test wafer group when a replacement instruction is received. Therefore, under the condition that the number of available test wafers is enough, the process can be executed by using the traversed available test wafers, and the test wafer group which does not meet the use conditions of all the test wafers can be replaced, namely, the task of replacing the test wafers is executed in the process of machining the wafers by a machine, the machine is not required to be stopped by manual intervention, and the replacement task is not interfered with the task of the current process, so that the utilization rate of the machine can be improved, and the productivity is improved.
In some embodiments of the present invention, referring to fig. 4, after step S3, that is, after performing a process using the traversed available test wafer, the method further includes:
S5, adding 1 to the use times of each available test wafer for executing the process;
in the above step S5, each test wafer is processed once, and the number of times of use is accumulated by 1.
S6, after the use times of each available test wafer are increased by 1, if all the test wafers in the test wafer group to which the available test wafers belong do not meet the use conditions, replacing the test wafer group.
In the above step S6, for example, the test wafer group to which each available test wafer of the process is belonged may be traversed again, and if all the test wafers do not meet the usage condition (for example, the usage number is greater than the preset upper limit value), the test wafer group is replaced. Likewise, the replacement task is performed in synchronization with the task of the process being performed by the semiconductor device without interfering with each other.
In some embodiments of the invention, after traversing all of the test wafer groups, if the accumulated number of available test wafers has not reached the second predetermined number, then in the event that there is at least one non-matching test wafer, the process is refused to execute and a non-matching test wafer is prompted.
In this case, the test wafers that do not satisfy the use condition include non-matching test wafers, and/or unusable test wafers whose number of uses is greater than or equal to a preset upper limit value.
The unmatched test wafer is a test wafer with the use frequency smaller than or equal to a preset upper limit value and the use and the process are unmatched. For example, if the current process requiring the use of a test die is before lot (before processing the first wafer), then the Dummy-purpose test die may be applied before lot, the test die of this type may be matched to the before lot, and the Cleaning-purpose test die may be unmatched to the before lot.
The refusing to execute the process includes, for example, not executing the task of executing the process issued by the control system and other tasks associated therewith, and feeding back to the control system. When the control system receives the feedback, a new test wafer box is automatically called and stored in the loading area of the semiconductor equipment; the control system also sends a replacement instruction to the semiconductor device; and when the replacement instruction is received, replacing the test wafer group which needs to be replaced.
In practical application, when the test wafer group is inconvenient to replace, the purpose of the unmatched test wafer can be manually changed to be matched with the current process to be performed so as to increase the number of available test wafers to a second preset number, and thus the available test wafers can be used for executing the process when a new issued task is received.
Referring to fig. 5, when a replacement instruction is received, a test wafer set to be replaced is replaced, which specifically includes:
s21, prompting to replace the test wafer group;
s22, when a replacement instruction is received, analyzing and obtaining test wafer information from the replacement instruction;
the test wafer information includes, for example, a first slot number of the cassette in which the new test wafer is located, and a second slot number of the storage area in which the test wafer to be replaced is located.
S23, judging whether the test wafer to be replaced meets the replacement condition, and if so, exchanging the new test wafer with the corresponding test wafer to be replaced according to the test wafer information;
s24, after the test wafers to be replaced are all exchanged, the prompt of replacing the test wafer group is cleared.
The replacing condition includes, for example, that the test wafers to be replaced belong to the same test wafer group, and the number of the second slot of the storage area where the test wafer to be replaced is located corresponds to the number of the first slot of the cassette where the new test wafer is located.
Specifically, referring to fig. 6, in the above step S23, determining whether the test wafer to be replaced meets the replacement condition may include:
s231, judging whether the test wafer to be replaced is executing the process,
If yes, determining that the replacement condition is not met, and refusing to execute the replacement instruction;
if not, executing step S232;
s232, judging whether all the test wafers to be replaced belong to the same test wafer group, and executing step S233 under the condition of belonging to the same test wafer group;
s233, judging whether the number of the test wafers to be replaced is equal to the number of the test wafers contained in the test wafer group, and if so, determining that the replacement condition is met;
if the test wafers do not belong to the same test wafer group or the number of the test wafers to be replaced is not equal to the number of the test wafers contained in the test wafer group, determining that the replacement condition is not met, and refusing to execute the replacement instruction.
In some embodiments of the present invention, referring to fig. 7, in the step S23, exchanging a new test wafer with a corresponding test wafer to be replaced according to the test wafer information includes:
s234, placing a new test wafer in a cassette in a loading area of the semiconductor device;
s235, if the semiconductor equipment has an idle buffer area, transferring the test wafer to be replaced, which corresponds to the number of the second wafer slot, in the storage area to the buffer area;
S236, transferring the new test wafer corresponding to the first wafer slot number to the wafer slot corresponding to the second wafer slot number in the storage area;
s237, the test wafer to be replaced in the buffer area is transferred to the wafer box of the loading area.
In some embodiments of the present invention, after the step S1, i.e. after dividing the first predetermined number of test wafers into the plurality of test wafer groups, the method further includes:
different priorities are set for the plurality of test wafer sets.
In this case, in the above step S2, the preset order is an order in which the priority is from high to low.
The rule for setting the initial priority of the plurality of test wafer groups is, for example, that the higher the number value is, the lower the priority is. Taking the first predetermined number of 25 test wafers as an example, the upper limit of the number of test wafer groups may be 4, the priority of the test wafer group with number 1 is the highest, called 1, the priority of the test wafer group with number 2 is called 2, the priority of the test wafer group with number 3 (if any) is called 3, and the priority of the test wafer group with number 4 (if any) is the lowest, called 4. Of course, in practical applications, other rules may be used to set the initial priority of multiple test wafer sets according to specific needs.
Further optionally, after replacing the test wafer group, further comprising:
s7, setting the priority of the replaced test wafer group to be the lowest, and increasing the priority of the test wafer group without prompt by one level; the priority of the test wafer group with the hint but not replaced remains unchanged.
Optionally, the prompt to complete the replacement test wafer set is cleared.
Specifically, referring to fig. 8, the step S7 specifically includes:
s71, circularly traversing all test wafers stored in a storage area of the semiconductor device;
information of all the test wafers stored in the storage area is prestored in a machine system (for example, in a machine system configuration file), and the information comprises numbers and priorities of test wafer groups to which the test wafers in the storage area belong. In step S71, all the test wafers stored in the storage area may be circulated through in order of the numbers of the test wafers from small to large.
S72, judging whether the number of the test wafer group to which each test wafer belongs obtained through traversing is the same as the number of the test wafer group which is replaced currently;
if the priority of the current replaced test wafer group is the same, setting the priority of the current replaced test wafer group to be the lowest;
if not, executing step S73;
S73, judging whether the test wafer groups of the test wafers in the storage area are prompted to be replaced or not, if so, keeping the priority of the test wafer groups unchanged; if not, the priority of the test wafer group is increased by one step.
In the step S72, the number of the currently replaced test wafer may be obtained according to the test wafer information, for example, if the number of the second slot of the storage area where the test wafer to be replaced is located is 1-10, which indicates that the test wafers numbered from slot1 to slot10 in the storage area need to be replaced, and the numbers of the test wafer groups to which all the test wafers in the storage area belong are stored in the machine system configuration file, and when the step S72 is executed, the numbers of the test wafer groups to which the test wafers numbered from slot1 to slot10 belong may be queried from the file, and the test wafer group is the currently replaced test wafer group.
In a specific embodiment, as shown in fig. 9, a test wafer scheduling method provided by an embodiment of the present invention includes:
s101, when a semiconductor wafer starts to be processed (the process is called as Lot run stock), judging whether a process (the process is called as run dummy) needs to be performed by using a test wafer; if not, executing step S102; if yes, go to step S103;
S102, continuously executing Lot run goods;
s103, searching from divided multiple groups of test wafer groups (Dummy groups) to obtain all available test wafer groups;
s104, sorting all available test wafer groups according to the order of the priority from high to low;
s105, traversing all available test wafer groups after sequencing;
s106, judging whether the number of the accumulated available test wafers is enough, if so, ending the traversing, and executing a process (called executing dummy) by using the traversed available test wafers; if not, executing step S108;
s107, after the dummy process is completed, adding 1 to the number of times of use of each available test wafer for executing the process, and judging whether the total number of the test wafer groups to which the test wafer groups belong reaches the upper limit value (level 1) of the number of times of use; if yes, the alarm is thrown out while the Lot run cargo is continued, and the test wafer group is informed of the need of replacement (the process becomes dummy exchange), so that the factory automation system issues a replacement instruction after receiving the alarm; then, when receiving the replacement instruction, executing the replacement process of the test wafer group while continuing the Lot cargo;
s108, judging whether all the members of the currently traversed test wafer group reach the upper limit value (level 1) of the using times; if yes, an alarm is thrown out, and the test wafer group is informed of the need of replacement, so that the factory automation system issues a replacement instruction after receiving the alarm; then, when the replacement instruction is received, executing a replacement process of the test wafer group; if not, executing step S109;
S109, judging whether each available test wafer group is traversed; if yes, throwing an alarm to prompt that a non-matched test wafer exists, namely, the using times are smaller than a preset upper limit value, and the test wafer which is not matched with the process is used, and rejecting to execute the process (reject job); if not, the process returns to step S105.
In another specific embodiment, as shown in fig. 10, the test wafer scheduling method provided by the embodiment of the present invention includes:
s201, when the processing of a semiconductor wafer is started (the process is called Lot run stock), judging whether a process (the process becomes run dummy) needs to be performed by using a test wafer; if yes, go to step S202; if not, continuing to execute the Lot run cargo;
s202, judging whether a test wafer (Dummy wafer) is managed in multiple groups, if yes, executing step S203; if not, executing step S210;
s203, searching from divided multiple groups of test wafer groups (Dummy groups) to obtain all available test wafer groups;
s204, sorting all available test wafer groups according to the order of the priority from high to low;
s205, traversing all available test wafer groups after sequencing;
s206, judging whether the number of the accumulated available test wafers is enough, if so, ending the traversing, and executing a process (called executing dummy) by using the traversed available test wafers; if not, executing step S108;
S207, after the dummy process is completed, adding 1 to the number of times of use of each available test wafer for executing the process, and judging whether the total number of the test wafer groups to which the test wafer groups belong reaches the upper limit value (level 1) of the number of times of use; if yes, the alarm is thrown out while the Lot run cargo is continued, and the test wafer group is informed of the need of replacement (the process becomes dummy exchange), so that the factory automation system issues a replacement instruction after receiving the alarm; then, when receiving the replacement instruction, executing the replacement process of the test wafer group while continuing the Lot cargo;
s208, judging whether all the members of the currently traversed test wafer group reach the upper limit value (level 1) of the using times; if yes, an alarm is thrown out, and the test wafer group is informed of the need of replacement, so that the factory automation system issues a replacement instruction after receiving the alarm; then, when the replacement instruction is received, executing a replacement process of the test wafer group; if not, executing step S209;
s209, judging whether each available test wafer group is traversed; if yes, throwing an alarm to prompt that a non-matched test wafer exists, namely, the using times are smaller than a preset upper limit value, and the test wafer which is not matched with the process is used, and rejecting to execute the process (reject job); if not, the process returns to step S205.
S210, judging whether the test wafers reaching the upper limit value (level 1) of the using times in the storage area (not grouped) are enough (more than or equal to a second preset number); if yes, performing a process (called performing dummy) using the test wafer; if not, executing step S211;
s211, judging whether all the test wafers in the storage area reach the upper limit value (level 1) of the using times, if so, throwing an alarm, and informing that all the test wafers in the storage area need to be replaced, so that the factory automation system sends a replacement instruction after receiving the alarm; then, when the replacement instruction is received, executing a replacement process of the test wafer group; if not, searching for a test wafer with the usage number reaching the upper limit value (level 1) of the usage number, but not reaching the allowable maximum usage number (level 2, which is greater than level 1), and executing step S212;
s212, if the sum of the number of the test wafers with the use times not reaching the upper limit value (level 1) of the use times and the number of the test wafers with the use times reaching the upper limit value (level 1) of the use times but not reaching the allowable maximum use times (level 2) is enough (more than or equal to the second preset number), executing a process (called executing dummy) by using the test wafers; if not, an alarm is thrown out, and no usable test wafer is reported, and the machine is down.
The usage rate of the test wafer group can be balanced by setting the priority of the replacement test wafer group to be the lowest and increasing the priority of the test wafer group without hint by one step. By keeping the priority of the test wafer group with the prompt but not replaced unchanged, the parameters of the test wafers in the test wafer group can be manually changed under the condition that the test wafers are inconvenient to replace, for example, the upper limit value of the using times of the test wafers is changed to meet the using condition, so that the test wafer group can be continuously put into use, and the prompt of replacing the test wafer group can be cleared by the test wafer group to which the test wafer group belongs.
In addition, the test wafer scheduling method in fig. 10 is added with steps S202 and S210 to S212 as compared with the test wafer scheduling method in fig. 9, i.e., it is possible to select whether to perform group management on test wafers (Dummy wafers), and when group management is not performed, determine whether to perform a process according to the number of available test wafers in a storage area (not grouped), and when the available test wafers are insufficient to perform the process, replace all the test wafers in the storage area (not perform the process).
By adding the selection of whether to conduct the grouping management on the test wafers (Dummy wafers), the two modes of grouping management and non-grouping management can be combined, more and more flexible choices are provided for users, and the users can freely select whether to conduct the grouping management on the test wafers (Dummy wafers) according to own use habits. In addition, since the alarms are thrown only when the number of available test wafers in all test wafers in the storage area (not grouped) is insufficient to perform the process when the grouping management is not performed, the number of alarms is small compared with the case where the alarms are thrown when all test wafers in the test wafer group do not satisfy the use condition when the grouping management is performed. Of course, in the case of performing grouping management, the number of alarms may be reduced by reducing the number of test wafer groups and increasing the number of test wafers in a part of the test wafer groups, for example, if 25 test wafers are divided into two groups, the number of test wafers in the test wafer group numbered 1 may be set to 20; the number of test wafers in the test wafer group numbered 2 may be set to 5. The greater the number of test wafers in the test wafer group, the fewer the number of alarms.
As another technical solution, referring to fig. 11, the embodiment of the present invention further provides a test wafer scheduling apparatus, which includes a grouping module 1, a searching module 2, and a traversing module 3, where the grouping module 1 is configured to divide a first predetermined number of test wafers into a plurality of test wafer groups; the traversing module 2 is used for sequentially traversing the plurality of test wafer groups according to a preset sequence when a process is required to be executed by using a second preset number of test wafers; the control module 3 is configured to control the traversing module to stop traversing when the number of the accumulated available test wafers reaches a second predetermined number, and execute a process using the traversed available test wafers; the available test wafer is a test wafer meeting the use conditions; and the device is also used for prompting the replacement of the test wafer group when all the test wafers in the currently traversed test wafer group do not meet the use conditions, and replacing the test wafer group to be replaced when a replacement instruction is received.
In summary, in the technical solution of the test wafer scheduling method and apparatus provided in the embodiments of the present invention, the first predetermined number of test wafers are divided into a plurality of test wafer groups, so that the grouping use and management of the test wafers can be implemented, specifically, by sequentially traversing the plurality of test wafer groups according to a preset sequence, if the number of available test wafers obtained by accumulation during the traversing reaches the required number, stopping the traversing, and executing a process using the traversed available test wafers; and if all the test wafers in the currently traversed test wafer group do not meet the use conditions, prompting to replace the test wafer group, and replacing the test wafer group when a replacement instruction is received. Therefore, under the condition that the number of available test wafers is enough, the process can be executed by using the traversed available test wafers, and the test wafer group which does not meet the use conditions of all the test wafers can be replaced, namely, the task of replacing the test wafers is executed in the process of machining the wafers by a machine, the machine is not required to be stopped by manual intervention, and the replacement task is not interfered with the task of the current process, so that the utilization rate of the machine can be improved, and the productivity is improved.
As another technical solution, an embodiment of the present invention further provides a semiconductor device, which includes a plurality of process chambers and a storage area storing a first predetermined number of test wafers, and the test wafer dispatching apparatus provided by the embodiment of the present invention.
The semiconductor device provided by the embodiment of the invention can execute the task of replacing the test wafer in the process of processing the wafer by the machine without manual intervention and shutdown, and the task of replacing the test wafer is not interfered with the task of the current process, so that the utilization rate of the machine can be improved, and the productivity can be improved.
Fig. 12 is a block diagram of a test wafer scheduler according to an embodiment of the present invention, and as shown in fig. 12, the test wafer scheduler is configured to schedule a first predetermined number of test wafers in a semiconductor device, and includes: at least one processor 101, memory 102, at least one I/O interface 103. The memory 102 has stored thereon at least one program which, when executed by the at least one processor 101, causes the at least one processor to implement the steps of any of the methods as in the embodiments described above; at least one I/O interface 103 is coupled between the processor 101 and the memory 102 and is configured to facilitate information interaction between the processor and the memory.
Wherein the processor 101 is a device having data processing capabilities, including but not limited to a Central Processing Unit (CPU) or the like; memory 102 is a device with data storage capability including, but not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically charged erasable programmable read-only memory (EEPROM), FLASH memory (FLASH); an I/O interface (read/write interface) 103 is connected between the processor 101 and the memory 102 to enable information interaction between the processor 101 and the memory 102, including but not limited to a data Bus (Bus) or the like.
In some embodiments, processor 101, memory 102, and I/O interface 103 are connected to each other via bus 104, and thus to other components of the computing device.
In some embodiments, the processor 101 comprises an FPGA.
According to an embodiment of the present disclosure, there is also provided a computer-readable medium. The computer readable medium has stored thereon a computer program, wherein the program when executed by a processor performs the steps of the test wafer scheduling method according to any of the above embodiments.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a machine-readable medium, the computer program comprising program code for performing the method shown in the flow diagrams. In such embodiments, the computer program may be downloaded and installed from a network via a communication portion, and/or installed from a removable medium. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU).
It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (13)
1. A test wafer scheduling method in a semiconductor device, comprising:
dividing a first predetermined number of test wafers into a plurality of test wafer groups;
when a process is required to be executed by using a second preset number of the test wafers, traversing the plurality of test wafer groups in sequence according to a preset sequence;
stopping traversing if the number of the available test wafers obtained through traversing reaches the second preset number, and executing a process by using the traversed available test wafers; the available test wafer is a test wafer meeting the use conditions;
and if all the test wafers in the currently traversed test wafer group do not meet the use conditions, replacing the test wafer group.
2. The test wafer scheduling method of claim 1, further comprising, after performing a process using the traversed available test wafer:
adding 1 to the number of times of use of each available test wafer for executing the process;
after the use times of each available test wafer are increased by 1, if all the test wafers in the test wafer group to which the available test wafers belong do not meet the use conditions, the test wafer group is replaced.
3. The method of claim 1, wherein the available test wafers satisfying the usage conditions are test wafers having a usage number smaller than a predetermined upper limit and a usage matching a process.
4. The test wafer scheduling method according to claim 1, wherein after traversing all of the test wafer groups, if the accumulated number of available test wafers does not reach the second predetermined number, if there is at least one non-matching test wafer, rejecting execution of the process and prompting the presence of the non-matching test wafer;
the unmatched test wafer is used for a number of times smaller than a preset upper limit value, and the usage and the process are unmatched.
5. The test wafer dispatching method of any one of claims 1-4, wherein the replacing the test wafer group comprises:
prompting replacement of the test wafer set;
when a replacement instruction is received, analyzing and obtaining test wafer information from the replacement instruction;
judging whether the test wafer to be replaced meets the replacement condition, if so, exchanging a new test wafer with the corresponding test wafer to be replaced according to the test wafer information;
After the test wafers to be replaced have all been exchanged, the prompt for replacing the set of test wafers is cleared.
6. The test wafer dispatching method of claim 5, wherein the determining whether the test wafer to be replaced satisfies a replacement condition comprises:
it is determined whether a test wafer to be replaced is performing a process,
if yes, determining that the replacement condition is not met, and refusing to execute the replacement instruction;
if not, judging whether all the test wafers to be replaced belong to the same test wafer group, and if so, judging whether the number of the test wafers to be replaced is equal to the number of the test wafers contained in the test wafer group, and if so, determining that the replacement condition is met;
if the test wafers do not belong to the same test wafer group or the number of the test wafers to be replaced is not equal to the number of the test wafers contained in the test wafer group, determining that the replacement condition is not met, and refusing to execute the replacement instruction.
7. The test wafer scheduling method of claim 5, wherein the test wafer information includes a first slot number of a cassette in which a new test wafer is located, and a second slot number of a storage area of the semiconductor device in which a test wafer to be replaced is located;
And exchanging the new test wafer with the corresponding test wafer to be replaced according to the test wafer information, comprising:
after a new test wafer box is placed in a loading area of the semiconductor device, if an idle buffer area exists in the semiconductor device, transferring the test wafer to be replaced, corresponding to the second wafer slot number, in the storage area into the buffer area;
transferring a new test wafer corresponding to the first wafer slot number to the wafer slot corresponding to the second wafer slot number in the storage area;
and transferring the test wafer to be replaced in the buffer area to the wafer box of the loading area.
8. The test wafer scheduling method of any one of claims 1-4, further comprising, after said dividing the first predetermined number of test wafers into a plurality of test wafer groups:
setting different priorities for a plurality of the test wafer groups;
the preset sequence is the sequence from high priority to low priority.
9. The test wafer dispatch method of claim 8, further comprising, after said replacing the test wafer group:
Setting the priority of the replaced test wafer group to be the lowest, and increasing the priority of the test wafer group without prompt by one level; the priority of the test wafer group with the hint but not replaced remains unchanged.
10. The test wafer dispatching method of claim 9, wherein the priority of the replaced test wafer group is set to be lowest, and the priority of the test wafer group without hint is increased by one step; the priority of the test wafer group with the prompt but not replaced remains unchanged, comprising:
cycling through all test wafers stored in a storage area of the semiconductor device;
judging whether the number of the test wafer group to which each test wafer obtained through traversing belongs is the same as the number of the test wafer group after current replacement,
if the priority of the current replaced test wafer group is the same, setting the priority of the current replaced test wafer group to be the lowest;
if the test wafer groups are different, judging whether the test wafer groups of the test wafers in the storage area are prompted to be replaced, and if so, keeping the priority of the test wafer groups unchanged; if not, the priority of the test wafer group is increased by one level.
11. A test wafer scheduler for scheduling a first predetermined number of test wafers in a semiconductor device, the test wafer scheduler comprising at least one processor and at least one memory, the memory having at least one program stored therein;
The at least one program, when executed by the at least one processor, causes the at least one processor to implement the method of any of claims 1-10.
12. A semiconductor apparatus comprising a plurality of process chambers and a storage area storing a first predetermined number of test wafers, further comprising:
the test wafer handler of claim 11.
13. A computer readable storage medium for a semiconductor processing apparatus, having stored thereon a computer program, which when executed by a processor, implements a method according to any of claims 1-10.
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| PCT/CN2024/113277 WO2025040071A1 (en) | 2023-08-22 | 2024-08-20 | Dummy wafer scheduling method and apparatus, and semiconductor device |
| TW113131248A TWI892802B (en) | 2023-08-22 | 2024-08-20 | Scheduling method and device of test wafer and semiconductor device |
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| JP3730651B2 (en) * | 2004-08-20 | 2006-01-05 | 株式会社日立国際電気 | Semiconductor manufacturing apparatus and method |
| JP5921200B2 (en) * | 2012-01-05 | 2016-05-24 | 株式会社日立国際電気 | Substrate processing apparatus, substrate processing method, semiconductor device manufacturing method, degenerate operation program, and production list creation program |
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| CN114883222B (en) * | 2022-05-07 | 2025-11-11 | 北京北方华创微电子装备有限公司 | Wafer scheduling method and device and semiconductor process equipment |
| CN116978829A (en) * | 2023-08-22 | 2023-10-31 | 北京北方华创微电子装备有限公司 | Test wafer scheduling method, apparatus and semiconductor equipment |
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