CN116978801A

CN116978801A - A chip packaging method and packaging structure

Info

Publication number: CN116978801A
Application number: CN202310922313.1A
Authority: CN
Inventors: 谢庭杰; 庄佳铭; 李尚轩; 王雪
Original assignee: Nantong Tongfu Technology Co ltd
Current assignee: Nantong Tongfu Technology Co ltd
Priority date: 2023-07-26
Filing date: 2023-07-26
Publication date: 2023-10-31

Abstract

Embodiments of the present disclosure provide a chip packaging method and packaging structure, including: providing a carrier board and a chip, with a conductive connector provided on the first surface of the chip; forming a rewiring layer on the first surface of the carrier board, and forming a rewiring layer on the first surface of the chip. forming conductive bumps in the central area of the redistribution layer, and forming conductive pillars in the edge areas of the redistribution layer; fixing the first surface of the chip to the first surface of the carrier board, and electrically connecting the conductive connectors to the conductive bumps; counterweighting the rewiring The layers, conductive pillars and chips are plastic-packed to form a plastic-packing unit; multiple plastic-packing units are stacked sequentially on the carrier board; two adjacent plastic-packing units are electrically connected through the corresponding conductive posts; the carrier board is removed , forming solder balls on the exposed rewiring layer of the bottom plastic packaging unit to obtain a target package. The disclosed interconnection lines formed by rewiring layers and conductive pillars for each layer of the chip reduce the packaging cost and improve the quality and production efficiency of the packaged product.

Description

Chip packaging method and packaging structure

Technical Field

The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging method and a chip packaging structure.

Background

In the semiconductor packaging industry, 3D packages have the problem of through silicon vias (TSV, throughSilicon Via). In this advanced packaging method, not only a 10 μm-sized silicon interposer is required, but also metal is inserted through holes in a wafer with transistors, so that the difficulty is high, the technology is not mature, and the cost is high.

In a typical TSV through-silicon-via 3D package, advanced nodes are connected by TSV structures, and thus the wafer size, interconnect length, and shape are limited. As electronic devices such as mobile phones are smaller, more wafers must be stacked and the size of the devices is reduced, so that the cost of TSV is not suitable for mobile market.

Disclosure of Invention

The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a chip packaging method and a packaging structure.

One aspect of the disclosed embodiments provides a chip packaging method. The method

Comprising the following steps:

providing a carrier plate and a chip, wherein a conductive connecting piece is arranged on the first surface of the chip;

forming a re-wiring layer on the first surface of the carrier, forming a conductive bump in a central region of the re-wiring layer, and forming a conductive post in an edge region of the re-wiring layer;

fixing the first surface of the chip on the first surface of the carrier plate, wherein the conductive connecting piece is electrically connected with the conductive bump;

performing plastic packaging on the rewiring layer, the conductive columns and the chip to form a plastic packaging unit;

sequentially stacking a plurality of plastic packaging units on the carrier plate; wherein two adjacent plastic packaging units are electrically connected through the corresponding conductive columns;

and removing the carrier plate, and forming solder balls on the rewiring layer exposed out of the plastic packaging unit at the bottom layer to obtain the target packaging body.

Optionally, the forming a redistribution layer on the first surface of the carrier, forming a conductive bump in a central area of the redistribution layer, and forming a conductive pillar in an edge area of the redistribution layer includes:

forming a first passivation layer on the first surface of the carrier, patterning the first passivation layer to form first openings in the central area and the edge area of the first passivation layer, and forming a metal wiring layer on the surface of the first passivation layer and the first openings;

and forming a second passivation layer on the first passivation layer, patterning the second passivation layer to form second openings in the central region and the edge region of the second passivation layer, and forming the conductive bumps and the conductive columns in the second openings.

Optionally, the first openings and the second openings in the central area are staggered, and the first openings and the second openings in the edge area are correspondingly arranged.

Optionally, before the plastic packaging of the redistribution layer, the conductive pillars, and the chip, the method further includes:

and forming underfill between the rewiring layer and the chip.

Optionally, the plastic packaging the redistribution layer, the conductive pillars and the chip to form a plastic packaging unit includes:

forming a plastic sealing layer which wraps the rewiring layer, the conductive columns and the chip;

and thinning the surface of the plastic sealing layer, which faces away from the carrier plate, until the second surface of the chip and the conductive column are exposed, so as to obtain the plastic sealing unit.

Optionally, an end of the conductive pillar facing away from the rewiring layer is higher than the second surface of the chip.

Optionally, before forming the redistribution layer on the first surface of the carrier plate, the method further includes: forming a release layer on a first surface of the carrier plate, and forming the rewiring layer on the release layer;

before forming the solder balls on the rewiring layer exposed by the plastic packaging unit at the bottom layer, the method further comprises the following steps: and removing the release layer.

Another aspect of an embodiment of the present disclosure provides a chip package structure. Including a plurality of plastic packaging units that stack gradually, the plastic packaging unit includes: the semiconductor package comprises a rewiring layer, a chip, a plastic sealing layer, a conductive bump positioned in the central area of the rewiring layer and a conductive column positioned in the edge area of the rewiring layer;

the first surface of the chip is provided with a conductive connecting piece, and the conductive connecting piece is electrically connected with the conductive bump;

the plastic layer is arranged on the rewiring layer, the conductive column and the chip;

and two adjacent plastic packaging units are electrically connected through the corresponding conductive columns, and solder balls are arranged on the rewiring layer exposed out of the plastic packaging units at the bottom layer.

Optionally, the conductive connecting piece comprises a conductive block, a conductive bump and a solder bump; the conductive block is arranged on the first surface of the chip, the conductive convex points and the welding blocks are sequentially arranged on the conductive block, and the welding blocks are electrically connected with the conductive convex blocks.

The plastic sealing layer optionally further comprises: filling glue; the underfill is between the redistribution layer and the chip.

In the chip packaging method of the embodiment of the disclosure, the chip is flipped to form the rewiring layer, and interconnection between stacked chips is realized through the rewiring layer and the conductive bumps and the conductive columns on the rewiring layer, so that the interconnection length is greatly shortened, and the chip size is not limited; the chips of each layer are connected by the rewiring layer, so that the packaging cost is reduced, compared with the transmission of power from the wires in the TSVs to the top of the chips, the connection of the conductive columns can provide better transmission power, the original form of the packaging structure can be well maintained, and the packaging structure is suitable for high-density chip packaging.

Drawings

Fig. 1 is a schematic flow chart of a chip packaging method according to an embodiment of the disclosure;

fig. 2 to 14 are process diagrams of a chip packaging method according to an embodiment of the disclosure.

In the figure:

100. a carrier plate; 200. a chip; 210. a conductive connection; 211. a conductive block;

212. conductive bumps; 213. welding blocks; 300. a rewiring layer; 310. a first passivation layer;

311. a first opening; 320. a metal wiring layer; 330. a second passivation layer; 331. a second opening; 400. conductive bumps; 500. a conductive post; 600. filling glue; 700. a plastic sealing layer; 800. a plastic packaging unit; 810. solder balls; 900. a release layer.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.

Referring to fig. 1, fig. 1 is a flow chart of a chip packaging method according to an embodiment of the disclosure, and the embodiment of the disclosure relates to a chip packaging method, where the method S100 includes:

step S110, a carrier plate and a chip are provided, wherein a conductive connecting piece is arranged on the first surface of the chip.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of a carrier and a chip. The material of the carrier 100 may be one of glass, silicon, ceramic, resin, sapphire, etc. The chip 200 may be a silicon chip, and the first surface of the chip 200 may be the front surface or the back surface of the chip 200, and the first surface is provided with conductive connectors 210.

Step S120, forming a redistribution layer on the first surface of the carrier, forming a conductive bump in a central area of the redistribution layer, and forming a conductive pillar in an edge area of the redistribution layer.

Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of the carrier after the redistribution layer, the conductive bump and the conductive pillar are formed on the first surface of the carrier. The redistribution layer 300 is formed on the carrier 100, then the conductive bump 400 is formed in the central area of the redistribution layer 300, and the conductive pillar 500 is formed in the edge area of the redistribution layer 300.

In the chip packaging method of the embodiment of the disclosure, interconnection among stacked chips is realized through the rewiring layer, the conductive bumps and the conductive columns on the rewiring layer, so that the interconnection length is greatly shortened; compared with the method that TSVs are arranged in a silicon medium to interconnect chips, the method saves cost and is simple and convenient to process; the method is not influenced by the silicon interposer, the rewiring layer can be arranged according to actual needs, and the size of the chip is not limited. And compared with the method that the conductive posts are directly arranged on the chip, the conductive posts are formed on the rewiring layer, and the cost is lower.

In an embodiment, before forming the redistribution layer on the first surface of the carrier plate, the method further comprises: and forming a release layer on the first surface of the carrier plate, and forming the rewiring layer on the release layer.

Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of a carrier plate forming a release layer. The Release layer (Release layer) serves to temporarily bond the carrier plate and the rewiring layer. The release layer 900 may be a temporary bonding adhesive, which is formed by adding an auxiliary agent into a basic adhesive material in a mixing ratio, and may be used as a high polymer material of the basic adhesive material, including thermoplastic resin, thermosetting resin, photoresist, etc. The main modes of temporary bonding are both thermal curing and Ultraviolet (UV) curing.

In an embodiment, referring to fig. 4 to 8, fig. 4 to 8 are process diagrams for forming a redistribution layer, a conductive bump and a conductive pillar on a first performance of the carrier in the embodiment of the disclosure, where the step S120 specifically includes:

step S121, forming a first passivation layer on the first surface of the carrier, patterning the first passivation layer to form first openings in a central region and an edge region of the first passivation layer, and forming a metal wiring layer on the surface of the first passivation layer and the first openings.

Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of a first passivation layer and a first opening formed on the carrier. The present disclosure forms a first passivation layer 310 on the first surface of the carrier plate 100 by using an atomic layer deposition (Atomic Layer Deposition, ALD) or a Plasma Enhanced CVD (PECVD) method, where the material of the first passivation layer is one or more of aluminum oxide, silicon nitride or silicon oxynitride. And the first passivation layer is provided with a first opening 311 which is obtained by adopting patterning treatment processes such as photoresist coating, exposure, development, etching and the like. After removing the photoresist, a first metal film (not shown) may be formed on the surface of the first passivation layer 310 and the first opening 311 by physical vapor deposition (Physical Vapor Deposition, PVD), and the first metal film may be a titanium copper alloy or the like, which is not limited herein.

As shown in fig. 5, fig. 5 is a schematic structural diagram of the first passivation layer on the carrier with a metal wiring layer formed thereon, the surface of the first passivation layer 310 and the first opening 311 are coated with photoresist again, exposed, developed, and the like to form a pattern of the metal wiring layer, the metal wiring layer 320 is formed by electroplating, the photoresist is removed, and the first metal film is etched. The metal wiring layer 320 is made of copper.

Step S122, forming a second passivation layer on the first passivation layer, patterning the second passivation layer to form second openings in a central region and an edge region of the second passivation layer, and forming the conductive bumps and the conductive pillars in the second openings.

The conductive bump 400 and the conductive pillar 500 of the embodiment of the present disclosure are electrically connected to the metal wiring layer 320, the conductive bump 400 is located in a central region, and the conductive pillar 500 is located in an edge region.

Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of a second passivation layer and a second opening formed on the carrier. The second passivation layer 330 and the second opening 331 are formed by the same method as in step S121, and the material of the second passivation layer 330 is the same as the material of the first passivation layer 310. The second openings 331 are distributed in a central region and an edge region of the second passivation layer 330. After removing the photoresist, a second metal film (not shown) is formed on the surface of the second passivation layer 330 and the second opening 331 by physical vapor deposition (Physical Vapor Deposition, PVD), and the material of the second metal film is the same as that of the first metal film, but not limited thereto. As shown in fig. 7, fig. 7 is a schematic structural diagram of the second passivation layer on the carrier with conductive bumps formed thereon, the surface of the second passivation layer 330 and the second opening 331 are coated with photoresist again, exposed, developed, and the like to obtain a pattern of the conductive bumps, and the conductive bumps 400 are formed by electroplating. The conductive bump 400 may be made of Ni.

As shown in fig. 8, fig. 8 is a schematic structural diagram of the second passivation layer on the carrier with conductive pillars formed thereon. Removing photoresist, re-coating Dry film on the surface of the second passivation layer 330 and the second opening 331, performing patterning treatment such as exposure and development to obtain a pattern of a conductive column, and electroplating to obtain a thick gold layer at the exposed position to obtain the conductive column 500, wherein the conductive column 500 is made of copper which is the same as the metal wiring layer, and the Dry film is removed by using a Dry film removing liquid medicine, excessive copper is etched by using a chemical copper etching liquid medicine, and the second metal film is etched.

In an embodiment, as shown in fig. 8, the first openings and the second openings in the central area are staggered, and the first openings and the second openings in the edge area are correspondingly arranged.

In the chip packaging method of the embodiment of the present disclosure, the positions of the first opening 311 and the second opening 331 may be set according to actual needs, where the first opening 311 and the second opening 331 located in the edge area are correspondingly set, so that when the later-stage chip 200 is stacked, the conductive pillars 500 may connect adjacent rewiring layers 300.

Step S130, fixing the first surface of the chip on the first surface of the carrier, where the conductive connecting member is electrically connected to the conductive bump.

Specifically, referring to fig. 9, fig. 9 is a schematic structural diagram of connection between a chip and a carrier in an embodiment of the disclosure. The conductive bump 400 is used for electrically connecting with the conductive connection 210 of the chip 200.

The conductive connection member 210 includes a conductive bump 211, a conductive bump 212, and a solder bump 213; the conductive bump 211 is disposed on the first surface of the chip 200, the conductive bump 212 and the solder bump 213 are sequentially disposed on the conductive bump 211, and the solder bump 213 is electrically connected to the conductive bump 400. The material of the conductive bump is copper Cu, the material of the conductive bump may be the same as the material of the conductive bump, both are nickel Ni, and the material of the solder bump is tin Sn, which is not limited herein. The first surface of the chip 200 is formed with a copper block, a nickel bump (UBM) is formed on the copper block, a tin block is formed on the nickel bump, and each conductive connection piece 210 is provided with a Solder bump (Solder) and is connected with the conductive bump 400 (PAD) on the surface of the redistribution layer 300 by means of Solder bonding, so that a good soldering effect can be achieved.

And step 140, performing plastic packaging on the rewiring layer, the conductive columns and the chip to form a plastic packaging unit.

In an embodiment, referring to fig. 10, fig. 10 is a process diagram of forming underfill between the redistribution layer and the chip, and before the plastic packaging of the redistribution layer, the conductive pillars and the chip, the method further includes:

and forming underfill between the rewiring layer and the chip.

In order to stabilize the chip 200, an underfill process (Under fill) may be used at a wafer level, forming an underfill 600 (Under fill) reinforcement between the redistribution layer 300 and the chip 200. Specifically, underfill 600 is filled between the redistribution layer 300 and the chip 200, the underfill 600 surrounds the conductive connectors 210 of the chip 200, and the filling thickness is equal to the distance between the chip 200 and the redistribution layer 300, so that the resulting underfill layer can support the chip 200.

According to the embodiment of the disclosure, the underfill (underfill) is injected into the bottom of the chip, so that the problem of packaging reliability caused by different thermal expansion coefficients between the chip and the carrier plate is solved, and poor contact caused by breakage of the conductive connecting piece in reflow soldering is avoided.

In an embodiment, referring to fig. 11 and 12, fig. 11 to 12 are process diagrams of plastic packaging the redistribution layer, the conductive pillars and the chip in the embodiment of the disclosure, where the step S140 specifically includes:

and step S141, forming a plastic sealing layer which wraps the rewiring layer, the conductive posts and the chip.

Specifically, the plastic sealing layer 700 may be made of rubber or the like, and the plastic sealing layer fills the gap between the conductive post and the chip, the plastic sealing layer realizes secondary reinforcement of the chip and fixes the conductive post,

and S142, thinning the surface of the plastic sealing layer, which is away from the carrier plate, until the conductive posts are exposed, so as to obtain the plastic sealing unit.

In this embodiment of the disclosure, the overall size of the plastic sealing unit 800 is smaller, and the surface of the plastic sealing layer 700 facing away from the carrier 100 may be thinned by grinding until the conductive pillars 500 are exposed.

In one embodiment, as shown in fig. 12, an end of the conductive pillar 500 facing away from the redistribution layer 300 is higher than the second surface of the chip 200.

Specifically, one end of the conductive pillar 500 facing away from the redistribution layer 300 is higher than the second surface of the chip 200, and only the conductive pillar 500 is exposed when the conductive pillar is thinned, so that the plastic package unit 800 can be obtained.

Step S150, stacking a plurality of plastic packaging units on the carrier plate in sequence; wherein two adjacent plastic package units are electrically connected through the corresponding conductive columns.

Specifically, referring to fig. 13, fig. 13 is a schematic structural diagram of a stacked plurality of the plastic packaging units according to an embodiment of the disclosure. The first opening 311 located in the edge area is disposed corresponding to the second opening 331, so that the conductive pillar 500 is formed in the second opening 331 in the edge area, and interconnection between the conductive pillar 500 and two adjacent plastic packaging units 800 can be achieved.

And step 160, removing the carrier plate, and forming solder balls on the rewiring layer exposed by the plastic packaging unit at the bottom layer to obtain the target package body.

Specifically, referring to fig. 14, fig. 14 is a schematic structural diagram of a target package according to an embodiment of the disclosure. After removing the carrier 100, C4 solder balls 810 are formed on the metal wiring layer 320 exposed by the plastic packaging unit 800 at the bottom layer. More specifically, bump metal layers (UBM, under bump metallization) are formed on the metal wiring layers, the bump metal layers are manufactured by adopting the same technological process as RDL, and then ball implantation is performed on the corresponding bump metal layers, so that the target package is obtained. The bump metal layer is made of the same material as the conductive bump and the conductive bump, and is made of nickel Ni. The solder balls are made of tin Sn, and the solder balls and the solder blocks are made of the same material. The target package may be electrically connected to an external circuit through solder balls.

In an embodiment, before forming the solder balls on the rewiring layer exposed by the plastic packaging unit of the bottom layer, the method further comprises: and removing the release layer.

Specifically, the release layer 900 may be peeled off by laser debonding or thermal bonding.

In the chip packaging method of the embodiment of the disclosure, the 3D packaging challenge of the TSV without the silicon interposer can be completely overcome by utilizing the re-routing (ReDistribution Layer, RDL) technology. The rewiring layer and the conductive columns can improve stability and reliability of the 3D package, and electrical performance among chips is effectively improved. The method and the device do not need TSV silicon perforation technology, solve the cost problem in common 3D packaging, and meet the operation mode and operation capability of the existing machine. Therefore, the method can be widely applied to the design of 3D packaging products, and the quality and the production efficiency of the packaging products are greatly improved.

Another aspect of an embodiment of the present disclosure provides a chip package structure. As shown in fig. 14, the structure includes a plurality of plastic packaging units 800 stacked in sequence, and the plastic packaging units 800 include: a re-wiring layer 300, a chip 200, a molding layer 700, a conductive bump 400 located at a central region of the re-wiring layer 300, and a conductive post 500 located at an edge region of the re-wiring layer 300; the first surface of the chip 200 is provided with a conductive connection member 210, and the conductive connection member 210 is electrically connected with the conductive bump 400; the plastic layer 700 is disposed on the redistribution layer 300, the conductive pillars 500, and the chip 200; adjacent two plastic packaging units 800 are electrically connected through the corresponding conductive posts 500, and solder balls 810 are disposed on the rewiring layer 300 exposed by the plastic packaging units 800 at the bottom layer.

Specifically, the packaging structure obtained by the chip packaging method reduces packaging cost by interconnecting the chips through the rewiring layer and the conductive columns, does not need a silicon interposer and a TSV structure, solves the cost problem in common 3D packaging, can be widely applied to 3D packaging products, and greatly improves the quality and production efficiency of the packaging products.

In one embodiment, as shown in fig. 14, the conductive connection member 210 includes a conductive bump 211, a conductive bump 212, and a solder bump 213; the conductive bump 211 is disposed on the first surface of the chip 200, the conductive bump 212 and the solder bump 213 are sequentially disposed on the conductive bump 211, and the solder bump 213 is electrically connected to the conductive bump 400.

Specifically, the solder bump is placed on a conductive bump (UBM) and placed in a reflow oven, and the solder is melted by reflow to form good wetting combination with the UBM, so that a good welding effect is achieved.

In one embodiment, as shown in fig. 14, the plastic layer 700 further includes: underfill 600; the underfill 600 is between the redistribution layer 300 and the chip 200.

Specifically, under filling glue (render fill) is injected into the bottom of the chip, so that the problem that the chip and the carrier plate are not attached to each other due to different thermal expansion coefficients between the chip and the carrier plate is solved except for reinforcing connection, and poor contact caused by breakage of the conductive connecting piece in reflow soldering is avoided.

It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims

1. A method of packaging a chip, the method comprising:

2. The method of claim 1, wherein forming a redistribution layer on the first surface of the carrier, forming conductive bumps in a central region of the redistribution layer, and forming conductive pillars in an edge region of the redistribution layer comprises:

3. The method of claim 2, wherein the first openings in the central region are staggered from the second openings, and wherein the first openings in the edge region are positioned corresponding to the second openings.

4. A method according to any one of claims 1 to 3, wherein prior to plastic packaging the redistribution layer, the conductive pillars, and the chip, the method further comprises:

and forming underfill between the rewiring layer and the chip.

5. A method according to any one of claims 1 to 3, wherein said plastic packaging the redistribution layer, the conductive pillars and the chip to form a plastic packaging unit comprises:

and thinning the surface of the plastic sealing layer, which faces away from the carrier plate, until the conductive columns are exposed, so as to obtain the plastic sealing unit.

6. A method according to any one of claims 1 to 3, wherein an end of the conductive post facing away from the redistribution layer is higher than the second surface of the chip.

7. A method according to any one of claim 1 to 3, wherein,

before forming the redistribution layer on the first surface of the carrier plate, the method further comprises: forming a release layer on a first surface of the carrier plate, and forming the rewiring layer on the release layer;

8. The utility model provides a chip packaging structure, includes a plurality of plastic packaging units that pile up in proper order, its characterized in that, plastic packaging unit includes: the semiconductor package comprises a rewiring layer, a chip, a plastic sealing layer, a conductive bump positioned in the central area of the rewiring layer and a conductive column positioned in the edge area of the rewiring layer;

9. The package structure of claim 8, wherein the conductive connection comprises a conductive bump, and a solder bump; the conductive block is arranged on the first surface of the chip, the conductive convex points and the welding blocks are sequentially arranged on the conductive block, and the welding blocks are electrically connected with the conductive convex blocks.

10. The package structure of claim 8, wherein the plastic layer further comprises: filling glue; the underfill is between the redistribution layer and the chip.