CN116954950B - Inter-core communication method and electronic equipment - Google Patents
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Abstract
The application relates to an inter-core communication method, wherein a shared memory is arranged between at least two cores of a processor, the shared memory comprises a plurality of sections with equal size, the method comprises the steps of calculating the number k of the sections in the shared memory which are occupied by data to be transmitted, wherein k is an integer which is more than 1 and less than N, N is the total number of the sections of the shared memory, and N is an integer which is more than or equal to 2; determining whether the rest idle sections in the shared memory are enough to continuously store the data to be sent; when the rest idle sections in the shared memory are not enough to continuously store the data to be sent, marking the data length in all rest idle sections in the shared memory as 0, and sending soft interrupt; re-determining the sequence number of the first idle section in the shared memory, writing the data to be sent into the shared memory, and sending soft interrupt; the at least two cores are cores comprising a cache, and the cache is not effective to the shared memory.
Description
Technical Field
The present application relates to the field of data communications, and in particular, to an inter-core communication method and an electronic device.
Background
Inter-core communication techniques are techniques for data or signal interaction between different cores in a multi-core processor architecture. In an embedded scenario, memory resources are limited, and a lightweight and efficient inter-core communication method is required. One common method of inter-core communication is to use a shared memory to store data to be transmitted, and use inter-core soft interrupts to notify other cores to acquire the data. In an embedded scene, in order to improve the use efficiency of the memory, the shared memory can be divided into a plurality of sections according to the equal length, and data content with the length of not more than one section can be sent each time.
However, depending on the usage scenario, inter-core communications may encounter situations where the data to be transmitted is greater than one segment length. The existing solution is to split the data to be transmitted into a plurality of data packets, and directly process the plurality of split data packets or recombine the plurality of split data packets into complete data when receiving the data. The direct processing of multiple packets requires the receiver to have the ability to process segmented packets, e.g., multiple packets may involve multiple pointers. For the re-merging scheme, since each data packet includes a packet header and a check bit, the operation of merging into complete data requires additional memory space as a buffer for removing the packet headers and check bits and re-combining. In embedded development scenarios, these existing solutions are either too demanding for the recipient or require a lot of memory space.
Disclosure of Invention
Aiming at the technical problems in the prior art, the application provides an inter-core communication method, wherein a shared memory is arranged between at least two cores of a processor, the shared memory comprises a plurality of sections with equal size, the method comprises the steps of calculating the number k of sections in the shared memory which are occupied by data to be transmitted, wherein k is an integer which is more than 1 and less than N, N is the total number of the sections of the shared memory, and N is an integer which is more than or equal to 2; determining whether the rest idle sections in the shared memory are enough to continuously store the data to be sent; when the rest idle sections in the shared memory are not enough to continuously store the data to be sent, marking the data length in all rest idle sections in the shared memory as 0, and sending soft interrupt; re-determining the sequence number of the first idle section in the shared memory, writing the data to be sent into the shared memory, and sending soft interrupt; the at least two cores are cores comprising a cache, and the cache is not effective to the shared memory.
In particular, the method further includes when the remaining free segments in the shared memory are capable of continuously storing the data to be sent, writing the data to be sent into the shared memory, and marking the total length of the data; a soft interrupt is sent.
In particular, determining whether the remaining free segments in the shared memory are sufficient to continuously store the data to be transmitted includes determining a sequence number m of a first free segment in the shared memory, where m is an integer greater than 1 and less than or equal to N; judging whether N-m+1 is greater than or equal to k.
Particularly, when the remaining free sections in the shared memory are not enough to continuously store the data to be transmitted, marking the data length in all the remaining free sections of the shared memory as 0, including applying for the mth shared memory section, and marking the data length to be transmitted as 0 in the mth shared memory section; judging whether m is equal to N; when m is not equal to N, adding 1 to m, and sending soft interrupt; and when m is equal to N, sending soft interrupt and redefining the sequence number of the first section which is shared and is currently idle.
The application provides an inter-core communication method, wherein a shared memory is arranged between at least two cores of a processor, and the shared memory comprises a plurality of sections with equal size, including judging whether a soft interrupt is received or not; under the condition of receiving the soft interrupt, determining the first section of the data received from the sending core and stored in the shared memory so as to acquire the length of the data; judging whether the data length in the first section is 0; when the data length in the first section is 0, releasing the shared memory section; when the data length in the first section is not 0, judging the number of the sections of the shared memory occupied by the first section according to the data length, and processing the data; releasing the section of the shared memory occupied by the received data; the at least two cores are cores comprising a cache, and the cache is not effective to the shared memory.
The application provides electronic equipment, which comprises a processor of a first core and a second core, and a shared memory between the two cores, wherein the shared memory comprises a plurality of sections with equal sizes, the first core and the second core are cores comprising a cache, and the cache is not effective to the shared memory; the first core includes a request module configured to provide a data transmission request; a transceiver module coupled to the request module configured to receive the data transmission request; calculating the number of sections in the shared memory which are occupied by the data to be sent to the second core; determining whether the rest idle sections in the shared memory are enough to continuously store the data to be sent; when the rest idle sections in the shared memory are not enough to continuously store the data to be sent, marking the data length in all rest idle sections in the shared memory as 0, and sending soft interrupt; and re-determining the position of the first free section in the shared memory, writing the data to be sent into the shared memory, and sending a soft interrupt to the second core.
In particular, the transceiver module in the first core is configured to continuously store the data to be sent when the remaining free sections in the shared memory are enough, write the data to be sent into the shared memory, and mark the total length of the data; a soft interrupt is sent.
In particular, the transceiver module in the first core is configured to determine a sequence number m of a first idle section of the shared memory, where m is an integer greater than 1 and less than or equal to N; judging whether N-m+1 is greater than or equal to k.
In particular, the transceiver module in the first core is configured to apply for the mth shared memory section, and mark the length of the data to be sent as 0 in the mth shared memory section; judging whether m is equal to N; when m is not equal to N, adding 1 to m, and sending soft interrupt; and when m is equal to N, sending soft interrupt and redetermining the sequence number of the first section of the shared memory which is currently idle.
In particular, the second core includes a processing module configured to process data sent by the first core stored in a shared memory; the receiving and transmitting module is configured to judge whether soft interruption is received or not; under the condition of receiving the soft interrupt, determining the first section of the data received from the sending core and stored in the shared memory so as to acquire the length of the data; judging whether the data length in the first section is 0; when the data length in the first section is 0, releasing the shared memory section; when the data length in the first section is not 0, judging the number of the sections of the shared memory occupied by the first section according to the data length, and processing the data; and releasing the section of the shared memory occupied by the received data.
The present application also provides a computer storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in any of the preceding.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a schematic block diagram of an electronic device including multiple cores and shared memory between the multiple cores;
FIG. 2 is a flow chart illustrating a method of inter-core communication according to one embodiment of the present application; and
fig. 3 is a flow chart illustrating a method of inter-core communication according to one embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.
FIG. 1 is a schematic block diagram illustrating a portion of a structure of an electronic device including multiple cores and shared memory between the multiple cores. The device includes at least two cores, core a 102 and core B103, and shared memory 101 therebetween. According to actual needs, the core A can write the data to be transmitted to the core B into the shared memory, and send the soft interrupt to the core B to inform that the data is to be sent, and the core B reads the data written by the core A from the shared memory after receiving the soft interrupt. The shared memory may include a plurality of equally sized sections.
According to other embodiments, core B may also write its data to be transferred to core a into shared memory and send a soft interrupt to core a informing that there is data to be sent, and core a may read the data to which core B is to send into shared memory. Of course, in general, different shared memories are set up during the two transmission processes to avoid unnecessary confusion.
Fig. 2 is a flow chart illustrating a method of inter-core communication according to one embodiment of the present application. The method may be performed by a core in a processor. In this method, when the size of data to be transmitted is larger than one section in the shared memory, the data to be transmitted is not divided into a plurality of packets to be stored, but is stored in a complete and continuous manner. In order to avoid the situation that the data storage is discontinuous, so that the receiving core needs to perform additional operations or needs additional storage space to be combined, the following operations are adopted in the embodiment of the present application.
Cores that include caches and cores that do not include caches currently exist in processors. For cores that do not include caches, the operations in inter-core communication are simpler and less restrictive.
First, it should be noted that, in this application, the cores include a cache, and in the process of inter-core communication, the cache needs to be disabled for the shared memory, so as to avoid writing or reading erroneous data due to the fact that the data in the cache is not synchronized with the memory.
According to one embodiment, the processor may include at least two cores, one core may be a transmitting core and one core may be a receiving core in one data transmission. The following method may be performed by the sending core.
At 201, a determination is made as to whether there is data to send to the receiving core. If so, the following operation is continued, and if not, the present operation is repeated.
At 202, the number k of shared memory segments to be occupied by data to be transmitted is calculated, where k is an integer greater than 1 and less than or equal to N, N is the total number of all segments of the shared memory, and N is an integer greater than or equal to 2.
At 203, it is determined that the sequence number m of the first segment of the shared memory that is currently free is an integer greater than or equal to 1 and less than or equal to N.
At 204, it is determined whether the remaining free segments of the shared memory can continuously store data to be transmitted, e.g., whether N-m+1 is greater than or equal to k. The reason for this determination is to avoid a situation where data is stored discontinuously in the shared memory, resulting in an additional operation being required. If yes, continuing the following operation; if not, jump to 208.
By continuous storage is meant that the data to be transmitted is not cut into k packets, but rather the entire data to be transmitted is one packet, comprising only one header and the end check bits. Therefore, the space of the shared memory is saved, the processing is convenient when the check data is received and processed, the header check bits of a plurality of packets do not need to be stripped one by one, a plurality of pointers are not needed, and the operation of combining the data packets does not need to be carried out in an extra storage space.
At 205, when N-m+1 is greater than or equal to k, meaning that the data to be sent can be continuously stored in the shared memory, the positions of the m-th to m+k-1-th sections in the shared memory are applied.
At 206, the data to be transmitted is filled or written into the m-th to m+k-1-th sections in the shared memory, and the total length of the data to be transmitted is marked, i.e. the total length of the data to be transmitted is written into the header of the entire data packet.
At 207, a soft interrupt is sent to the receiving core to the other core and 201 is returned.
At 208, when N-m+1 is less than k, it means that the data to be sent cannot be stored in the shared memory continuously, and the mth sector shared memory is applied.
At 209, the length of the data to be transmitted is marked as 0 in the mth sector shared memory.
At 210, determining whether m is equal to N, if not, continuing the following operations; if so, a soft interrupt is sent to the receiving core and operation 203 is entered where the sequence number of the first free segment is redetermined.
At 211, m is incremented by 1, a soft interrupt is sent to the receiving core, and jumps back to 208, continuing to mark the data length in the remaining free section as 0.
According to other embodiments, when N-m+1 is less than k, N-m+1 remaining free sections may be marked as data length to be transmitted 0 at a time, and a soft interrupt may be transmitted.
In the above embodiment, when the remaining segments in the shared memory are insufficient to accommodate the data to be transmitted, the data length of the remaining free segments in the shared memory is marked as 0, and a soft interrupt is sent to the receiving core. The receiving core releases the segments, and the sending core can redetermine the sequence number of the first free segment in the current shared memory and evaluate whether the number of segments of the remaining shared memory is enough to continuously store the data to be sent. According to one embodiment, the first free segment after reevaluation may be the first segment in shared memory.
It is noted that first, the free shared memory segments are contiguous rather than being spaced apart from each other. Second, the size of the data to be transmitted is greater than one sector but less than or equal to the total number of sectors of the shared memory. Third, the speed of the reception checkup data processing is fast, and when the sequence number of the first free section is newly determined after the section that is not enough to continuously store the data to be transmitted is marked as 0 and released, the data to be transmitted can be continuously stored in the shared memory basically.
Fig. 3 is a flow chart illustrating a method of inter-core communication according to one embodiment of the present application. The method may be performed by a receiving core.
At 301, a determination is made as to whether a soft interrupt has been received, or whether there is data to be received. If not, repeating the operation; if so, the following operations are performed.
At 302, the sequence number of the first section of the shared memory occupied by the received data is checked to obtain the total length of the data.
At 303, determining whether the total length of data is 0; if so, operation 304 is performed; if not, operation 305 is performed.
At 304, a shared memory segment is released.
At 305, the number of the sections of the shared memory that need to be occupied is determined to be k according to the data length. The data length is recorded as part of the header of the data. The receiving core reads the header to obtain the length of each packet.
At 306, data in the shared memory is processed.
According to one embodiment, when processing data in the shared memory, the data is not required to be copied, extra memory is not required to be occupied, and the data is directly acquired from an address corresponding to the shared memory. I.e. for a data processing module section, its input is a pointer to the data to be processed. In contrast, in the prior art, if the data segments are stored in a shared memory, such as the nth segment and the 1 st segment, then multiple pointers need to be provided to the receiving core.
At 307, after processing is complete, k shared memory segments are released and operation 301 is returned.
The present application also provides an electronic device including a plurality of cores and a shared memory between the plurality of cores, the system being configured to perform the above method.
The core sending data according to one embodiment may include a transceiver module and a request module, wherein the data transceiver module may be configured to perform operations such as operations 202-211 and the data processing module may be configured to perform operations such as operation 201.
The core receiving the data may include a transceiver module and a processing module, where the data transceiver module may be configured to perform operations such as operations 301-305 and 307, and the data processing module may be configured to perform operations such as operation 306.
According to various embodiments, the identities of the core receiving the data and the core sending the data may be adjusted or tuned as needed, so that the operations performed may be correspondingly adjusted or tuned.
The present application also provides a computer storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in any of the preceding.
By adopting the scheme, the data transmission which is maximally close to the total size of the shared memory can be supported, the data can be continuously stored in the shared memory, extra memory copy operation is avoided, extra shared memory is not needed, and the use efficiency of the shared memory is higher.
The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (9)
1. An inter-core communication method in which a shared memory is provided between at least two cores of a processor, the shared memory including a plurality of equal-sized sections, the method comprising
The sending core calculates the number k of the sections in the shared memory which are occupied by the data to be sent, wherein k is an integer which is more than 1 and less than N, N is the total number of the sections of the shared memory, and N is an integer which is more than or equal to 2;
the sending core determines whether the rest idle sections in the shared memory are enough to continuously store the data to be sent;
when the rest idle sections in the shared memory are not enough to continuously store the data to be sent, the sending core marks that the data length in all the rest idle sections in the shared memory is 0, and sends soft interrupt;
the sending core re-determines the sequence number of the first free section in the shared memory, writes the data to be sent into the shared memory, and sends a soft interrupt, wherein the first free section in the re-determined shared memory comprises the first section in the shared memory;
the receiving core judges whether a soft interrupt is received or not;
under the condition of receiving the soft interrupt, the receiving core determines the first section of the data received from the sending core and stored in the shared memory so as to acquire the length of the data;
the receiving core judges whether the data length in the first section is 0;
when the data length in the first section is 0, the receiving core releases the shared memory section;
when the data length in the first section is not 0, the receiving core judges the number of the sections of the shared memory occupied by the receiving core according to the data length and processes the data; and
the receiving core releases the section of the shared memory occupied by the received data;
the at least two cores are cores comprising a cache, and the cache is not effective to the shared memory.
2. The method of claim 1, further comprising
When the rest idle sections in the shared memory can continuously store the data to be sent, writing the data to be sent into the shared memory, and marking the total length of the data; and sending a soft interrupt.
3. The method of claim 1, wherein determining whether remaining free segments in the shared memory are sufficient to continuously store the data to be transmitted comprises
Determining a sequence number m of a first idle section in the shared memory, wherein m is an integer which is more than 1 and less than or equal to N; and
judging whether N-m+1 is greater than or equal to k.
4. The method of claim 3, wherein marking the data length of all remaining free segments of the shared memory as 0 when the remaining free segments of the shared memory are insufficient to continuously store the data to be transmitted comprises
Applying for the mth shared memory section, and marking the length of the data to be sent as 0 in the mth shared memory section;
judging whether m is equal to N;
when m is not equal to N, adding 1 to m, and sending soft interrupt; and
and when m is equal to N, sending soft interrupt and redefining the sequence number of the first section which is shared and is currently idle.
5. An electronic device comprising a processor of a first core and a second core, and a shared memory between the two cores, the shared memory comprising a plurality of equal-sized segments, wherein the first core and the second core are both cores comprising a cache, and the cache is not effective to the shared memory;
the first core includes
A request module configured to provide a data transmission request;
a transceiver module coupled to the request module configured to
Receiving the data transmission request;
calculating the number of sections in the shared memory which are occupied by the data to be sent to the second core;
determining whether the rest idle sections in the shared memory are enough to continuously store the data to be sent;
when the rest idle sections in the shared memory are not enough to continuously store the data to be sent, marking the data length in all rest idle sections in the shared memory as 0, and sending soft interrupt; and
the position of a first free section in the shared memory is redetermined, the data to be sent is written into the shared memory, and soft interrupt is sent to a second core, wherein the first free section in the redetermined shared memory comprises a first section in the shared memory;
wherein the second core comprises
The processing module is configured to process the data sent by the first core stored in the shared memory;
a transceiver module coupled to the processing module configured to
Judging whether soft interruption is received or not;
under the condition of receiving the soft interrupt, determining the first section of the data received from the sending core and stored in the shared memory so as to acquire the length of the data;
judging whether the data length in the first section is 0;
when the data length in the first section is 0, releasing the shared memory section;
when the data length in the first section is not 0, judging the number of the sections of the shared memory occupied by the first section according to the data length, and processing the data; and
and releasing the section of the shared memory occupied by the received data.
6. The electronic device of claim 5, wherein the transceiver module in the first core is configured to
When the rest idle sections in the shared memory can continuously store the data to be sent, writing the data to be sent into the shared memory, and marking the total length of the data; and sending a soft interrupt.
7. The electronic device of claim 5, wherein the transceiver module in the first core is configured to
Determining a sequence number m of a first idle section of the shared memory, wherein m is an integer which is more than 1 and less than or equal to N;
judging whether N-m+1 is greater than or equal to k.
8. The electronic device of claim 7, wherein the transceiver module in the first core is configured to
Applying for the mth shared memory section, and marking the length of the data to be sent as 0 in the mth shared memory section;
judging whether m is equal to N;
when m is not equal to N, adding 1 to m, and sending soft interrupt; and
and when m is equal to N, sending soft interrupt and redetermining the sequence number of the first section of the shared memory which is currently idle.
9. A computer storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-4.
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