CN116931812A - Data access method and storage medium and apparatus for responding to host discard command - Google Patents

Abstract

A data access method, computer readable storage medium and apparatus for responding to a host discard command. The method comprises the following steps: configuring a space in the random access memory to an extended discard table comprising a plurality of entries, each entry describing a logical address of the discarded user data; receiving a host discard command from the host indicating a first logical address of user data that is no longer in use; newly adding a new item containing the first logical address to the extended discard table; and setting a start address register and an end address register in the performance engine for redefining an address range of the extended discard table stored in the random access memory. By setting the performance engine and using the extended discard table, the processing unit is prevented from consuming excessive operation resources to judge whether the logic address of the user data to be written by the host write command or the logic address of the user data to be read by the host read command falls into the logic address section which has been discarded before.

Description

Data access methods and storage media and devices in response to host discard command

Technical field

The present invention relates to storage devices. In particular, the present invention relates to a data access method, computer-readable storage medium and device in response to a host discard command.

Background technique

Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. On the contrary, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write serial byte (Bytes) values to NAND flash memory to define the type of request command (Command) (such as, read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest block of data for a write operation in flash memory) or a block (the smallest block of data for an erase operation in flash memory). In order to improve the execution performance of the flash memory controller, the present invention proposes a data access method, a computer-readable storage medium and a device in response to a host discard command.

Contents of the invention

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

The invention relates to a data access method in response to a host discard command, which is executed by a processing unit and includes: configuring space in a random access memory for an extended discard table, including a plurality of items, and each item records that it has been discarded the logical address of the user data; receiving a host discard command from the host end, indicating the first logical address of the user data that is no longer used; adding a new item containing the first logical address to the extended discard table; and setting the start address register and the end address register in the performance engine to redefine the address range of the extended discard table stored in the random access memory, so that the performance engine passes the The address range in memory searches the extended discard table to determine whether user data for a particular logical address is no longer in use.

The invention also relates to a computer-readable storage medium containing a computer program. When the processing unit loads and executes the computer program, the data access method in response to the host discard command as shown above is implemented.

The invention also relates to a data access device responding to a host discard command, including: a random access memory; a performance engine; and a processing unit. The random access memory is used to allocate space for the extended discard table, which contains multiple entries, and each entry records the logical address of discarded user data. The performance engine includes a start address register and an end address register, which are used to define an address range in the random access memory where the extended discard table is stored. The processing unit is configured to receive a host discard command from the host, which indicates a first logical address of user data that is no longer used; add a new entry including the first logical address to the extended discard table; and set The start address register and the end address register in the performance engine are used to redefine the address range of the extended discard table stored in the random access memory, so that the performance engine passes the The address range in the random access memory searches the extended discard table to determine whether user data at a specific logical address is no longer in use.

One of the advantages of the above embodiment is that through the setting of the performance engine and the use of the extended discard table, the processing unit is prevented from consuming too much computing resources to determine the logical address of the user data to be written by the host write command or the host read. Whether the logical address of the user data to be read by the command falls into the previously discarded logical address range.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and the accompanying drawings.

Description of the drawings

The description and drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

FIG. 1 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

Figure 3 is a block diagram of a performance engine and a random access memory according to an embodiment of the present invention.

Figure 4 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 5 is a flow chart of a method for updating the extended discard table after the host write command is executed according to an embodiment of the present invention.

FIG. 6 is a flow chart of a method for executing a host read command according to an embodiment of the present invention.

Figure 7 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

FIG. 8 is a flow chart of a discard command and an update method of an extended discard table after the host write command is executed according to an embodiment of the present invention.

FIG. 9 is a flow chart of a method for executing a host read command according to an embodiment of the present invention.

Among them, the reference signs are:

10 electronic devices

110 Host side

130 Flash Controller

131 host interface

132 bus architecture

134 processing units

136 random access memory

137 Performance Engine

138 Direct Memory Access Controller

139 Flash memory interface

150 flash memory module

151 interface

153#0～153#15 NAND flash memory unit

CH#0~CH#3 channels

CE#0～CE#3 start signal

310 Search circuit

322 Start address register

324 end address register

330#0～330#7 target register

350#0～350#7 result register

S410～S430 method steps

S510～S540 method steps

S610～S640 method steps

S710～S720 method steps

S810～S820 method steps

S910～S924 method steps

Detailed ways

The embodiments of the present invention will be described below with reference to relevant drawings. In the drawings, the same reference numerals represent the same or similar components or method flows.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, elements and/or components, but do not exclude the possibility of Plus further technical features, values, method steps, processes, components, assemblies, or any combination of the above.

The use of words such as "first", "second" and "third" in the present invention are used to modify the components in the claims, and are not used to indicate a priority order or precedence relationship between them, or that one component comes first. to another component, or the time sequence when executing method steps, only used to distinguish components with the same name.

It must be understood that when a component is described as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component or intervening components may be present. In contrast, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components present. Other words used to describe the relationship between components could be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device 10 includes: a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as a device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, and digital video cameras. The host interface (Host Interface) 131 between the host side 110 and the flash memory controller 130 can be a universal serial bus (Universal Serial Bus, USB), advanced technology attachment (Advanced Technology Attachment, ATA), serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), Embedded Multi-Media Card (eMMC) and other communication protocols communicate with each other. The flash memory interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (Double Data Rate, DDR) communication protocol, for example, Open NAND Flash Memory Interface (Open NAND Flash Interface, ONFI), Double Data rate switch (DDR Toggle) or other communication protocols. The flash memory controller 130 includes a processing unit 134, which may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and When executing software and/or firmware instructions, the functions described later are provided. The processing unit 134 receives host commands through the host interface 131, such as read commands (Read Command), write commands (Write Command), erase commands (Erase Command), etc., and schedules and executes these commands. The flash memory controller 130 also includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM) or The combination of the above two is used to configure the space as a data buffer to store user data (also called host data) read from the host 110 and about to be written to the flash memory module 150, and read from the flash memory module 150 and about to be written. User data output to the host 110. The random access memory 136 can also store data needed during execution, such as variables, data tables, host-to-Flash (H2F Table), and flash-to-host comparison table (Flash-to-Host, H2F Table). F2H Table) etc. The flash memory interface 139 includes a NAND Flash Controller (NFC), which provides functions required to access the flash memory module 150, such as a command serializer (Command Sequencer) and a low density parity check (LDPC). wait.

In some embodiments, the processing unit 134 may comply with the specifications of eMMC, such as Section 6.6.12 of "EMBEDDED MULTI-MEDIA CARD (e·MMC), ELECTRICAL STANDARD (5.1)" published in January 2019, through the host The interface 131 receives a discard command (Discard Command) from the host 110 . In other embodiments, the processing unit 134 may comply with UFS specifications, such as Section 11.3.26 of Version 3.1 of UNIVERSAL FLASH STORAGE (UFS) published in January 2020, and receive data from the host 110 through the host interface 131 Unmap command (UNMAP Command). If the parameter "bProvisioningType" of the unit descriptor (Unit Descriptor) in the unmapping command is set to "02h", it means that this is a discard command. The host 110 can send the host discard command as described above to the flash memory controller 130 to indicate the logical address of the user data that is no longer used, such as the host page number (Host PageNumber), logical block address (Logical Block Address). , LBA) and other methods. Different from the host erase command, when executing the host discard command, the flash memory controller 130 does not need to physically erase the memory unit used to store the data at the specified logical address, but only needs to mark that the data at the logical address no longer exists. When appropriate, the flash memory controller 130 executes a garbage collection program to collect physical memory cells corresponding to the marked logical addresses and erase them.

The configurable bus architecture (Bus Architecture) 132 in the flash memory controller 130 is used to couple components to each other to transmit data, addresses, control signals, etc. These components include: host interface 131, processing unit 134, RAM 136, direct Memory access (Direct Memory Access, DMA) controller 138, flash memory interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the RAM 136, the DMA controller 138, and the flash memory interface 139 may be coupled to each other through a single bus. In other embodiments, the flash memory controller 130 may be configured with a high-speed bus for coupling the processing unit 134, the DMA controller 138 and the RAM 136 to each other, and a low-speed bus may be configured for the processing unit 134, the DMA controller 138. The host interface 131 and the flash memory interface 139 are coupled to each other. The DMA controller 138 can migrate data between components through the bus architecture 132 according to the instructions of the processing unit 134, for example, move the data of a specific data buffer (DataBuffer) in the host interface 131 or the flash memory interface 139 to a specific address in the RAM 136, The data at a specific address in the RAM 136 is moved to a specific data buffer in the host interface 131 or the flash memory interface 139, etc.

The bus includes parallel physical lines that connect two or more components in the flash memory controller 130 . The bus is a shared transmission medium. At any time, only two devices can use these lines to communicate with each other and transfer data. Data and control signals can propagate in both directions between components along the data and control lines respectively, but on the other hand, address signals can only propagate in one direction along the address lines. For example, when processing unit 134 wants to read data at a specific address of RAM 136, processing unit 134 transmits this address to RAM 136 on the address line. Then, the data at this address will be returned to the processing unit 134 on the data line. In order to complete the data read operation, control signals are transmitted using control lines.

The flash memory module 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high resolution Pictures, videos, etc. The flash memory module 150 includes a control circuit and a memory array. The memory cells in the memory array can be configured into single-level cells (Single Level Cells, SLCs), multi-level cells (Multiple Level Cells, MLCs), or three-level cells after erasure. Triple Level Cells (TLCs), Quad-Level Cells (QLCs) or any combination of the above. The processing unit 134 writes user data to a specified address (destination address) in the flash memory module 150 through the flash memory interface 139, and reads user data from the specified address (source address) in the flash memory module 150. The flash memory interface 139 uses multiple electronic signals to coordinate data and command transmission between the flash memory controller 130 and the flash memory module 150, including data lines (DataLine), clock signals (Clock Signal) and control signals (Control Signal). The data line can be used to transmit commands, addresses, read and write data; the control signal line can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable (Command Latch Enable) , CLE), write enable (Write Enable, WE) and other control signals.

Referring to Figure 2, the interface 151 in the flash memory module 150 may include four input and output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel is connected to four NAND flash memory cells, for example, channel CH# 0 connects NAND flash memory cells 153#0, 153#4, 153#8, and 153#12, and so on. Each NAND flash memory cell can be packaged as an independent chip (die). The flash memory interface 139 may send one of the activation signals CE#0 to CE#3 through the interface 151 to activate the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the activated NAND flash memory unit in a parallel manner, or write user data to the activated NAND flash memory unit.

In some previous implementations, the flash memory controller 130 may configure space in the RAM 136 for a discard queue (Discard Queue). The discard queue contains multiple nodes, and each node is used to store information about the logical address range of the discarded user data indicated by the host discard command. Table 1 shows the discard queue for the example:

Table 1

Node number start address length 0 P#100 32 1 P#200 4 2 P#300 64 3 P#500 8

For example, each node stores the starting master page number and length indicated by a discard command. As mentioned above, the 0th to 3rd example nodes contain the following information. The four previously received discard commands respectively indicate that the main pages P#100~P#131, P#200~P#203, and P#300~ The user data of P#363 and P#500~P#507 are discarded. However, each time the processing unit 134 receives a host read command from the host terminal 110 through the host interface 131, it needs to spend computing resources searching the discard queue to determine whether the user data to be read by the host read command has been discarded. If the read user data has been discarded, the processing unit 134 replies to the host 110 with an error message or a dummy value through the host interface 131 . When the processing unit 134 receives a host write command from the host 110 through the host interface 131 each time, it also needs to expend computing resources to search the discard queue to determine whether the logical address of the user data to be written by the host write command falls within the previous The logical address range that has been discarded.

In order to reduce the load on the processing unit 134 and improve the overall performance of the flash memory controller 130, the flash memory controller 130 can allocate space in the RAM 136 for the expanded discard table (Expanded Discard Table), and use a dedicated performance engine 137 to search for the expanded discard table. Discard table. The extended discard table can contain 1024 entries, each entry recording the logical address of discarded user data, or a NULL value. It should be noted that those skilled in the art can configure more or less space in the RAM 136 to store the extended discard table according to system requirements. The present invention is not limited to the extended discard table containing only 1024 items. Table 2 shows an example extended drop table:

Table 2

Compared with Table 1, conceptually, the information of the 0th item in Table 1 can be expanded to the 0th to 31st items in Table 2, recording the main page numbers P#100 to P#131 respectively; Table 1 The information of the first item in Table 2 can be expanded to the 32nd to 35th items in Table 2, and the main page numbers P#200 to P#203 are recorded respectively, and so on. The processing unit 134 can perform sorting when adding items to the extended discard table based on the information carried in the host discard command, so that the logical addresses can be arranged in ascending or descending order to facilitate search by the dedicated performance engine 137 .

Refer to Figure 3. The performance engine 137 may include a start address register 322 and an end address register 324 for allowing the processing unit 134 to define the address range of the extended discard table in the RAM 136 . Since the number of items stored in the extended discard table is variable, whenever the contents of the extended discard table are updated, the processing unit 134 will reset the start address register 322 and the end address register 324 to allow the search circuit to 310 can search within the address range of RAM 136 specified by the start address register 322 and the end address register 324 . For example, corresponding to the contents of Table 2, the start address register 322 stores the memory address "ExpDiscardTable_start", and the end address register 324 stores ExpDiscardTable_star+107. The performance engine 137 may include eight target registers 330#0˜330#7 for allowing the processing unit 134 to instruct the search circuit 310 to search up to eight primary page numbers in the extended discard table. The performance engine 137 may include eight result registers 350#0˜350#7, allowing the search circuit 310 to store search results corresponding to the target registers 330#0˜330#7 respectively. For example, result register 350#0 stores search results for the main page number indicated by target register 330#0, result register 350#1 stores search results for the main page number indicated by target register 330#1, and so on. For example, the result register may be a 16-bit register, in which the 15th bit stores the information of whether there is a hit. If there is a hit, the 14th to 0th bits store the hit item number in the extended discard table. The processing unit 134 can read the value of any one of the result registers 350#0˜350#7 to obtain the information whether the main page number in the corresponding target register appears in the extended discard table, and, if hit, the main page The item in the extended discard table where the number exists. It should be noted that those skilled in the art can configure more or fewer pairs of target registers and result registers in the performance engine 137 according to the needs of the system. The present invention is not limited to only eight pairs of target registers in the performance engine 137. registers and result registers. Those skilled in the art can use known circuits to implement the search circuit 310, so that the search circuit 310 can complete linear search (Linear Search), binary search (Binary Search), and exponential search (Exponential Search) in the extended discard table. , Fibonacci Search, etc.

In some embodiments, dedicated wires may be used to connect the processing unit 134 and the performance engine 137 to allow the processing unit 134 to set the start address register 322, the end address register 324, and the target registers 330#0˜330# through the dedicated wires. 7, and read the search results from the result registers 350#0~350#7.

In other embodiments, the processing unit 134 can set the start address register 322, the end address register 324, and the target registers 330#0˜330#7 in the performance engine 137 through the shared bus architecture 132, and obtain the data from the performance engine 137. The result registers 350#0~350#7 read the search results.

In some embodiments, a dedicated wire may be used to connect the performance engine 137 and the RAM 136 to allow the performance engine 137 to read the value of a specific address in the RAM 136 through the dedicated wire.

In other embodiments, performance engine 137 may read the value of a specific address in RAM 136 through shared bus architecture 132 and DAM controller 138 .

In response to the technical solution of the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly to process the host discard command received from the host end 110 . Referring to Figure 4, the detailed steps are as follows:

Step S410: Receive the first (next) host discard command from the host terminal 110 through the host interface 131. The host discard command is used to indicate the logical address of the user data that is no longer used.

Step S420: Update the contents of the extended discard table stored in the RAM 136 according to the logical address of discarded user data indicated by the host discard command. The items in the updated extended discard table will be sorted in ascending or descending order according to the logical address.

Step S430: Set the start address register 322 and the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before step S420 in a loop is executed, the extended discard table is as shown in Table 2: When the processing unit 134 receives user data instructing to discard the main pages P#400~P#403 (step S410), Table 2 The extended discard table can be updated as shown in Table 3 below (step S420):

table 3

Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+111 (step S430).

In response to the technical solutions of the extended discard table and the performance engine 137, embodiments of the present invention propose a method for updating the extended discard table after the host write command is executed, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. . This method is executed iteratively to adaptively update the extended discard table after each host write command. Referring to Figure 5, the detailed steps are as follows:

Step S510: Execute the first (next) host write command, which is used to write the user data at the specified logical address into the flash memory module 150 through the flash memory interface 139.

Step S520: Determine whether the logical address where the user data is written appears in the extended discard table. If yes, the process continues to the process of step S530; otherwise, the process continues to the process of step S510. The processing unit 134 may set the logical addresses to the target registers 330#0˜330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0˜330#7 and the driver performance engine 137, it can continue to process other tasks. After a default period of time, the processing unit 134 checks the result registers 350#0˜350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S530: Delete the corresponding entry of the logical address appearing in the extended discard table.

Step S540: Set the end address register 324 in the performance engine 137 according to the updated extended discard table.

Assume that before step S510 in a loop is executed, the extended discard table is as shown in Table 2: when the processing unit 134 completes executing the host write command of the user data of the main pages P#200 to P#203 (step S510) , the processing unit 134 sets the logical addresses P#200~P#203 to the target registers 330#0~330#3 in the performance engine 137, and drives the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in in the extended discard table (step S520). When it is found that the logical addresses P#200˜P#203 all appear in the extended discard table (“Yes” path in step S520), the processing unit 134 may update the extended discard table to be as shown in Table 4 below (step S530):

Table 4

Next, the processing unit 134 sets the end address register 324 to ExpDiscardTable_star+103 (step S540).

In response to the technical solution of the extended discard table and the performance engine 137, an embodiment of the present invention proposes a host read command execution method, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly, and is used to selectively reply false data or real user data to the host 110 according to the contents of the extended discard table when each host read command is executed. Referring to Figure 6, the detailed steps are as follows:

Step S610: Extract the first (next) host write command to instruct the flash memory controller 130 to read the user data at the specified logical address.

Step S620: Determine whether any logical address of the user data to be read appears in the extended discard table. If yes, the process continues to the process of step S630; otherwise, the process continues to the process of step S640. The processing unit 134 may set the logical addresses to the target registers 330#0˜330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0˜330#7 and the driver performance engine 137, it can continue to process other tasks. After a default period of time, the processing unit 134 checks the result registers 350#0˜350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S632: For the logical address appearing in the extended discard table, drive the host interface 131 to reply a false value to the host 110.

Step S634: Drive the flash memory interface 139 to read user data of other logical addresses that do not appear in the extended discard table from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host end 110.

Step S640: drive the flash memory interface 139 to read the user data at the specified logical address from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host end 110.

In some embodiments, flash controller 130 may configure space in RAM 136 for the extended discard table and discard queue. If the logical address length of discarded user data indicated by a host discard command exceeds or is equal to a specified number (for example, exceeds or is equal to 32), the information carried in the host discard command is stored in a node in the discard queue. If the logical address length of discarded user data indicated by a host discard command is less than the specified number, the information carried in the host discard command is stored in one or more consecutive entries in the extended discard table. For example, when the four previously received discard commands respectively indicate that the users of the main pages P#100~P#131, P#200~P#203, P#300~P#363 and P#500~P#507 When data is discarded, the information indicated by these four discard commands will be recorded in the discard queue shown in Table 5 below and the extended discard table shown in Table 6 below:

table 5

Node number start address length 0 P#100 32 1 P#300 64

Table 6

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, an embodiment of the present invention proposes a method for executing a host discard command, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly to process the host discard command received from the host end 110 . Referring to Figure 7, the difference from Figure 4 is that Figure 7 inserts the judgment of step S710 after step S410, and adds the processing of step S720 after the judgment is established. The detailed description is as follows:

Step S710: Determine whether the logical address length of the user data discarded as instructed by the host discard command exceeds or is equal to a specified number (for example, 32). If yes, the process continues to the process of step S720; otherwise, the process continues to the process of step S420.

Step S720: Update the contents of the discard queue stored in the RAM 136 according to the logical address of the discarded user data indicated by the host discard command.

For technical details of steps S410 to S430 in Figure 7 , reference can be made to the corresponding description in Figure 4 , and will not be described again for the sake of simplicity.

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, the embodiment of the present invention proposes a method for updating the discard queue and the extended discard table after the host write command is executed, and the processing unit 134 loads and executes the relevant Firmware or software instructions are implemented. This method is executed iteratively to adaptively update the drop queue and extended drop table after each host write command is executed. Referring to Figure 8, the difference from Figure 5 is that Figure 8 adds a new judgment of step S810 after step S510, and adds the processing of step S820 after the judgment is established. The details are as follows:

Step S810: Determine whether the logical address to which user data is written appears in the discard queue. If yes, the process continues to the process of step S820; otherwise, the process continues to the process of step S510.

Step S820: Update the content in the discard queue to reflect the execution result of the host write command. Assume that before step S510 in a loop is executed, the discard queue is as shown in Table 5: When the processing unit 134 completes executing the host write command of the user data of the main pages P#100 to P#131 (step S510), the processing Unit 134 may delete the 0th node in the discard queue to become as shown in Table 7 below (step S820):

Table 7

Node number start address length 0 P#300 64

For the technical details of steps S510, S530 to S430 in Figure 8, please refer to the corresponding description in Figure 5, and will not be described again for the sake of simplicity. It should be noted here that, with the assistance of the performance engine 137, the operations of steps S520 to S540 may be performed in parallel with the operations of steps S810 to S820.

In response to the technical solutions of the discard queue, the extended discard table and the performance engine 137, an embodiment of the present invention proposes a host read command execution method, which is implemented when the processing unit 134 loads and executes relevant firmware or software instructions. This method is executed repeatedly and is used to selectively reply false data or real user data to the host 110 according to the contents of the discard queue and the extended discard table when each host read command is executed. Referring to Figure 9, the difference between it and Figure 6 is that steps S620, S632, and S634 of Figure 6 are replaced by steps S910, S922, and S924 respectively. The detailed description is as follows:

Step S910: Determine whether the logical address of the user data to be read appears in at least one of the extended discard table and the discard queue. If yes, the flow continues to the processing of step S922; otherwise, the flow continues to the processing of step S640. The processing unit 134 may set the logical addresses to the target registers 330#0˜330#7 in the performance engine 137, and drive the performance engine 137 to search the extended discard table to determine whether these logical addresses appear in the extended discard table. It should be noted that after the processing unit 134 sets the target registers 330#0˜330#7 and the driver performance engine 137, it can then search the discard queue to determine whether these logical addresses appear in the discard queue. After a default period of time, the processing unit 134 checks the result registers 350#0˜350#7 in the performance engine 137 to determine whether these logical addresses appear in the extended discard table. After all logical addresses have been judged, the processing unit 134 continues the processing of the next step.

Step S922: For each logical address appearing in the extended discard table or discard queue, drive the host interface 131 to reply a false value to the host end 110.

Step S924: Drive the flash memory interface 139 to read user data of other logical addresses that do not appear in the extended discard table and discard queue from the flash memory module 150, and drive the host interface 131 to reply the read user data to the host end 110.

All or part of the steps in the method of the present invention can be implemented by a computer program, such as a firmware translation layer (FTL) in a storage device, a driver for specific hardware, etc. In addition, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the methods of the embodiments of the present invention into program codes, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, such as DVD, CD-ROM, U disk, hard disk, or can be placed through a network (for example, the Internet, or other appropriate media ) to access the network server.

Although the above-described components are included in FIGS. 1 to 3 , it does not rule out the use of more other additional components to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts of Figures 4 to 9 are executed in a specified order, those skilled in the art can modify the order of these steps without violating the spirit of the invention and achieving the same effect, so , the present invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention should not be limited thereby.

The above are only preferred embodiments of the present invention, but they are not intended to limit the scope of the present invention. Any person skilled in the art can make further improvements and modifications on this basis without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims of this application.

Claims (15)

1. A data access method according to a host discard command, executed by a processing unit, the data access method according to a host discard command comprising:

configuring a space in a random access memory to an extended discard table, wherein the extended discard table comprises a plurality of items, and each item records a logic address of user data which is discarded;

receiving a host discard command from a host, wherein the host discard command indicates a first logical address of user data that is no longer used;

newly adding a new item containing the first logical address to the extended discard table; and

setting a start address register and an end address register in a performance engine for redefining an address range of the extended discard table stored in the random access memory such that the performance engine searches the extended discard table through the address range in the random access memory to determine whether user data of a specific logical address has been no longer used.

2. The method of claim 1, wherein a plurality of the entries of the extended discard table are arranged in an ascending or descending manner according to the logical address.

3. The data access method in response to a host discard command as recited in claim 1, comprising:

executing a host write command to write user data of the second logical address to the flash memory module; and

when the second logical address appears in the extended discard table, deleting an entry containing the second logical address from the extended discard table, and setting the end address register in the performance engine according to the updated content of the extended discard table for redefining an address range of the extended discard table stored in the random access memory.

4. The data access method in response to a host discard command as recited in claim 1, comprising:

receiving a host read command from a host, wherein the host read command indicates to read user data of a third logical address; and

and replying false data to the host side when the third logical address appears in the extended discard table.

5. The data access method in response to a host discard command as recited in claim 1, comprising:

configuring space in a random access memory to a discard queue, wherein the discard queue comprises a plurality of nodes, and each node is used for storing a logic address interval of discarded user data;

determining whether the number of the first logical addresses of the user data that are no longer used, indicated by the host discard command, exceeds or is equal to a specified number;

when the number of the first logical addresses exceeds or equals the specified number, newly adding a new entry containing the first logical address to the extended discard table, and setting the start address register and the end address register in the performance engine for redefining an address range of the extended discard table stored in the random access memory; and

when the number of the first logical addresses is lower than the specified number, a new node containing the first logical addresses is newly added to the discard queue.

6. The method for accessing data in response to a host discard command as recited in claim 5, comprising:

executing a host write command sent by the host side, wherein the host write command indicates to write user data of a fourth logical address into the flash memory module;

deleting a corresponding entry of the fourth logical address from the extended discard table when the fourth logical address appears in the extended discard table, and setting the end address register in the performance engine according to the updated contents of the extended discard table for defining a new address range in the random access memory; and

when the fourth logical address appears in the discard queue, updating contents in the discard queue to reflect the execution result of the host write command.

7. The method for accessing data in response to a host discard command as recited in claim 5, comprising:

receiving a host read command from a host, wherein the host read command indicates to read user data of a fifth logical address; and

and replying false data to the host side when the fifth logical address appears in the extended discard table or the discard queue.

8. A computer readable storage medium for storing a computer program executable by a processing unit, wherein the computer program when executed by the processing unit implements the data access method according to any one of claims 1 to 7 in response to a host discard command.

9. A data access apparatus responsive to a host discard command, comprising:

a random access memory for configuring a space to an extended discard table, wherein the extended discard table contains a plurality of entries, each of the entries recording a logical address of user data that has been discarded;

a performance engine including a start address register and an end address register for defining an address range in the random access memory in which the extended discard table is stored; and

a processing unit coupled to the random access memory and the performance engine for receiving a host discard command from a host, wherein the host discard command indicates a first logical address of user data that is no longer used; newly adding a new item containing the first logical address to the extended discard table; and setting the start address register and the end address register in the performance engine to redefine an address range of the extended discard table stored in the random access memory such that the performance engine searches the extended discard table through the address range in the random access memory to determine whether user data for a particular logical address has been no longer used.

10. The data access apparatus in response to a host discard command as recited in claim 9, wherein a plurality of the entries of the extended discard table are arranged in an ascending or descending manner depending on the logical address.

11. The data access device of claim 9, wherein the processing unit executes a host write command to write user data of the second logical address to the flash memory module; and deleting an entry containing the second logical address from the extended discard table when the second logical address is present in the extended discard table, and setting the end address register in the performance engine according to the updated contents of the extended discard table for redefining an address range of the extended discard table stored in the random access memory.

12. The data access device of claim 9, wherein the processing unit receives a host read command from a host, wherein the host read command indicates user data to read a third logical address; and replying false data to the host side when the third logical address appears in the extended discard table.

13. The data access apparatus according to claim 9, wherein the data access apparatus is configured to,

the random access memory configures a space for a discard queue, wherein the discard queue comprises a plurality of nodes, each node is used for storing a logic address interval of discarded user data,

the processing unit judges whether the number of the first logical addresses of the user data which are not used any more and indicated by the host discard command exceeds or is equal to a specified number; when the number of the first logical addresses exceeds or equals the specified number, newly adding a new entry containing the first logical address to the extended discard table, and setting the start address register and the end address register in the performance engine for redefining an address range of the extended discard table stored in the random access memory; and when the number of the first logical addresses is lower than the specified number, adding a new node containing the first logical addresses to the discard queue.

14. The data access device according to claim 13, wherein the processing unit executes a host write command sent from the host side, wherein the host write command indicates to write user data of a fourth logical address to the flash memory module; deleting a corresponding entry of the fourth logical address from the extended discard table when the fourth logical address appears in the extended discard table, and setting the end address register in the performance engine according to the updated contents of the extended discard table for defining a new address range in the random access memory; and updating contents of the discard queue to reflect an execution result of the host write command when the fourth logical address appears in the discard queue.

15. The data access device of claim 13, wherein the processing unit receives a host read command from a host, wherein the host read command indicates user data to read a fifth logical address; and replying false data to the host side when the fifth logical address appears in the extended discard table or the discard queue.