CN116931811A - Data processing methods, devices and storage media - Google Patents

Abstract

The disclosure relates to a data processing method, a data processing device and a storage medium. The method comprises the following steps: under the condition that the first memory chip receives data to be processed, determining the priority of the data to be processed; determining a target storage unit corresponding to the priority from at least two storage units of the first storage chip; each storage unit has a corresponding data reading and writing speed; and writing the data to be processed into the target storage unit. By setting, in the first memory chip, memory cells having corresponding data read-write speeds for data of different priorities. The method has the advantages that the data read-write speed of the determined target storage unit is matched with the priority of the data to be processed, the data read-write efficiency is improved, the data with different priorities can be written into different storage units, the probability of frequently erasing a certain storage unit can be reduced, the service lives of the storage units are prolonged, and the overall service life of the first storage chip is prolonged.

Description

Data processing methods, devices and storage media

Technical field

The present disclosure relates to data storage technology, and in particular, to a data processing method, device and storage medium.

Background technique

As the storage capacity of computer flash memory chips (such as Nand chips) becomes larger and larger, in order to make electronic devices have larger storage space, flash memory chips will be used in electronic devices.

During the operation of an electronic device, business data will be generated. Generally, the business data will be stored in the physical memory of the electronic device. When the physical memory of the electronic device is full, part of the data in the physical memory will be stored. Cleared, or swapped into the flash memory chip of the electronic device through swap (SWAP) technology.

However, the flash memory chip will directly store the exchange data into the default storage unit, but the data reading and writing speed of the default storage unit does not match the exchange data, which will affect the reading and writing efficiency of the exchange data, and for the default storage unit Frequent erase and write operations will affect the service life of the default storage unit.

Contents of the invention

The present disclosure provides a data processing method, device and storage medium.

According to a first aspect of an embodiment of the present disclosure, a data processing method is provided, including:

When the first memory chip receives the data to be processed, determine the priority of the data to be processed;

Determine a target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data reading and writing speed;

Write the data to be processed into the target storage unit.

Optionally, determining a target storage unit corresponding to the priority level from at least two storage units of the first memory chip includes:

When the priority of the data to be processed satisfies the preset priority condition, the storage unit with the highest data reading and writing speed among the at least two storage units is determined as the target storage unit.

Optionally, the method also includes:

Obtain the data identifier of the data to be processed;

When the data identification indicates that the data to be processed is data read from the second memory chip, it is determined that the priority of the data to be processed satisfies the preset priority condition.

Optionally, determining the storage unit with the highest data reading and writing speed among the at least two storage units as the target storage unit includes:

Determine whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the data amount of the data to be processed;

When the storage margin is greater than the data amount of the data to be processed, the storage unit with the highest data reading and writing speed is determined as the target storage unit.

Optionally, the method also includes:

When the amount of data in the second memory chip is greater than the preset data threshold, determine the data to be processed from the data that has been stored in the second memory chip;

When the data to be processed is read out of the second memory chip, a data identifier corresponding to the data to be processed is generated;

The data to be processed carrying the data identifier is transmitted to the first memory chip.

Optionally, the at least two storage units include: a first SLC storage unit, a second SLC storage unit and a TLC storage unit;

Wherein, the data reading and writing speed of the first SLC storage unit is equal to the data reading and writing speed of the second SLC storage unit, and the data reading and writing speeds of the first SLC storage unit and the second SLC storage unit are greater than The data reading and writing speed of the TLC storage unit.

According to a second aspect of the embodiment of the present disclosure, a data processing device is provided, including:

A first determination module configured to determine the priority of the data to be processed when the first memory chip receives the data to be processed;

The second determination module is configured to determine the target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data reading and writing speed. ;

A writing module configured to write the data to be processed into the target storage unit.

Optionally, the second determination module is configured as:

When the priority of the data to be processed satisfies the preset priority condition, the storage unit with the highest data reading and writing speed among the at least two storage units is determined as the target storage unit.

Optionally, the device also includes:

An acquisition module configured to acquire the data identifier of the data to be processed;

A third determination module configured to determine that the priority of the data to be processed satisfies the preset priority condition when the data identifier indicates that the data to be processed is data read from the second memory chip. .

Optionally, the second determination module is configured as:

Determine whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the data amount of the data to be processed;

When the storage margin is greater than the data amount of the data to be processed, the storage unit with the highest data reading and writing speed is determined as the target storage unit.

Optionally, the device also includes:

A fourth determination module configured to determine the data to be processed from the data that has been stored in the second memory chip when the amount of data in the second memory chip is greater than the preset data threshold;

A generation module configured to generate a data identifier corresponding to the data to be processed when the data to be processed is read out of the second memory chip;

A transmission module configured to transmit the data to be processed carrying the data identifier to the first memory chip.

Optionally, the at least two storage units include: a first SLC storage unit, a second SLC storage unit and a TLC storage unit;

Wherein, the data reading and writing speed of the first SLC storage unit is equal to the data reading and writing speed of the second SLC storage unit, and the data reading and writing speeds of the first SLC storage unit and the second SLC storage unit are greater than The data reading and writing speed of the TLC storage unit.

According to a third aspect of the embodiment of the present disclosure, a data processing device is provided, including:

processor;

Memory configured to store instructions executable by the processor;

Wherein, the processor is configured to: when executed, implement the steps in any one of the data processing methods in the above first aspect.

According to a fourth aspect of an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, which when instructions in the storage medium are executed by a processor of a data processing device, enables the device to perform the above first aspect steps in any of the data processing methods.

The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

According to the technical solution of the present disclosure, after the first memory chip receives the data to be processed, it can determine the priority of the data to be processed, and determine the priority level from at least two memory units of the first memory chip. The corresponding target storage unit, and stores the data to be processed in the target storage unit.

By arranging storage units with corresponding data reading and writing speeds in the first memory chip for data of different priorities. In the process of use, the priority of the data to be processed can be judged first, and the storage unit corresponding to the priority can be determined, so that the data reading and writing speed of the determined target storage unit can match the priority of the data to be processed. This improves data reading and writing efficiency. Moreover, compared with the related technology where all data is stored in the default storage unit, data with different priorities can be written into different storage units, which can reduce the probability of frequently erasing a certain storage unit, thereby reducing the probability of frequent erasure of a certain storage unit. The service life of each memory unit is improved, thereby improving the overall service life of the first memory chip.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the present disclosure.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a flowchart of a data processing method according to an exemplary embodiment.

FIG. 2 is a schematic diagram of data storage of a second memory chip according to an exemplary embodiment.

FIG. 3 is a schematic diagram of a first memory chip according to an exemplary embodiment.

FIG. 4 is a schematic diagram of an architecture for data processing according to an exemplary embodiment.

Figure 5 is a block diagram of a data processing device according to an exemplary embodiment.

Figure 6 is a hardware structure block diagram 1 of a data processing device according to an exemplary embodiment.

Figure 7 is a second hardware structure block diagram of a data processing device according to an exemplary embodiment.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the disclosure as detailed in the appended claims.

Figure 1 is a flow chart of a data processing method according to an exemplary embodiment. As shown in Figure 1, the data processing method includes the following steps:

In step 101, when the first memory chip receives the data to be processed, determine the priority of the data to be processed;

In step 102, determine a target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data reading and writing speed;

In step 103, the data to be processed is written into the target storage unit.

It should be noted that the data processing method proposed in this disclosure can be applied to electronic devices or network servers. Here, the electronic devices can include: terminal devices, such as mobile terminals or fixed terminals. Among them, mobile terminals can include: mobile phones, tablets, laptops and other devices. Fixed terminals can include: desktop computers or smart TVs, etc.

Here, the first memory chip may be a storage device that can be used for data storage in the electronic device. In some embodiments, the first memory chip may include: a flash memory chip (Nand chip). For example, the first memory chip may include a universal flash storage (Universal Flash Storage, UFS) chip.

The data to be processed received by the first memory chip may include: data exchanged from other memory chips in the electronic device to the first memory chip; or data generated when an application in the electronic device is running, etc.

In some embodiments, the priority of the data to be processed may be determined based on the importance of the data to be processed; or the priority of the data to be processed may be determined based on the data reading and writing speed requirements of the data to be processed; or the priority of the data to be processed may be determined based on the Type, determine the priority of the data to be processed; or determine the priority of the data to be processed based on the source of the data to be processed.

Taking the priority of the data to be processed based on the importance of the data to be processed as an example, after the first memory chip receives the data to be processed, the importance of the data to be processed can be determined based on the data content of the data to be processed, and then based on The importance of the data to be processed and the first mapping relationship determine the priority of the data to be processed. The first mapping relationship can be used to represent the correlation between the importance and priority of the data, and can be set in advance, for example, through experiments or manually.

In some embodiments, the priority of the data to be processed may be positively related to the importance of the data to be processed. It can be understood that the higher the priority of the data to be processed, the higher the importance of the data to be processed; the lower the priority of the data to be processed, the lower the importance of the data to be processed. Here, the importance of the data to be processed can be set as needed, and is not specifically limited here.

Taking the priority of the data to be processed based on the data reading and writing speed requirements of the data to be processed as an example, after the first memory chip receives the data to be processed, the data to be processed can be determined according to the data content of the data to be processed. The read and write speed requirements, and then determine the priority of the data to be processed based on the data read and write speed requirements of the data to be processed and the second mapping relationship. Among them, the second mapping relationship can be used to represent the correlation between the data's demand for data reading and writing speed and the priority, and can be preset, for example, preset through experiments or preset manually. wait.

In some embodiments, the priority of the data to be processed may be positively related to the data reading and writing speed requirements of the data to be processed. It can be understood that the higher the priority of the data to be processed, the higher the demand for the data reading and writing speed of the data to be processed; the lower the priority of the data to be processed, the higher the demand for the data reading and writing speed of the data to be processed. Low.

The above is a partial enumeration and description of determining the priority of data to be processed. In other optional embodiments, the priority of data to be processed can also be determined in other ways, which is not specifically limited here.

In the embodiment of the present disclosure, the first memory chip may include at least two memory units, and each memory unit has a corresponding data reading and writing speed. By setting up multiple storage units with different data reading and writing speeds, it can provide more options for storing data to be processed and improve the flexibility of reading and writing data to be processed.

In the embodiment of the present disclosure, after determining the priority of the data to be processed, a target storage unit corresponding to the priority may be determined from at least two storage units included in the first memory chip.

In some embodiments, the mapping relationship between each priority and the storage unit may be preset, that is, the third mapping relationship. After the priority of the data to be processed is determined, the target storage unit corresponding to the priority may be determined according to the priority of the data to be processed and the third mapping relationship.

In some embodiments, the number of storage units may correspond to the number of priorities of the data to be processed. For example, the number of storage units and the number of priorities of the data to be processed can be the same. Assuming that the data to be processed can be divided into 10 priority levels, 10 storage units can be set accordingly. For another example, the number of storage units can be smaller than the number of priorities of the data to be processed. Assuming that the data to be processed can be divided into 10 priority levels, 3 storage units can be set correspondingly for the 1st to 4th levels of data to be processed. The data to be processed at the 5th to 7th levels can be stored in the second storage unit, and the data to be processed at the 8th to 10th levels can be stored in the third storage unit.

According to the technical solution of the present disclosure, after the first memory chip receives the data to be processed, it can determine the priority of the data to be processed, and determine the priority level from at least two memory units of the first memory chip. The corresponding target storage unit, and stores the data to be processed in the target storage unit.

By setting storage units with corresponding data reading and writing speeds in the first memory chip for data of different priorities. In the process of use, the priority of the data to be processed can be judged first, and the storage unit corresponding to the priority can be determined, so that the data reading and writing speed of the determined target storage unit can match the priority of the data to be processed. This improves data reading and writing efficiency. Moreover, compared with the related technology where all data is stored in the default storage unit, data with different priorities can be written into different storage units, which can reduce the probability of frequently erasing a certain storage unit, thereby reducing the probability of frequent erasure of a certain storage unit. The service life of each memory unit is improved, thereby improving the overall service life of the first memory chip.

In some embodiments, the at least two storage units may include: a first single-level storage unit (Single-Level Multi-Level Cell, SLC), a second SLC storage unit, and a triple-level storage unit (Triple-Level Cell, TLC);

Wherein, the data reading and writing speed of the first SLC storage unit is equal to the data reading and writing speed of the second SLC storage unit, and the data reading and writing speeds of the first SLC storage unit and the second SLC storage unit are greater than The data reading and writing speed of the TLC storage unit.

Of course, in other embodiments, the at least two storage units may also include: multi-level storage cells (Multi-Level Cell, MLC). The data reading and writing speed of the MLC storage unit is greater than the data reading and writing speed of the TLC storage unit, and is smaller than the data reading and writing speed of the second SLC storage unit.

In some embodiments, taking the first memory chip including a second SLC storage unit (Common SLC buffer) and a TLC storage unit as an example, when the electronic device initiates a data exchange (SWAP) request, the data to be processed will be transferred to The first memory chip, at this time, can first determine whether there is remaining space in the second SLC storage unit. If there is remaining space in the second SLC storage unit, it will first write the data to be processed into the second SLC storage unit.

Among them, the data to be processed can be: data that needs to be exchanged, which can also be called SWAP data or exchange data, or regular data. The exchange data is used to distinguish it from regular data. The exchange data can be data obtained based on an exchange request. Here, the exchange request is used to instruct the exchange of data in one memory chip to another memory chip. The regular data can be based on Data generated by the operation of applications in electronic devices. Among them, the priority of SWAP data is higher than that of regular data.

In some embodiments, in order to ensure the normal use of the second SLC storage unit and maintain good read and write performance of the first memory chip (eg, UFS chip), the controller inside the first memory chip will All data (including normal data and SWAP data) are transferred to the TLC storage unit, or if the remaining space of the second SLC storage unit is insufficient, all data is directly written to the TLC storage unit. If the data in the second SLC storage unit is frequently written into the TLC storage unit, or all data is directly written into the TLC storage unit, it will lead to frequent erasing and writing of the TLC storage unit, accelerating the wear and tear of the TLC storage unit, and thus causing the entire first The wear and tear of the memory chip affects the service life of the first memory chip.

Since the average erase and write life of SLC memory cells is greater than the average erase and write life of TLC memory cells, for example, the average erase and write life of SLC memory cells can be 100 times the average erase and write life of TLC memory cells, and the data reading of SLC memory cells The writing speed is greater than the data reading and writing speed of TLC memory cells.

In some embodiments, when there is a second SLC storage unit and a TLC storage unit in the first memory chip, the data to be processed with different priorities can be written to the second SLC respectively according to the priority of the data to be processed. memory cells and TLC memory cells. For example, when the data to be processed is SWAP data, it means that the priority of the data to be processed is higher. At this time, the data to be processed can be written into the second SLC storage unit; when the data to be processed is regular data, it means that it is to be processed. The data has a lower priority. At this time, the data to be processed can be written into the TLC storage unit.

In other embodiments, when the first memory chip has a first SLC storage unit, a second SLC storage unit and a TLC storage unit, the data to be processed with different priorities can be Data is written into the first SLC storage unit, the second SLC storage unit and the TLC storage unit respectively. For example, when the data to be processed is SWAP data, it means that the priority of the data to be processed is higher. At this time, the data to be processed can be written into the first SLC storage unit; when the data to be processed is regular data, it means that it is to be processed. The data has a lower priority. At this time, the data to be processed can be written into the second SLC storage unit or TLC storage unit.

In the embodiment of the present disclosure, the data that needs to be exchanged by the application program can be written into a specific storage unit (the first SLC storage unit, which may also be called SWAP SLC) first. In scenarios where SWAP technology is often used, there will be It helps to balance the wear of the first memory chip, thereby extending the overall service life of the first memory chip.

In some embodiments, determining a target storage unit corresponding to the priority level from at least two storage units of the first memory chip includes:

When the priority of the data to be processed satisfies the preset priority condition, the storage unit with the highest data reading and writing speed among the at least two storage units is determined as the target storage unit.

Here, the priority of the data to be processed satisfies a preset priority condition, including: the priority of the data to be processed is greater than or equal to a priority threshold. Here, the priority threshold can be a level value set as needed, which can be set at the time of the experiment or set manually.

During the implementation process, the priority of the data to be processed can be compared with the priority threshold. When the comparison result indicates that the priority of the data to be processed is greater than the priority threshold, it indicates that the priority of the data to be processed meets the preset priority conditions. , at this time, the storage unit with the highest data reading and writing speed can be determined as the target storage unit.

In some embodiments, at least two storage units may include a first storage unit, a second storage unit and a third storage unit, wherein the data reading and writing speed of the first storage unit is greater than that of the second storage unit, and the second storage unit The data reading and writing speed is greater than that of the third storage unit.

If the determined priority of the data to be processed is the first level and the priority threshold is the third level, it is determined that the priority of the data to be processed is greater than the priority threshold. At this time, the storage unit with the highest data reading and writing speed, that is, the first storage unit, can be determined as the target storage unit, and the data to be processed can be written into the target storage unit.

If the determined priority of the data to be processed is the fifth level and the priority threshold is the third level, it is determined that the priority of the data to be processed is less than the priority threshold. At this time, the second storage unit or the third storage unit may be determined as the target storage unit.

In other embodiments, taking the first storage unit as an SLC storage unit, the second storage unit as an MLC storage unit, and the third storage unit as a TLC storage unit as an example, if the data to be processed is SWAP data, it can be determined that the data to be processed is When the priority of the data meets the preset priority conditions, the data to be processed can be directly written into the SLC storage unit.

When the data to be processed is regular data, it means that the data to be processed does not meet the preset priority condition. At this time, the data to be processed can be written into the second SLC storage unit or TLC storage unit. For example, it can be determined first whether the storage margin of the second SLC storage unit is greater than the margin threshold, and if the storage margin of the second SLC storage unit is greater than the margin threshold, then the regular data is written into the second SLC storage unit; if the storage margin of the second SLC storage unit is greater than the margin threshold, If the storage margin of the second SLC storage unit is less than or equal to the margin threshold, the regular data is written into the TLC storage unit.

In the embodiment of the present disclosure, when the priority of the data to be processed meets the preset priority conditions, it indicates that the priority of the data to be processed is higher. At this time, the storage unit with the highest data reading and writing speed can be determined as the target. The storage unit can improve the efficiency of reading and writing data to be processed.

In some embodiments, the method further includes:

Obtain the data identifier of the data to be processed;

When the data identification indicates that the data to be processed is data read from the second memory chip, it is determined that the priority of the data to be processed satisfies the preset priority condition.

Here, after the first memory chip receives the data to be processed, it can determine whether the data to be processed carries a data identifier. If the data to be processed carries a data identifier, the data identifier can be obtained, and the determination is made based on the data identifier. The data to be processed is data read from the second memory chip.

Here, the second memory chip may include: a physical memory of the electronic device. For example, it may include double-rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM) or static random access memory (Static Random-Access Memory, SRAM) of electronic equipment.

In some embodiments, when the data to be processed carries the data identifier (Flag), it can be determined that the data to be processed is data read from the second memory chip. In this case, the data to be processed can be directly determined. Meet preset priority conditions.

That is to say, during the implementation process, data identification can be added to the data read from the second memory chip, while conventional data is not identified. In this way, when writing and storing data to be processed, the processing priority of the data to be processed can be quickly distinguished.

In other embodiments, different data to be processed can also be identified through different data identifiers. For example, the data read out from the second memory chip can be identified through the first data identifier; the data read out from the second memory chip can be identified through the second data identifier. Data identification identifies regular data. The first data identifier and the second data identifier may be numbers, letters, etc., as long as they can be easily distinguished by the controller of the first memory chip, and are not specifically limited here. For example, the first data identifier may be 1, the second data identifier may be 0, and so on.

In other words, during the implementation process, different data identifiers can be set for different data. In this way, when writing and storing data to be processed, the processing priority of the data to be processed can be quickly distinguished. Each data identifier can correspond to a priority. For example, when the data identifier is 1, it means that the priority of the data to be processed is higher, and when the data identifier is 0, it means that the priority of the data to be processed is lower, etc.

In the embodiment of the present disclosure, after the first memory chip receives the data to be processed, the processing priority of each data to be processed can be distinguished based on the data identification, and the target storage unit corresponding to the priority is determined, and the data to be processed is Writing processing data into the data to be processed can improve the convenience of data processing.

In some embodiments, the method further includes:

When the amount of data in the second memory chip is greater than the preset data threshold, determine the data to be processed from the data that has been stored in the second memory chip;

When the data to be processed is read out of the second memory chip, a data identifier corresponding to the data to be processed is generated;

The data to be processed carrying the data identifier is transmitted to the first memory chip.

Here, the second memory chip may include: a physical memory of the electronic device. For example, it may include Double Data Rate SDRAM (DDR SDRAM) of electronic equipment.

When the application program in the electronic device is running, it will occupy the storage space of the second memory chip. When multiple applications are running at the same time, the space in the second memory chip will be full. At this time, if the user needs to open another When an application program is running, the operating system of the electronic device will clear a part of the application data of the relatively inactive application program in the second memory chip, or exchange it to the first memory chip through the switching technology, so that when the application program needs to be awakened, Then, the application data of the application program is read out from the first memory chip.

Among them, the application data of a part of relatively inactive application programs in the second memory chip is the data to be processed in the embodiment of the present disclosure.

In the embodiment of the present disclosure, when the amount of data in the second memory chip is greater than the preset data threshold, it indicates that the storage space of the second memory chip is about to be filled up, or has been filled up. At this time, the stored data can be retrieved from the stored data. From the data sent to the second memory chip, the data to be processed is determined.

In some embodiments, when the amount of data in the second memory chip is greater than the preset data threshold, determining the data to be processed from the data that has been stored in the second memory chip includes:

When the amount of data in the second memory chip is greater than the preset data threshold, determine the application data in the inactive state in the second memory chip as the data to be processed;

Among them, the application data in the inactive state includes: application data of unused applications whose waiting time is longer than the preset time.

For example, after it is determined that the amount of data in the second memory chip has occupied 80% of the total storage space of the second memory chip, the unused application data of the application whose waiting time is longer than 2 hours can be determined as the waiting time. Data processing. The preset data threshold and the preset duration can be set as needed. For example, the preset data threshold can be determined based on the performance of the second memory chip, the preset duration can be determined based on the frequency of use of each application, etc.

Figure 2 is a schematic diagram of data storage of the second memory chip according to an exemplary embodiment. As shown in Figure 2, during the operation of the system, if the communication application and the music application are running at the same time, the system data will occupy the third memory chip. Part of the storage space of the second memory chip 201. The communication application program will occupy part of the storage space of the second memory chip 201. The music application program will occupy part of the storage space of the second memory chip 201. In this way, the second memory chip 201 may be damaged. Storage space is full.

In some embodiments, assuming that the storage space of the second memory chip is full, at this time, if a game application is opened, the system will exchange a part of the relatively inactive application data in the second memory chip to in the first memory chip. For example, if the waiting time for the music application to be unused is longer than the preset time, it is determined that the music application is relatively inactive. At this time, the application data of the music application can be exchanged to the first memory chip as data to be processed. When the music application needs to be awakened, the application data of the music application is read from the first memory chip.

The second memory chip may include a DDR chip; the first memory chip may include a UFS chip; and the electronic device may include a mobile phone.

Here, after the data to be processed is determined, the data to be processed needs to be read out from the second memory chip and exchanged to the first memory chip. When the data to be processed is read out of the second memory chip, a corresponding data corresponding to the data to be processed can be generated. Process the data identification of the data, and transmit the data to be processed carrying the data identification to the first memory chip.

The data identifier is used to indicate that the data to be processed is data read from the second memory chip, and the corresponding priority is higher than that of regular data.

In some embodiments, when the data to be processed is a data packet, a data identifier can be added to the header of the data packet to facilitate the data to be processed to carry the data identifier to the first memory chip.

In this disclosed embodiment, the system will use data identifiers to distinguish exchange data from regular data during the process of delivering data to be processed. For example, when the data identifier of the data to be processed is 1, it indicates that the data to be processed is exchange data. , In this way, when performing data analysis, the first memory chip can determine the priority of the data to be processed according to the data identifier, and then determine the target storage unit corresponding to the priority.

When the priority of the data to be processed is higher, the data reading and writing speed of the determined target storage unit is also faster. In this way, when the application program corresponding to the data to be processed needs to be activated, the speed of reading the data to be processed is also faster. It is fast and can restore the previously running application site more quickly, thereby completing fast switching.

In some embodiments, determining the storage unit with the highest data reading and writing speed among the at least two storage units as the target storage unit includes:

Determine whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the data amount of the data to be processed;

When the storage margin is greater than the data amount of the data to be processed, the storage unit with the highest data reading and writing speed is determined as the target storage unit.

In the embodiment of the present disclosure, when the data identifier indicates that the data to be processed is data read from the second memory chip, it may first be determined whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the data to be processed. amount of data. When the storage margin of the storage unit with the highest data reading and writing speed is greater than the data amount of the data to be processed, the storage unit with the highest data reading and writing speed is determined as the target storage unit, and the data to be processed is stored in the target storage. unit.

In other embodiments, when the storage margin of the storage unit with the highest data reading and writing speed is less than or equal to the data amount of the data to be processed, the storage unit with the second highest data reading and writing speed among the at least two storage units may be The unit is determined as the target storage unit.

The storage unit with the highest data reading and writing speed may include a first SLC storage unit, and the storage unit with the second highest data reading and writing speed may include a second SLC storage unit. Of course, the storage unit with the highest data reading and writing speed may also include: a first SLC storage unit, and the storage unit with the second highest data reading and writing speed may include a TLC storage unit. Alternatively, the storage unit with the highest data reading and writing speed may include: a first SLC storage unit, and the storage unit with the second highest data reading and writing speed may include an MLC storage unit. It can be flexibly determined according to the type of memory cells included in the first memory chip.

In other embodiments, it may also be determined whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the storage margin threshold. If the storage margin is greater than the storage margin threshold, the storage unit with the highest data reading and writing speed is The storage unit is determined as the target storage unit, and the data to be processed is stored in the target storage unit.

In other embodiments, when the storage margin of the storage unit with the highest data reading and writing speed is less than or equal to the storage margin threshold, the storage unit with the second highest data reading and writing speed among the at least two storage units may be determined. is the target storage unit.

Before storing the data to be processed, the storage margin of the storage unit with the highest data reading and writing speed is first judged. When the storage margin of the storage unit with the highest data reading and writing speed is sufficient, the data to be processed is then written. By inserting the storage unit into the storage unit, the possibility of losing the data to be processed due to insufficient storage margin of the storage unit can be reduced.

When the storage margin of the storage unit is insufficient, writing the data to be processed into the storage unit with the second highest data reading and writing speed can also achieve a balance of data stored in each storage unit.

In some embodiments, when the electronic device is initialized and configured, a first SLC storage unit can be set inside the first memory chip of the electronic device for the data exchange function of the first memory chip, and the first SLC memory cells as high-speed data. The second SLC storage unit and the TLC storage unit are set simultaneously.

Figure 3 is a schematic diagram of a first memory chip according to an exemplary embodiment. As shown in Figure 3, the first memory chip 301 includes: a first SLC memory unit (SWAP SLC) and a second SLC memory unit (Common SLC). and TLC storage unit (TLC Area).

Figure 4 is an architectural schematic diagram of data processing according to an exemplary embodiment. As shown in Figure 4, a storage device controller (Storage Device Controller) 401 includes: a central processing unit (Central Processing Unit, CPU), static random access Memory (SRAM)), flash memory chip controller (Nand Controller). The first memory chip 301 includes: a first SLC memory unit, a second SLC memory unit and a TLC memory unit. During the implementation process, the host (Host) 402 can interact with the storage device controller 401 through the switching interface (SWAP IO) and the general interface (General IO).

In the embodiment of the present disclosure, the first SLC storage unit is separately set up in the first memory chip to be used exclusively for data to be processed (such as SWAP data) with higher priority. It is assumed that the second memory chip (physical memory, such as DDR ) has been fully occupied. If the first application needs to be opened at this time, the system will use the application data of the relatively least active second application in the second memory chip as pending data and write it into the first memory chip. in an SLC storage unit.

When the data to be processed is read out, a data flag (SWAP Flag) of the data to be processed is generated. For example, the data flag of the data to be processed is set to 1. This data flag is used to identify the data to be processed as SWAP data. After the first memory chip receives the data to be processed, when the controller of the first memory chip determines that the data identifier of the data to be processed indicates that the data to be processed is data read from the second memory chip, the controller of the first memory chip will write the data to be processed. Enter the first SLC storage unit (SWAPSLC). Since the data reading and writing speed of the first SLC storage unit is relatively high, it can have better reading and writing performance when exchanging data, and when reading the data to be processed from the first memory chip, it can improve the efficiency of inactive data processing. The speed at which the status application switches to the active state, thereby improving the user experience.

In the embodiment of the present disclosure, the first SLC storage unit (SWAP SLC) can be opened for SWAP data, and the SWAP data can be identified through data identification. Then, when receiving the SWAP data, the first memory chip will write all the SWAP data. into the first SLC storage unit. When the user needs to switch an inactive application to an active state, the previously running application can be restored more quickly, allowing the user to switch between multiple applications more smoothly, making Users can experience the feeling of multiple applications resident at the same time.

Figure 5 is a block diagram of a data processing device according to an exemplary embodiment. As shown in Figure 5, the data processing device 500 mainly includes:

The first determination module 501 is configured to determine the priority of the data to be processed when the first memory chip receives the data to be processed;

The second determination module 502 is configured to determine a target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data read and write function. speed;

The writing module 503 is configured to write the data to be processed into the target storage unit.

In some embodiments, the second determination module 502 is configured as:

When the priority of the data to be processed satisfies the preset priority condition, the storage unit with the highest data reading and writing speed among the at least two storage units is determined as the target storage unit.

In some embodiments, the apparatus 500 further includes:

An acquisition module configured to acquire the data identifier of the data to be processed;

A third determination module configured to determine that the priority of the data to be processed satisfies the preset priority condition when the data identifier indicates that the data to be processed is data read from the second memory chip. .

In some embodiments, the second determination module 502 is configured as:

Determine whether the storage margin of the storage unit with the highest data reading and writing speed is greater than the data amount of the data to be processed;

When the storage margin is greater than the data amount of the data to be processed, the storage unit with the highest data reading and writing speed is determined as the target storage unit.

In some embodiments, the apparatus 500 further includes:

A fourth determination module configured to determine the data to be processed from the data that has been stored in the second memory chip when the amount of data in the second memory chip is greater than the preset data threshold;

A generation module configured to generate a data identifier corresponding to the data to be processed when the data to be processed is read out of the second memory chip;

A transmission module configured to transmit the data to be processed carrying the data identifier to the first memory chip.

In some embodiments, the at least two storage units include: a first SLC storage unit, a second SLC storage unit and a TLC storage unit;

Wherein, the data reading and writing speed of the first SLC storage unit is equal to the data reading and writing speed of the second SLC storage unit, and the data reading and writing speeds of the first SLC storage unit and the second SLC storage unit are greater than The data reading and writing speed of the TLC storage unit.

Regarding the devices in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

Figure 6 is a hardware structure block diagram 1 of a data processing device according to an exemplary embodiment. For example, the device 700 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

Referring to Figure 6, apparatus 700 may include one or more of the following components: processing component 702, memory 704, power supply component 706, multimedia component 708, audio component 710, input/output (I/O) interface 712, sensor component 714, and Communication component 716.

Processing component 702 generally controls the overall operations of device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the above method. Additionally, processing component 702 may include one or more modules that facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702.

Memory 704 is configured to store various types of data to support operations at device 700 . Examples of such data include instructions for any application or method operating on device 700, contact data, phonebook data, messages, pictures, videos, etc. Memory 704 may be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EEPROM), Programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

Power supply component 706 provides power to the various components of device 700 . Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to device 700 .

Multimedia component 708 includes a screen that provides an output interface between the device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide action. In some embodiments, multimedia component 708 includes a front-facing camera and/or a rear-facing camera. When the device 700 is in an operating mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front-facing camera and rear-facing camera can be a fixed optical lens system or have a focal length and optical zoom capabilities.

Audio component 710 is configured to output and/or input audio signals. For example, audio component 710 includes a microphone (MIC) configured to receive external audio signals when device 700 is in operating modes, such as call mode, recording mode, and speech recognition mode. The received audio signal may be further stored in memory 704 or sent via communication component 716 . In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

The I/O interface 712 provides an interface between the processing component 702 and a peripheral interface module, which may be a keyboard, a click wheel, a button, etc. These buttons may include, but are not limited to: Home button, Volume buttons, Start button, and Lock button.

Sensor component 714 includes one or more sensors that provide various aspects of status assessment for device 700 . For example, sensor component 714 can detect the open/closed state of device 700, the relative positioning of components, such as the display and keypad of device 700, and sensor component 714 can also detect a change in position of device 700 or a component of device 700. , the presence or absence of user contact with device 700 , device 700 orientation or acceleration/deceleration and temperature changes of device 700 . Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

Communication component 716 is configured to facilitate wired or wireless communication between apparatus 700 and other devices. Device 700 may access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In one exemplary embodiment, communication component 716 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communications component 716 also includes a near field communications (NFC) module to facilitate short-range communications. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

In an exemplary embodiment, apparatus 700 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable Gate array (FPGA), controller, microcontroller, microprocessor or other electronic components are implemented for executing the above method.

In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as a memory 704 including instructions, which are executable by the processor 720 of the device 700 to complete the above method is also provided. For example, the non-transitory computer-readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

A non-transitory computer-readable storage medium that, when instructions in the storage medium are executed by a processor of a mobile terminal, enables the mobile terminal to perform a data processing method, the method comprising:

When the first memory chip receives the data to be processed, determine the priority of the data to be processed;

Determine a target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data reading and writing speed;

Write the data to be processed into the target storage unit.

Figure 7 is a second hardware structure block diagram of a data processing device according to an exemplary embodiment. For example, device 800 may be provided as a server. Referring to Figure 7, apparatus 800 includes a processing component 822, which further includes one or more processors, and memory resources represented by memory 832 for storing instructions, such as application programs, executable by processing component 822. The application program stored in memory 832 may include one or more modules, each corresponding to a set of instructions. Additionally, processing component 822 is configured to execute instructions to perform a data processing method including:

When the first memory chip receives the data to be processed, determine the priority of the data to be processed;

Determine a target storage unit corresponding to the priority level from at least two storage units of the first memory chip; wherein each of the storage units has a corresponding data reading and writing speed;

Write the data to be processed into the target storage unit.

Device 800 may also include a power supply component 826 configured to perform power management of device 800, a wired or wireless network interface 850 configured to connect device 800 to a network, and an input/output (I/O) interface 858. The device 800 may operate based on an operating system stored in the memory 832, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™ or the like.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the disclosure that follow the general principles of the disclosure and include common common sense or customary technical means in the technical field that are not disclosed in the disclosure. . It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the disclosure is limited only by the appended claims.

Claims (14)

1. A method of data processing, comprising:

under the condition that the first storage chip receives data to be processed, determining the priority of the data to be processed;

determining a target storage unit corresponding to the priority from at least two storage units of the first storage chip; wherein each storage unit has a corresponding data reading and writing speed;

and writing the data to be processed into the target storage unit.

2. The method of claim 1, wherein the determining a target memory location corresponding to the priority from at least two memory locations of the first memory chip comprises:

and under the condition that the priority of the data to be processed meets the preset priority condition, determining the storage unit with the highest data reading and writing speed from the at least two storage units as the target storage unit.

3. The method according to claim 2, wherein the method further comprises:

Acquiring a data identifier of the data to be processed;

and under the condition that the data identifier indicates that the data to be processed is the data read out from the second memory chip, determining that the priority of the data to be processed meets the preset priority condition.

4. The method according to claim 2, wherein determining a memory cell having a highest data read/write speed among the at least two memory cells as the target memory cell includes:

determining whether the storage margin of a storage unit with the highest data reading and writing speed is larger than the data volume of the data to be processed;

and determining a storage unit with the highest data reading and writing speed as the target storage unit under the condition that the storage margin is larger than the data quantity of the data to be processed.

5. The method according to claim 1, wherein the method further comprises:

under the condition that the data amount in the second memory chip is larger than a preset data threshold value, determining the data to be processed from the data stored in the second memory chip;

generating a data identifier corresponding to the data to be processed when the data to be processed is read out of the second memory chip;

And transmitting the data to be processed carrying the data identifier to the first memory chip.

6. The method according to any one of claim 1 to 5, wherein,

the at least two memory cells include: a first SLC memory cell, a second SLC memory cell, and a TLC memory cell;

the data read-write speed of the first SLC storage unit is equal to the data read-write speed of the second SLC storage unit, and the data read-write speeds of the first SLC storage unit and the second SLC storage unit are larger than the data read-write speed of the TLC storage unit.

7. A data processing apparatus, comprising:

the first determining module is configured to determine the priority of the data to be processed under the condition that the first memory chip receives the data to be processed;

a second determining module configured to determine a target storage unit corresponding to the priority from at least two storage units of the first storage chip; wherein each storage unit has a corresponding data reading and writing speed;

and the writing module is configured to write the data to be processed into the target storage unit.

8. The apparatus of claim 7, wherein the second determination module is configured to:

And under the condition that the priority of the data to be processed meets the preset priority condition, determining the storage unit with the highest data reading and writing speed from the at least two storage units as the target storage unit.

9. The apparatus of claim 8, wherein the apparatus further comprises:

the acquisition module is configured to acquire a data identifier of the data to be processed;

and the third determining module is configured to determine that the priority of the data to be processed meets the preset priority condition under the condition that the data identifier indicates that the data to be processed is the data read out from the second memory chip.

10. The apparatus of claim 8, wherein the second determination module is configured to:

determining whether the storage margin of a storage unit with the highest data reading and writing speed is larger than the data volume of the data to be processed;

and determining a storage unit with the highest data reading and writing speed as the target storage unit under the condition that the storage margin is larger than the data quantity of the data to be processed.

11. The apparatus of claim 7, wherein the apparatus further comprises:

a fourth determining module configured to determine the data to be processed from the data already stored to the second memory chip, in the case where the amount of data in the second memory chip is greater than a preset data threshold;

A generation module configured to generate a data identifier corresponding to the data to be processed when the data to be processed is read out of the second memory chip;

and the transmission module is configured to transmit the data to be processed carrying the data identifier to the first memory chip.

12. The device according to any one of claims 7 to 11, wherein,

the at least two memory cells include: a first SLC memory cell, a second SLC memory cell, and a TLC memory cell;

the data read-write speed of the first SLC storage unit is equal to the data read-write speed of the second SLC storage unit, and the data read-write speeds of the first SLC storage unit and the second SLC storage unit are larger than the data read-write speed of the TLC storage unit.

13. A data processing apparatus, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to: the steps of the data processing method of any of the preceding claims 1 to 6 are implemented when executed.

14. A non-transitory computer readable storage medium, which when executed by a processor of a data processing apparatus, causes the apparatus to perform the steps of the data processing method of any of the preceding claims 1 to 6.