CN116938168A - Power amplifier and method for amplifying signal - Google Patents
Power amplifier and method for amplifying signal Download PDFInfo
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- CN116938168A CN116938168A CN202210331487.6A CN202210331487A CN116938168A CN 116938168 A CN116938168 A CN 116938168A CN 202210331487 A CN202210331487 A CN 202210331487A CN 116938168 A CN116938168 A CN 116938168A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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Abstract
The application provides a power amplifier and a method for amplifying a signal. The power amplifier includes: the circuit comprises a first circuit, a second circuit and a transformer. Wherein: the first circuit comprises a first amplifier and a second amplifier; the second circuit comprises a third amplifier and a fourth amplifier; the transformer comprises a first inductor and a second inductor, wherein the coupling coefficient of the first inductor and the second inductor is K, and K is larger than 0. The power amplifier amplifies a first input signal through a first amplifier, a third amplifier, a fourth power amplifier tube and an eighth power amplifier tube in a first working mode; and in a second working mode, the power amplifier amplifies a second input signal through the second amplifier, the fourth amplifier, the third power amplifier tube and the seventh power amplifier tube. According to the device disclosed by the application, the transformer is arranged at the middle node of the two paths of amplifiers, so that multiplexing of a plurality of power amplification tubes can be realized, the output power of signals is improved, and the transmission of high-bandwidth high-order quadrature amplitude modulation signals is satisfied.
Description
Technical Field
The present application relates to the field of communication technology, and more particularly, to a power amplifier and a method of amplifying a signal.
Background
With the development of communication technology and the current external environment, there is an increasing demand for services such as home offices and video conferences, which generally require high-speed and stable communication conditions. Currently, expanding signal bandwidth and increasing spectrum utilization are two of the most common means of increasing the rate of a communication system. For example, with the development of wireless fidelity (wireless fidelity, wi-Fi) technology, the signal bandwidth has been expanding from 20MHz at 802.11g to 160MHz at 802.11ax, and the modulated signal has been modulated from orthogonal frequency division multiplexing (orthogonal frequency division multiplexing, OFDM) 64-quadrature amplitude modulation (quadrature amplitude modulation, QAM). This has led to a rise in the rate of the communication system from 38Mbps to 10Gbps.
A Power Amplifier (PA) is used as a core functional module in the communication transmission link to realize high-power amplification output of signals. The transmission of higher order QAM signals requires higher linearity of the PA, e.g., lower amplitude-to-amplitude modulation (amplitude to amplitude, AM-AM) distortion and amplitude-to-phase modulation (amplitude to phase modulation, AM-PM) distortion.
Therefore, a power amplifier and a method for amplifying a signal are needed to increase the output power of the signal, so as to satisfy the transmission of high-bandwidth, high-order quadrature amplitude modulation signals.
Disclosure of Invention
The application provides a power amplifier and a signal amplifying method, which can improve the output power of signals and meet the transmission of high-bandwidth high-order quadrature amplitude modulation signals.
In a first aspect, a power amplifier is provided. The power amplifier includes: the first amplifier, second amplifier, third amplifier, fourth amplifier and transformer, first amplifier and second amplifier parallel, third amplifier and fourth amplifier parallel, wherein: the first amplifier comprises a first power amplifier tube and a third power amplifier tube, and the first power amplifier tube is connected with the third power amplifier tube in series; the second amplifier comprises a second power amplifier tube and a fourth power amplifier tube, and the second power amplifier tube is connected in series with the fourth power amplifier tube; the third amplifier comprises a fifth power amplifier tube and a seventh power amplifier tube, and the fifth power amplifier tube is connected with the seventh power amplifier tube in series; the fourth amplifier comprises a sixth power amplifier tube and an eighth power amplifier tube, and the sixth power amplifier tube is connected with the eighth power amplifier tube in series; the transformer comprises a first inductor and a second inductor, the first inductor is connected with the first amplifier and the third amplifier, the second inductor is connected with the second amplifier and the fourth amplifier, and the coupling coefficient of the first inductor and the second inductor is K, wherein K is larger than 0; when the power of the input signal is smaller than a preset value, the second inductor controls the fourth power amplification tube and the eighth power amplification tube to work, so that the power amplifier amplifies the input signal through the first amplifier, the third amplifier, the fourth power amplification tube and the eighth power amplification tube to obtain a first output signal; or when the power of the input signal is greater than or equal to a preset value, the first inductor controls the third power amplifier tube and the seventh power amplifier tube to work, so that the power amplifier amplifies the input signal through the second amplifier, the fourth amplifier, the third power amplifier tube and the seventh power amplifier tube to obtain a second output signal.
According to the device disclosed by the application, the transformer is arranged at the middle node of the two paths of amplifiers, so that multiplexing of a plurality of power amplification tubes can be realized, the output power of signals is improved, and the transmission of high-bandwidth high-order quadrature amplitude modulation signals is satisfied.
With reference to the first aspect, in some implementations of the first aspect, the power amplifier further includes a first capacitor and a second capacitor, a first end of the first capacitor is connected to the first inductor, a second end of the first capacitor is grounded, a first end of the second capacitor is connected to the second inductor, and a second end of the second capacitor is grounded; when the power of the input signal is smaller than a preset value, the power amplifier controls the linearity of the first output signal by adjusting at least one of the first capacitor and the second capacitor; alternatively, when the power of the input signal is greater than or equal to a preset value, the power amplifier controls the linearity of the second output signal by adjusting at least one of the first capacitor and the second capacitor.
According to the device disclosed by the application, the capacitor connected with the inductor is arranged, so that the size of the capacitor can be adjusted according to the power of an input signal, the second harmonic impedance of the output end of the power amplifier tube is enabled to be zero, and the linearity of the output signal is improved.
With reference to the first aspect, in some implementations of the first aspect, bias voltages of the third power amplifier tube and the fourth power amplifier tube are provided in a unified manner or provided separately, and bias voltages of the seventh power amplifier tube and the eighth power amplifier tube are provided in a unified manner or provided separately. In this way, when bias voltages of a plurality of power amplifier tubes are provided uniformly, the performance of the amplifier does not need to be considered, and the implementation mode is simple and convenient; when the bias voltages of the power amplifier tubes are respectively provided, the bias voltage of each power amplifier tube can be determined according to actual conditions, so that the optimization of the overall performance of the amplifier is facilitated.
With reference to the first aspect, in some implementations of the first aspect, the first power amplifier tube and the second power amplifier tube are commonly sourced, and the fifth power amplifier tube and the sixth power amplifier tube are commonly sourced.
With reference to the first aspect, in certain implementations of the first aspect, the power amplifier further includes a first feedback circuit, a first end of the first feedback circuit is connected to input terminals of the first amplifier and the second amplifier, a second end of the first feedback circuit is connected to output terminals of the first amplifier and the second amplifier, and the first feedback circuit is used for adjusting amplification factors of the first amplifier and the second amplifier.
With reference to the first aspect, in certain implementations of the first aspect, the power amplifier further includes a second feedback circuit, a first end of the second feedback circuit is connected to input terminals of the third amplifier and the fourth amplifier, a second end of the second feedback circuit is connected to output terminals of the third amplifier and the fourth amplifier, and the second feedback circuit is used for adjusting amplification factors of the third amplifier and the fourth amplifier.
The device disclosed by the application can ensure the stable operation of the amplifier and avoid the occurrence of oscillation phenomenon by arranging the feedback circuit.
With reference to the first aspect, in certain implementations of the first aspect, the power amplifier further includes an output matching network, where the output matching network is connected to the output of the first amplifier, the output of the second amplifier, the output of the third amplifier, and the output of the fourth amplifier. In this way, the load impedance can be matched to the optimal load impedance of the amplifier through the output matching network, which is beneficial to improving the performance of the amplifier.
With reference to the first aspect, in some implementations of the first aspect, the power amplifier further includes a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, where the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are used to isolate direct current, the third capacitor is located between the first power amplifier tube and an input terminal of the first amplifier, the fourth capacitor is located between the second power amplifier tube and an input terminal of the second amplifier, the fifth capacitor is located between the fifth power amplifier tube and an input terminal of the third amplifier, and the sixth capacitor is located between the sixth power amplifier tube and an input terminal of the fourth amplifier.
With reference to the first aspect, in certain implementations of the first aspect, at least one of the first inductance, the second inductance, and the coupling coefficient K is adjustable. In so doing, the gain and linearity of the amplifier may be adjusted so that the amplifier of the present application may be adapted to different application scenarios.
In a second aspect, a method of amplifying a signal is provided. The method comprises the following steps: when the power of the input signal is smaller than a preset value, amplifying the input signal through a first amplifier, a third amplifier, a fourth power amplifier tube and an eighth power amplifier tube to obtain a first output signal; or when the power of the input signal is greater than or equal to a preset value, amplifying the input signal through a second amplifier, a fourth amplifier, a third power amplifier tube and a seventh power amplifier tube to obtain a second output signal; the first amplifier is connected with the second amplifier in parallel, the third amplifier is connected with the fourth amplifier in parallel, the first amplifier comprises a first power amplifier tube and a third power amplifier tube, the second amplifier comprises a second power amplifier tube and a fourth power amplifier tube, the third amplifier comprises a fifth power amplifier tube and a seventh power amplifier tube, the fourth amplifier comprises a sixth power amplifier tube and an eighth power amplifier tube, the first amplifier is connected with the third amplifier through a first inductor, the second amplifier is connected with the fourth amplifier through a second inductor, and the coupling coefficient of the first inductor and the second inductor is K, and K is larger than 0.
According to the method disclosed by the application, the transformer is arranged at the intermediate node of the two paths of amplifiers, so that multiplexing of a plurality of power amplification tubes can be realized, the output power of signals is improved, and the transmission of high-bandwidth high-order quadrature amplitude modulation signals is satisfied.
With reference to the second aspect, in some implementations of the second aspect, the power amplifier further includes a first capacitor and a second capacitor, a first end of the first capacitor is connected to the first inductor, a second end of the first capacitor is grounded, a first end of the second capacitor is connected to the second inductor, and a second end of the second capacitor is grounded, where the method further includes: when the power of the input signal is smaller than a preset value, controlling the linearity of the first output signal by adjusting at least one of the first capacitor and the second capacitor; or when the power of the input signal is greater than or equal to a preset value, controlling the linearity of the second output signal by adjusting at least one of the first capacitor and the second capacitor.
According to the method disclosed by the application, the capacitor connected with the inductor is arranged, so that the size of the capacitor can be adjusted according to the power of an input signal, the second harmonic impedance of the output end of the power amplifier tube is enabled to be zero, and the linearity of the output signal is improved.
Drawings
Fig. 1 is a schematic diagram showing an example of a two-stage power amplifier.
Fig. 2 is a schematic diagram of the structure of the current first power amplifier.
Fig. 3 is a schematic diagram of the structure of a third current power amplifier.
Fig. 4 is a schematic structural diagram of a first power amplifier according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a second power amplifier according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a third power amplifier according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a fourth power amplifier according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of a fifth power amplifier according to an embodiment of the present application.
Fig. 9 is a flowchart of a signal amplifying method according to an embodiment of the present application.
Detailed Description
The technical scheme of the application will be described below with reference to the accompanying drawings.
With the development of communication technology and the current external environment, there is an increasing demand for services such as home offices and video conferences, which generally require high-speed and stable communication conditions. Currently, expanding signal bandwidth and increasing spectrum utilization are two of the most common means of increasing the rate of a communication system. For example, with the development of Wi-Fi technology, the signal bandwidth has been extended from 20MHz for 802.11g to 160MHz for 802.11ax, and the modulated signal has been from OFDM64-QAM. This has led to a rise in the rate of the communication system from 38Mbps to 10Gbps.
The PA is used as a core functional module in the communication transmitting link to realize high-power amplification output of signals. The transmission of higher order QAM signals requires higher linearity of the PA, e.g., lower AM-AM distortion and AM-PM distortion.
Currently, complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) is widely used as a mainstream semiconductor process for implementation of various digital/analog signal processing chips, such as a common communication baseband and analog transceiver. PA is usually implemented by using a III-V semiconductor process such as GaAs (gallium arsenide), siGe (silicon germanium), gaN (gallium nitride) or the like as a final module of a transmitter, and cannot be fully integrated with a CMOS transceiver chip, which results in an increase in board area and an increase in cost. The PA developed based on the CMOS technology at present has the problems of low efficiency, low output power and the like, is suitable for narrow-band low-power scenes such as Bluetooth, zigbee protocol (Zigbee), narrow-band Internet of things (narrow band internet of things, NB-IoT) and the like, and can also be applied to an early WiFi system. In recent years, with the increasing commercial use of fiber to the room (Fiber to The Room, FTTR) and WiFi-6 technologies, the output power requirements for CMOS PAs have been greatly reduced, while WiFi-6 defines a signal with a maximum modulation order of 1024-QAM.
Therefore, there is a need for a power amplifier that can accommodate the transmission of high bandwidth, high order QAM signals.
The PA, as the endmost active device in a transmitter system, directly determines the power and quality of the transmitted signal, and in order to ensure the transmitted power of the signal, the power amplifier typically comprises a multi-stage amplifier.
Fig. 1 shows an example of a schematic diagram of a two-stage power amplifier. Since the signal is continuously amplified, the final stage amplifier usually works in a nonlinear region, the linearity of the signal is affected most, and the common technology for improving the linearity of the PA is mainly aimed at the final stage amplifier.
Fig. 2 shows a schematic diagram of the structure of a current first power amplifier. Fig. 2 (a) is a multi-gate transistor (multigated transistor, MGTR) technique in which M A1 And M M1 The circuit is connected with the drain terminals of Common Gate (CG) tubes by bias (V G2_M 、V G2_A ) Very sensitive, resulting in poor circuit performance. The design shown in FIG. 2 (b) improves on the MGTR technique by M A1 And M M1 Separation is carried out, so that the bias influence of two paths of CG pipes is avoided, and meanwhile, the bias voltage (V G1 、V B1_A 、V G2_M 、V G2_A ) May be provided separately to achieve optimum performance of the circuit. In the technical proposal, however, the negative substrate bias voltage V is increased B1_A The design difficulty of the on-chip bias voltage generating circuit is increased.
In addition, there is currently a second type of power amplifier that uses an asymmetric two-way cascode amplifier in combination, similar to the architecture of the existing Doherty (Doherty) amplifier. In the amplifier, low Power (LP) is biased at a Class-AB end, high Power (HP) is biased at a Class-C end, the AM-AM and AM-PM of the amplifier in two paths of different bias states are opposite in characteristics, nonlinear characteristic offset can be realized after synthesis, and the performance of the PA is improved. However, in the architecture of the amplifier, the bias of the two paths of the cascode amplifiers is different, so that the optimal load impedance is different, and output matching networks with different loads are required to be designed according to the working states of the LP and the HP, so that the design difficulty of the output network is increased.
Fig. 3 shows a schematic diagram of the structure of a third current power amplifier. As shown in fig. 3, in the design scheme of the power amplifier, an inductor Lx is added to the middle node of the two paths of the cascode amplifiers, and resonates with a parasitic capacitance at the middle node, so that the AM-PM distortion of the PA is reduced. After the inductance Lx is added, the AM-PM of the PA is significantly reduced under different bias conditions. However, in this technical scheme, only AM-PM distortion can be improved, and no improvement effect is provided for AM-AM distortion.
Based on the above, the application provides a power amplifier and a signal amplifying method, which are expected to improve the output power of signals and meet the transmission of high-bandwidth and high-order QAM signals.
Fig. 4 shows a schematic structural diagram of a first power amplifier according to an embodiment of the present application. As shown in fig. 4, the power amplifier 400 includes a first amplifier 411, a second amplifier 412, a third amplifier 421, a fourth amplifier 422, and a transformer 430. The first amplifier 411 is connected in parallel with the second amplifier 412, and the third amplifier 421 is connected in parallel with the fourth amplifier 422. Wherein: the first amplifier 411 comprises a first power amplifier tube 413 and a third power amplifier tube 414, and the first power amplifier tube 413 is connected with the third power amplifier tube 414 in series; the second amplifier 412 includes a second power amplifier tube 415 and a fourth power amplifier tube 416, and the second power amplifier tube 415 is connected in series with the fourth power amplifier tube 416; the third amplifier 421 includes a fifth power amplifier tube 423 and a seventh power amplifier tube 424, where the fifth power amplifier tube 423 is connected in series with the seventh power amplifier tube 424; the fourth amplifier 422 includes a sixth power amplifier tube 425 and an eighth power amplifier tube 426, the sixth power amplifier tube 425 being connected in series with the eighth power amplifier tube 426. The transformer 430 includes a first inductor 431 and a second inductor 432, the first inductor 431 is connected to the first amplifier 411 and the third amplifier 421, the second inductor 432 is connected to the second amplifier 412 and the fourth amplifier 422, and the coupling coefficient of the first inductor 431 and the second inductor 432 is K, where K is greater than 0. When the power of the input signal is smaller than the preset value, the second inductor 432 controls the fourth power amplifier tube 416 and the eighth power amplifier tube 426 to work, so that the power amplifier 400 amplifies the input signal through the first amplifier 411, the third amplifier 421 and the fourth power amplifier tube 416 and the eighth power amplifier tube 426 to obtain a first output signal; or, when the power of the input signal is greater than or equal to the preset value, the first inductor 431 controls the third power amplifier tube 414 and the seventh power amplifier tube 424 to work, so that the power amplifier 400 amplifies the input signal through the second amplifier 412, the fourth amplifier 422, the third power amplifier tube 421 and the seventh power amplifier tube 424, and a second output signal is obtained.
Optionally, the bias voltages of the third power amplifier tube 414 and the fourth power amplifier tube 416 are provided uniformly or respectively, and the bias voltages of the seventh power amplifier tube 424 and the eighth power amplifier tube 426 are provided uniformly or respectively. In this way, when bias voltages of a plurality of power amplifier tubes are provided uniformly, the performance of the amplifier does not need to be considered, and the implementation mode is simple and convenient; when the bias voltages of the power amplifier tubes are respectively provided, the bias voltage of each power amplifier tube can be determined according to actual conditions, so that the optimization of the overall performance of the amplifier is facilitated.
Optionally, the first power amplifier tube 413 and the second power amplifier tube 415 are commonly sourced, and the fifth power amplifier tube 423 and the sixth power amplifier tube 425 are commonly sourced.
Optionally, at least one of the first inductance 431, the second inductance 432 and the coupling coefficient K is adjustable. In so doing, the gain and linearity of the amplifier may be adjusted so that the amplifier of the present application may be adapted to different application scenarios.
According to the device disclosed by the application, the transformer is arranged at the middle node of the two paths of amplifiers, so that multiplexing of a plurality of power amplification tubes can be realized, the output power of signals is improved, and the transmission of high-bandwidth high-order quadrature amplitude modulation signals is satisfied.
Fig. 5 shows a schematic structural diagram of a second power amplifier according to an embodiment of the present application. As shown in fig. 5, the power amplifier 500 has a first capacitor 433 and a second capacitor 434 added thereto in addition to the power amplifier 400. A first end of the first capacitor 433 is connected with the first inductor 431, a second end of the first capacitor 433 is grounded, a first end of the second capacitor 434 is connected with the second inductor 432, and a second end of the second capacitor 434 is grounded; when the power of the input signal is less than the preset value, the power amplifier 500 controls the linearity of the first output signal by adjusting at least one of the first capacitor 433 and the second capacitor 434; alternatively, the power amplifier 500 controls the linearity of the second output signal by adjusting at least one of the first capacitor 433 and the second capacitor 434 when the power of the input signal is greater than or equal to a preset value.
According to the device disclosed by the application, the capacitor connected with the inductor is arranged, so that the size of the capacitor can be adjusted according to the power of an input signal, the second harmonic impedance of the output end of the power amplifier tube is enabled to be zero, and the linearity of the output signal is improved.
Fig. 6 shows a schematic structural diagram of a third power amplifier according to an embodiment of the present application. As shown in fig. 6, the power amplifier 600 is newly added with a first feedback circuit 441 and a second feedback circuit 442 on the basis of the power amplifier 500 or the power amplifier 400. The first feedback circuit 441 has a first end connected to input terminals of the first amplifier 411 and the second amplifier 412, and a second end of the first feedback circuit 442 is connected to output terminals of the first amplifier 411 and the second amplifier 412, and the first feedback circuit 441 is used for adjusting amplification factors of the first amplifier 411 and the second amplifier 412. The first end of the second feedback circuit 442 is connected to the input terminals of the third amplifier 421 and the fourth amplifier 422, the second end of the second feedback circuit 442 is connected to the output terminals of the third amplifier 421 and the fourth amplifier 422, and the second feedback circuit 442 is used for adjusting the amplification factors of the third amplifier 421 and the fourth amplifier 422.
It should be understood that, for convenience of description in fig. 6, the power amplifier 600 includes the first feedback circuit 441 and the second feedback circuit 442 at the same time, and in actual use, only one of the first feedback circuit 441 and the second feedback circuit 442 may be included in the power amplifier 600 according to application scenarios.
The device disclosed by the application can ensure the stable operation of the amplifier and avoid the occurrence of oscillation phenomenon by arranging the feedback circuit.
Fig. 7 is a schematic structural diagram of a fourth power amplifier according to an embodiment of the present application. As shown in fig. 7, the power amplifier 700 has an output matching network 451 added to the power amplifier 600. The output matching network 451 is connected to the output of the first amplifier 411, the output of the second amplifier 412, the output of the third amplifier 421 and the output of the fourth amplifier 422. In this way, the load impedance can be matched to the optimal load impedance of the amplifier through the output matching network, which is beneficial to improving the performance of the amplifier.
Fig. 8 is a schematic diagram of a fifth power amplifier according to an embodiment of the present application. As shown in fig. 8, the power amplifier 800 has a third capacitor 417, a fourth capacitor 418, a fifth capacitor 428 and a sixth capacitor 427 added to the power amplifier 700. The third capacitor 417, the fourth capacitor 418, the fifth capacitor 428 and the sixth capacitor 427 are used for isolating direct current, the third capacitor 417 is located between the first power amplifier tube 413 and the input end of the first amplifier 411, the fourth capacitor 418 is located between the second power amplifier tube 415 and the input end of the second amplifier 412, the fifth capacitor 428 is located between the fifth power amplifier tube 423 and the input end of the third amplifier 421, and the sixth capacitor 427 is located between the sixth power amplifier tube 425 and the input end of the fourth amplifier 422.
Fig. 9 is a schematic flow chart of a signal amplifying method according to an embodiment of the present application. The method is performed by one of the power amplifiers 400 to 800 described above.
S910, an input signal is acquired.
Specifically, two cases can be classified according to the power of an input signal.
Case 1:
and S920, when the power of the input signal is smaller than a preset value, amplifying the input signal through the first amplifier, the third amplifier, the fourth power amplifier tube and the eighth power amplifier tube to obtain a first output signal.
Optionally, when the power amplifier includes a first capacitor and a second capacitor, a first end of the first capacitor is connected with the first inductor, a second end of the first capacitor is grounded, a first end of the second capacitor is connected with the second inductor, and a second end of the second capacitor is grounded, the size of the capacitor can be adjusted according to the power of the input signal, so that the second harmonic impedance of the output end of the power amplifier tube is zero, and linearity of the output signal is improved.
S930, controlling linearity of the first output signal by adjusting at least one of the first capacitor and the second capacitor.
Case 2:
s940, when the power of the input signal is greater than or equal to a preset value, the input signal is amplified through the second amplifier, the fourth amplifier, the third power amplifier tube and the seventh power amplifier tube, and a second output signal is obtained.
Optionally, when the power amplifier includes a first capacitor and a second capacitor, a first end of the first capacitor is connected with the first inductor, a second end of the first capacitor is grounded, a first end of the second capacitor is connected with the second inductor, and a second end of the second capacitor is grounded, the size of the capacitor can be adjusted according to the power of the input signal, so that the second harmonic impedance of the output end of the power amplifier tube is zero, and linearity of the output signal is improved.
S950 controlling linearity of the second output signal by adjusting at least one of the first capacitance and the second capacitance.
According to the method disclosed by the application, the transformer is arranged at the intermediate node of the two paths of amplifiers, so that multiplexing of a plurality of power amplification tubes can be realized, the output power of signals is improved, and the transmission of high-bandwidth high-order quadrature amplitude modulation signals is satisfied.
The power amplifier provided by the application can be applied to the scenes of Bluetooth, fourth generation (4th generation,4G) communication systems (for example, a long term evolution (long term evolution, LTE) system), fifth generation (5th generation,5G) communication systems (for example, a New Radio (NR) system), millimeter wave communication and the like, and can be used for improving the performance of the PA in the scenes.
The embodiment of the application also provides a device which comprises a processor and an interface. The processor may be used to perform the methods of the method embodiments described above.
It should be understood that the processing means may be a chip. For example, the processing device may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processor unit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, or discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
It will be appreciated that the memory in embodiments of the application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
According to a method provided by an embodiment of the present application, the present application also provides a computer program product, including: computer program code to, when run on a computer, cause the computer to perform the method of the embodiment shown in fig. 9.
According to the method provided by the embodiment of the present application, the present application also provides a computer readable medium storing a program code which when run on a computer causes the computer to perform the method of the embodiment shown in fig. 9.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks (illustrative logical block) and steps (steps) described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A power amplifier, comprising: the first amplifier, second amplifier, third amplifier, fourth amplifier and transformer, first amplifier with the second amplifier is parallelly connected, the third amplifier with the fourth amplifier is parallelly connected, wherein:
the first amplifier comprises a first power amplifier tube and a third power amplifier tube, and the first power amplifier tube is connected in series with the third power amplifier tube;
the second amplifier comprises a second power amplifier tube and a fourth power amplifier tube, and the second power amplifier tube is connected in series with the fourth power amplifier tube;
the third amplifier comprises a fifth power amplifier tube and a seventh power amplifier tube, and the fifth power amplifier tube is connected with the seventh power amplifier tube in series;
the fourth amplifier comprises a sixth power amplifier tube and an eighth power amplifier tube, and the sixth power amplifier tube is connected with the eighth power amplifier tube in series;
the transformer comprises a first inductor and a second inductor, the first inductor is connected with the first amplifier and the third amplifier, the second inductor is connected with the second amplifier and the fourth amplifier, and the coupling coefficient of the first inductor and the second inductor is K, wherein K is larger than 0;
when the power of an input signal is smaller than a preset value, the second inductor controls the fourth power amplifier tube and the eighth power amplifier tube to work, so that the power amplifier amplifies the input signal through the first amplifier, the third amplifier, the fourth power amplifier tube and the eighth power amplifier tube to obtain a first output signal; or alternatively
When the power of the input signal is greater than or equal to a preset value, the first inductor controls the third power amplifier tube and the seventh power amplifier tube to work, so that the power amplifier amplifies the input signal through the second amplifier, the fourth amplifier, the third power amplifier tube and the seventh power amplifier tube to obtain a second output signal.
2. The power amplifier of claim 1, further comprising a first capacitor and a second capacitor, wherein a first end of the first capacitor is coupled to the first inductor, a second end of the first capacitor is coupled to ground, a first end of the second capacitor is coupled to the second inductor, a second end of the second capacitor is coupled to ground,
when the power of the input signal is smaller than a preset value, the power amplifier controls the linearity of the first output signal by adjusting at least one of the first capacitor and the second capacitor;
when the power of the input signal is greater than or equal to a preset value, the power amplifier controls the linearity of the second output signal by adjusting at least one of the first capacitor and the second capacitor.
3. The power amplifier according to claim 1 or 2, wherein the bias voltages of the third power amplifier tube and the fourth power amplifier tube are uniformly provided or provided separately,
the bias voltages of the seventh power amplifier tube and the eighth power amplifier tube are uniformly provided or respectively provided.
4. A power amplifier according to any one of claims 1 to 3, wherein the first and second power amplifier tubes are co-sourced and the fifth and sixth power amplifier tubes are co-sourced.
5. The power amplifier of any of claims 1-4, further comprising a first feedback circuit having a first end coupled to the inputs of the first and second amplifiers and a second end coupled to the outputs of the first and second amplifiers, the first feedback circuit operable to adjust the amplification of the first and second amplifiers.
6. The power amplifier of any of claims 1 to 5, further comprising a second feedback circuit, a first end of the second feedback circuit being connected to the inputs of the third and fourth amplifiers, a second end of the second feedback circuit being connected to the outputs of the third and fourth amplifiers, the second feedback circuit being operable to adjust the amplification of the third and fourth amplifiers.
7. The power amplifier of any of claims 1 to 6, further comprising an output matching network connected to the output of the first amplifier, the output of the second amplifier, the output of the third amplifier, and the output of the fourth amplifier.
8. The power amplifier of any one of claims 1 to 7, further comprising a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor, wherein the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are configured to isolate direct current,
the third capacitor is positioned between the first power amplifier tube and the input end of the first amplifier,
the fourth capacitor is positioned between the second power amplifier tube and the input end of the second amplifier,
the fifth capacitor is positioned between the fifth power amplifier tube and the input end of the third amplifier,
the sixth capacitor is located between the sixth power amplifier tube and the input end of the fourth amplifier.
9. The power amplifier according to any one of claims 1 to 8, wherein at least one of the first inductance, the second inductance and the coupling coefficient K is adjustable.
10. A method of amplifying a signal, the method performed by a power amplifier, the power amplifier comprising a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, and a transformer, the method comprising:
when the power of an input signal is smaller than a preset value, amplifying the input signal through a first amplifier, a third amplifier, a fourth power amplifier tube and an eighth power amplifier tube to obtain a first output signal; or,
when the power of the input signal is larger than or equal to a preset value, amplifying the input signal through a second amplifier, a fourth amplifier, a third power amplifier tube and a seventh power amplifier tube to obtain a second output signal;
the first amplifier is connected with the second amplifier in parallel, the third amplifier is connected with the fourth amplifier in parallel, the first amplifier comprises a first power amplifier tube and a third power amplifier tube, the second amplifier comprises a second power amplifier tube and a fourth power amplifier tube, the third amplifier comprises a fifth power amplifier tube and a seventh power amplifier tube, the fourth amplifier comprises a sixth power amplifier tube and an eighth power amplifier tube, the first amplifier and the third amplifier are connected through a first inductor, the second amplifier and the fourth amplifier are connected through a second inductor, and the coupling coefficient of the first inductor and the second inductor is K, and K is larger than 0.
11. The method of claim 10, wherein the power amplifier further comprises a first capacitor and a second capacitor, a first end of the first capacitor being connected to the first inductor, a second end of the first capacitor being grounded, a first end of the second capacitor being connected to the second inductor, a second end of the second capacitor being grounded, the method further comprising:
when the power of the input signal is smaller than a preset value, controlling the linearity of the first output signal by adjusting at least one of the first capacitor and the second capacitor; or,
and when the power of the input signal is greater than or equal to a preset value, controlling the linearity of the second output signal by adjusting at least one of the first capacitor and the second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210331487.6A CN116938168A (en) | 2022-03-31 | 2022-03-31 | Power amplifier and method for amplifying signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210331487.6A CN116938168A (en) | 2022-03-31 | 2022-03-31 | Power amplifier and method for amplifying signal |
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| Publication Number | Publication Date |
|---|---|
| CN116938168A true CN116938168A (en) | 2023-10-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210331487.6A Pending CN116938168A (en) | 2022-03-31 | 2022-03-31 | Power amplifier and method for amplifying signal |
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| Country | Link |
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| CN (1) | CN116938168A (en) |
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2022
- 2022-03-31 CN CN202210331487.6A patent/CN116938168A/en active Pending
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