CN116938164A - GaN power amplifier power supply driving control circuit and equipment - Google Patents
GaN power amplifier power supply driving control circuit and equipment Download PDFInfo
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- CN116938164A CN116938164A CN202310732916.5A CN202310732916A CN116938164A CN 116938164 A CN116938164 A CN 116938164A CN 202310732916 A CN202310732916 A CN 202310732916A CN 116938164 A CN116938164 A CN 116938164A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
- H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application provides a GaN power amplifier power supply driving control circuit and equipment, comprising: the grid voltage driving circuit, the grid current return voltage stabilizing circuit, the grid voltage monitoring circuit, the positive and negative voltage power-on time sequence protection circuit and the drain voltage driving control circuit; the gate voltage driving circuit generates a gate driving voltage Vg required for driving the power amplifier; the grid current return voltage stabilizing circuit absorbs grid current return of the power amplifier; the grid voltage monitoring circuit outputs a grid driving voltage monitoring signal to the positive and negative voltage power-on time sequence protection circuit; the positive and negative voltage power-on time sequence protection circuit generates a protection level and outputs the protection level to the electric leakage driving control circuit; the drain voltage driving control circuit generates a pulse drain driving voltage Vd required for the power amplifier. Aiming at the phenomenon that grid voltage is pulled to deviate due to grid voltage return current of a GaN power amplifier, the application provides a scheme of combining a voltage stabilizing circuit with a downward deviation monitoring protection circuit, which is used for absorbing the return current, stabilizing the grid voltage of the GaN power amplifier and providing downward deviation monitoring protection for the grid voltage.
Description
Technical Field
The application relates to the technical field of power amplifier driving circuits, in particular to a GaN power amplifier power supply driving control circuit and equipment.
Background
The basic architecture of a conventional power amplifier power supply drive control circuit is shown in fig. 1, and includes: the grid voltage detection circuit comprises a grid voltage driving circuit unit, a grid voltage detection circuit unit, a positive and negative voltage power-on protection circuit unit and a drain voltage pulse modulation circuit unit. The circuit is a power supply drive control circuit which is common to the current mainstream radio frequency/microwave power amplifier, and can realize the functions of grid voltage and drain voltage drive, pulse/continuous wave work, positive and negative voltage power-on protection and the like of the power amplifier.
For a common drain voltage driving circuit of the current GaN power amplifier, which is realized by matching a bootstrap circuit with a grid voltage driver switch NMOS tube, as shown in FIG. 2, the drain voltage driving circuit comprises a grid driver N1, two N-type power MOS tubes (an upper tube Q1 and a lower tube Q2) for the drain voltage switch, and a bootstrap capacitor C boot Bootstrap diode D boot The bootstrap circuit current-limiting resistor R1, the charge-discharge current-limiting resistors R2 and R3 respectively connected with the high-end/low-end output of the grid driver and the grid of the corresponding N-type power MOS tube, the drain voltage input energy storage capacitor C0 and the capacitor C1 for decoupling and driving of the grid voltage driver working power supply.
When the grid voltage of the power amplifier can reversely discharge current, the current circuit can lead the grid voltage to be biased (or up or down), and when the upper bias exceeds a threshold value, the protection circuit can lead the protection circuit to start to turn off the drain voltage output; when the power amplifier is severely deflected downwards, the grid voltage driving circuit is destroyed due to no deflection protection, and the power amplifier is burnt out. When the GaN power amplifier works under video loading, the grid electrode can generate a detection effect, so that the grid voltage driving output voltage is pulled to bias (generally, when the grid electrode of the power tube returns to spit current, the grid voltage is pulled to bias downwards), and particularly when the radio frequency input power is overdriven, the grid voltage is pulled to bias instantly, so that the chain reaction of the grid voltage driving circuit and the power tube is burnt is caused. Even if the gate voltage of the pull bias is insufficient to cause the device to burn out, the pull bias has a great influence on the performance such as the output power, the stability and the like of the circuit and the long-term reliability.
The current circuit adopts a bootstrap circuit to match with a grid voltage driver to rapidly charge and discharge the grid electrode of the power MOS tube, so that the initial start of the GaN power amplifier and the power supply of the pulse/continuous wave working drain electrode can be realized. This circuit has two common drawbacks: the grid series resistance R2/R3 of the high-end/low-end output pins of the grid electrode of the power MOS tube and the grid electrode driver in the circuit can influence the charge-discharge time of grid charges of the power MOS tube, thereby influencing the ultra-fast pulse switch application of narrow pulse and high duty ratio; the bootstrap capacitor in the circuit needs a certain charge and discharge time, so that the application of a narrow pulse and high duty ratio ultrafast pulse switch and the starting of the circuit can be influenced; when the gate series resistance R2 is smaller, the gate of the NMOS transistor Q1 discharges rapidly (when Q2 is in a conductive state), which causes a "negative voltage" to be generated at the source of Q1 (caused by parasitic inductance of the discharge channel), resulting in a chain reaction such as latch-up failure of the gate voltage driver. The above drawbacks are more common especially when driving high-gate capacitance power MOS transistors required for high-voltage, high-current applications such as high-power GaN power amplifiers.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide a GaN power amplifier power supply driving control circuit and a GaN power amplifier power supply driving control device.
The application provides a GaN power amplifier power supply driving control circuit, which comprises: the grid voltage driving circuit, the grid current return voltage stabilizing circuit, the grid voltage monitoring circuit, the positive and negative voltage power-on time sequence protection circuit and the drain voltage driving control circuit;
the grid voltage driving circuit is electrically connected with the grid electrode of the power amplifier and generates grid electrode driving voltage Vg required by driving the power amplifier;
the grid current return voltage stabilizing circuit is electrically connected with the grid voltage driving circuit and absorbs grid return current of the power amplifier;
the grid voltage monitoring circuit is respectively and electrically connected with the grid voltage driving circuit and the positive and negative voltage power-on time sequence protection circuit, monitors the grid voltage of the grid electrode of the power amplifier output by the grid voltage driving circuit, and outputs a grid voltage monitoring signal Vg-BIT to the positive and negative voltage power-on time sequence protection circuit when the grid voltage exceeds a preset upper and lower threshold value;
the positive and negative voltage power-on time sequence protection circuit is electrically connected with the leakage voltage driving control circuit, and generates a protection level and outputs the protection level to the leakage voltage driving control circuit;
the drain voltage driving control circuit is electrically connected with the drain electrode of the power amplifier and generates pulse drain electrode driving voltage Vd required by the power amplifier.
Preferably, the gate voltage driving circuit includes a broadband low noise operational amplifier N1, a resistor R2, a resistor R3, an adjustable resistor RP1, a capacitor C1, and a capacitor C2;
the other end of the resistor R1 is connected with the grid power supply voltage VG, the other end of the resistor R1 is respectively connected with an adjustable resistor RP1 and an IN+1 port of the broadband low-noise operational amplifier N1, the other end of the adjustable resistor RP1 is grounded, two ends of the capacitor C1 are connected with the adjustable resistor RP1 IN parallel, two ends of the resistor R2 are respectively connected with an IN-1 port, an OUT1 port of the broadband low-noise operational amplifier N1 and one end of the resistor R3, a V-port of the broadband low-noise operational amplifier N1 is connected with the grid power supply voltage VG, a V+ port of the broadband low-noise operational amplifier N1 is grounded, the other end of the resistor R3 is connected with one end of the capacitor C2, the other end of the capacitor C2 is grounded, and the other end of the resistor R3 outputs the grid driving voltage VG.
Preferably, the grid current return voltage stabilizing circuit comprises a resistor R4 and a zener diode D1, wherein one end of the resistor R4 and the positive electrode of the zener diode D1 are connected with the output end of the grid driving voltage Vg, and the other end of the resistor R4 and the negative electrode of the zener diode D1 are grounded.
Preferably, the gate voltage monitoring circuit includes a negative pressure monitoring chip N1, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C3, and a capacitor C4;
the two ends of the resistor R4 are respectively connected with an ADJ1 port and a REF port of the negative pressure monitoring chip N1, the two ends of the resistor R5 are respectively connected with an ADJ1 port and an ADJ2 port of the negative pressure monitoring chip, one end of the resistor R6 is connected with an ADJ2 port of the negative pressure monitoring chip N1, the other end of the resistor R6 is respectively connected with one end of the capacitor C3 and an output end of gate driving voltage Vg of the gate voltage driving circuit, the other end of the capacitor C3 is grounded, one end of the capacitor C4 is connected with a TMR port of the negative pressure monitoring chip N1, the other end of the capacitor C4 is grounded, the VCC port of the negative pressure monitoring chip N1 is connected with +3.3V voltage, and the RST port of the negative pressure monitoring chip N1 is an output port of gate driving voltage monitoring signal Vg-BIT and is electrically connected to +3.3V voltage through the resistor R7.
Preferably, the positive and negative voltage power-on time sequence protection circuit comprises an and gate chip D1 and a resistor R8, wherein an INA port of the and gate chip D1 is connected with an output port of a gate driving voltage monitoring signal Vg-BIT, an INB port of the and gate chip N1 is connected with an external TTL signal, the INB port is grounded through the resistor R8, a VCC port of the and gate chip N1 is connected with +3.3v, and an OUT port of the and gate chip N1 outputs a protection level VD-ctr.
Preferably, the drain voltage driving control circuit includes: a gate driver N1, an NMOS transistor Q2, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a diode D2, a diode D3, a diode D4, and a diode D5;
the IN port of the gate driver N1 is connected to the output port of the protection level VD-ctr and is grounded through a resistor R10, the VDD port of the gate driver N1 is respectively connected to the positive electrode of a diode D3, one end of a capacitor C8 and the Vcc terminal, the other end of the capacitor C8 is grounded, the negative electrode of the diode D3 is respectively connected to the HB port of the gate driver N1, one end of a capacitor C9 and the negative electrode of a diode D2, the positive electrode of the diode D2 is connected to the external Vee terminal through a resistor R9, the other end of the capacitor C9 is connected to the HS terminal of the gate driver N1, the EN port of the gate driver N1 is connected to +3.3v through a resistor R11, the HO port of the gate driver N1 is respectively connected to one end of a resistor R12 and one end of a capacitor D4, the other end of a resistor R12 is respectively connected to the positive electrode of a diode D4, the gate of a MOS transistor Q1 and one end of a resistor R13, the other end of a resistor R13 is respectively connected to the HS port of the gate driver N1, the source of a transistor Q1 and the drain of a transistor Q2, the drain of the capacitor C1 and the other end of a capacitor C6 is connected to the drain terminal of a capacitor C7, and the other end of a capacitor C5 is connected to the drain terminal of a pulse of the capacitor C1 is connected to the other end of the capacitor C6;
the LO port of the gate driver N1 is respectively connected with the cathode of the diode D5 and one end of the resistor R14, the anode of the diode D5 is respectively connected with the other end of the resistor R14, one end of the resistor R15 and the gate of the MOS tube Q2, the other end of the resistor R15 is grounded, the source electrode of the MOS tube Q2 is grounded, the RDT port of the gate driver N1 is connected with one end of the resistor R16, and the VSS port of the gate driver N1 is grounded after being connected with the other end of the resistor R16.
Preferably, the gate driver N1 is LM5106.
Preferably, the negative pressure monitoring chip N1 is of the type LTC2909ITS8-3.3.
Preferably, the wideband low noise operational amplifier N1 is model AD8615.
The power supply driving control device for the GaN power amplifier comprises the power supply driving control circuit for the GaN power amplifier.
Compared with the prior art, the application has the following beneficial effects:
1. aiming at the phenomenon that grid voltage is pulled to deviate due to grid voltage return current of a GaN power amplifier, the application provides a scheme of combining a voltage stabilizing circuit with a downward deviation monitoring protection circuit, which is used for absorbing the return current, stabilizing the grid voltage of the GaN power amplifier and further providing the downward deviation monitoring protection for the grid voltage.
2. The application provides a backup bootstrap circuit and a power MOS tube grid acceleration circuit scheme aiming at a GaN power amplifier device, and realizes easy starting, narrow pulse and high duty ratio pulse operation.
3. The scheme provided by the application can be suitable for GaN power amplifiers with different frequency bands and different powers, is also suitable for other amplifiers, meets the working occasions such as continuous wave, long pulse width/narrow pulse, high repetition frequency/large duty ratio, overdrive and the like, and has the beneficial effects of ensuring the long-term working stability and reliability of products and the like by good protection functions.
Other advantages of the present application will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a power amplifier power supply driving control circuit in accordance with the prior art;
FIG. 2 is a schematic diagram of a drain voltage driving control circuit of a GaN power amplifier commonly used in the prior art;
FIG. 3 is a schematic diagram of a GaN power amplifier power driving control circuit architecture according to the present application;
FIG. 4 is a schematic diagram of the gate voltage driving circuit and gate return current voltage stabilization according to an embodiment of the present application;
FIG. 5 is a schematic diagram of the gate voltage monitoring circuit according to an embodiment of the application;
fig. 6 is a schematic diagram of a gate voltage & drain positive and negative voltage power-up timing protection circuit according to an embodiment of the present application.
FIG. 7 is a schematic diagram of a drain voltage driving control circuit of the GaN power amplifier according to an embodiment of the application;
reference numerals illustrate:
grid voltage driving circuit 4 of power amplifier 1
Grid voltage monitoring circuit 5 of positive and negative voltage power-on time sequence protection circuit 2
Grid current return voltage stabilizing circuit 6 of drain voltage driving control circuit 3
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
The application discloses a GaN power amplifier power supply driving control circuit, as shown in figure 3, comprising: the grid voltage driving circuit 4, the grid electrode return voltage stabilizing circuit, the grid voltage monitoring circuit 5, the positive and negative voltage power-on time sequence protection circuit 2 and the drain voltage driving control circuit 3.
The gate voltage driving circuit 4 is electrically connected to the gate of the power amplifier 1, and generates a gate driving voltage Vg required for driving the power amplifier 1. The grid current return voltage stabilizing circuit 6 is electrically connected with the grid voltage driving circuit 4, absorbs grid return current of the power amplifier 1 and stabilizes grid voltage of the GaN power amplifier device. The grid voltage monitoring circuit 5 is respectively and electrically connected with the grid voltage driving circuit 4 and the positive and negative voltage power-on time sequence protection circuit 2, the grid voltage monitoring circuit 4 monitors the grid voltage of the grid electrode of the power amplifier 1, and when the grid voltage exceeds a preset upper and lower threshold value, the grid voltage monitoring circuit 5 outputs a grid voltage monitoring signal Vg-BIT to the positive and negative voltage power-on time sequence protection circuit 2. The positive and negative voltage power-on time sequence protection circuit 2 is electrically connected with the drain voltage driving control circuit 3, and the positive and negative voltage power-on time sequence protection circuit 2 is controlled by an input control TTL and a gate driving voltage monitoring signal Vg-BIT to generate a protection level and output the protection level to the drain voltage driving control circuit. The drain voltage driving control circuit 3 is electrically connected to the drain of the power amplifier 1, and generates a pulse drain driving voltage Vd required by the power amplifier 1.
The constituent circuits are further described below.
Referring to fig. 4, the gate voltage driving circuit 4 includes a broadband low noise operational amplifier N1, a resistor R2, a resistor R3, an adjustable resistor RP1, a capacitor C1, and a capacitor C2.
The other end of the resistor R1 is connected with the grid power supply voltage VG, the other end of the resistor R1 is respectively connected with an adjustable resistor RP1 and an IN+1 port of the broadband low-noise operational amplifier N1, the other end of the adjustable resistor RP1 is grounded, two ends of the capacitor C1 are connected with the adjustable resistor RP1 IN parallel, two ends of the resistor R2 are respectively connected with an IN-1 port, an OUT1 port of the broadband low-noise operational amplifier N1 and one end of the resistor R3, a V-port of the broadband low-noise operational amplifier N1 is connected with the grid power supply voltage VG, a V+ port of the broadband low-noise operational amplifier N1 is grounded, the other end of the resistor R3 is connected with one end of the capacitor C2, the other end of the capacitor C2 is grounded, and the other end of the resistor R3 outputs the grid driving voltage VG.
The grid current return voltage stabilizing circuit 6 comprises a resistor R4 and a zener diode D1, wherein one end of the resistor R4 and the positive electrode of the zener diode D1 are connected with the output end of the grid driving voltage Vg, and the other end of the resistor R4 and the negative electrode of the zener diode D1 are grounded.
The model of the broadband low-noise operational amplifier N1 is AD8615.
The operating principle of the grid voltage driving circuit 4 and the grid current return voltage stabilizing circuit 6 is as follows: the input-5V realizes voltage division through the R1 and the adjustable resistor RP1, the working voltage of the broadband low-noise operational amplifier N1 is-5V, the driving current reaches 100mA, the grid driving voltage Vg is output in a radial-following mode, and the resistor R3 realizes grid voltage current limiting protection. The grid return voltage stabilizing circuit is realized by connecting R4 and a voltage stabilizing diode (a zener diode) in parallel to the ground and is as close to the grid output end of the power amplifier 1 as possible, the resistor R4 is used for realizing return current absorption (the internal resistances of the power amplifier and the operational amplifier are generally high resistance and are more than dozens of kΩ, the resistor R4 is generally in the order of tens to hundreds of ohms), and the voltage stabilizing diode D1 is used for stabilizing the grid voltage on the safe working voltage through zener breakdown when the grid voltage is insufficient for absorbing return current for continuous pulling bias.
Referring to fig. 5, the gate voltage monitoring circuit 5 includes a negative pressure monitoring chip N1, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C3, and a capacitor C4.
The two ends of the resistor R4 are respectively connected with an ADJ1 port and a REF port of the negative pressure monitoring chip N1, the two ends of the resistor R5 are respectively connected with an ADJ1 port and an ADJ2 port of the negative pressure monitoring chip, one end of the resistor R6 is connected with an ADJ2 port of the negative pressure monitoring chip N1, the other end of the resistor R6 is respectively connected with one end of the capacitor C3 and an output end of gate driving voltage Vg of the gate voltage driving circuit 4, the other end of the capacitor C3 is grounded, one end of the capacitor C4 is connected with a TMR port of the negative pressure monitoring chip N1, the other end of the capacitor C4 is grounded, the VCC port of the negative pressure monitoring chip N1 is connected with +3.3V voltage, and the RST port of the negative pressure monitoring chip N1 is an output port of gate driving voltage monitoring signal Vg-BIT and is electrically connected to +3V voltage through the resistor R7. The model of the negative pressure monitoring chip N1 is LTC2909ITS8-3.3.
The gate voltage monitoring circuit 5 works according to the following principle: the negative pressure monitoring chip N1 is an integrated circuit special for negative pressure monitoring, the upper and lower thresholds of the pull-bias protection threshold can be set by changing the resistance values of the resistor R4, the resistor R5 and the resistor R6, and the monitoring signal is output through the RST pin of the negative pressure monitoring chip N1 and is pulled up to be Vg-BIT level through +3.3V and is generally abnormal.
Referring to fig. 6, the positive and negative voltage power-on timing protection circuit 2 includes an and gate chip D1 and a resistor R8, wherein an INA port of the and gate chip D1 is connected to an output port of the gate driving voltage monitoring signal Vg-BIT, an INB port of the and gate chip N1 is connected to an external TTL signal, the INB port is grounded through the resistor R8, a VCC port of the and gate chip N1 is connected to +3.3v, and an OUT port of the and gate chip N1 outputs the protection level VD-ctr.
The working principle of the positive and negative voltage power-on time sequence protection circuit 2 is as follows: referring to fig. 6, the and gate chip D1 outputs a high level to drive the trigger terminal of the drain voltage driving control circuit 3 when only TTL and Vg-BIT are input. Wherein R8 is connected in parallel to ground to prevent false triggering caused by interference.
Referring to fig. 7, the drain voltage drive control circuit 3 includes: a gate driver N1, an NMOS transistor Q2, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a diode D2, a diode D3, a diode D4, and a diode D5;
the IN port of the gate driver N1 is connected to the output port of the protection level VD-ctr and is grounded through a resistor R10, the VDD port of the gate driver N1 is respectively connected to the positive electrode of the diode D3, one end of the capacitor C8 and the Vcc terminal, the other end of the capacitor C8 is grounded, the negative electrode of the diode D3 is respectively connected to the HB port of the gate driver N1, one end of the capacitor C9 and the negative electrode of the diode D2, the positive electrode of the diode D2 is connected to the external Vee terminal through a resistor R9, the other end of the capacitor C9 is connected to the HS terminal of the gate driver N1, the EN port of the gate driver N1 is connected to +3.3v through a resistor R11, the HO port of the gate driver N1 is respectively connected to one end of the resistor R12 and one end of the negative electrode of the diode D4, the other end of the resistor R12 is respectively connected to the positive electrode of the diode D4, the gate of the MOS transistor Q1 and one end of the resistor R13, the other end of the MOS transistor Q13 is respectively connected to the HS port of the gate driver N1, the source of the MOS transistor Q1 and one end of the drain of the capacitor C1 and one end of the capacitor C5 is connected to the drain of the capacitor C6 and the other end of the capacitor C5 is connected to the drain voltage of the capacitor C7.
The LO port of the gate driver N1 is respectively connected with the cathode of the diode D5 and one end of the resistor R14, the anode of the diode D5 is respectively connected with the other end of the resistor R14, one end of the resistor R15 and the gate of the MOS tube Q2, the other end of the resistor R15 is grounded, the source electrode of the MOS tube Q2 is grounded, the RDT port of the gate driver N1 is connected with one end of the resistor R16, and the VSS port of the gate driver N1 is grounded after being connected with the other end of the resistor R16.
The gate driver N1 is model LM5106.
The operating principle of the leakage voltage driving control circuit 3 is as follows: n-type power MOS transistors Q1 and Q2 are used for drain switch and capacitor C 6 Is a bootstrap capacitor and a diode D 3 For bootstrap diode, a fast recovery diode is generally adopted, a resistor R10 is a bootstrap circuit current-limiting resistor, a resistor R11 and a resistor R12 are charge-discharge current-limiting resistors, a capacitor C5 is a drain voltage input energy storage capacitor, and an external drain driving voltage VD is used for decoupling and driving a capacitor C6. Compared with FIG. 2, the present application adds a bootstrap diode D of the standby bootstrap circuit 2 The bootstrap circuit current-limiting resistor R9 and the power supply Vee are specially used for the bootstrap capacitor C boot Auxiliary charging; the charge-discharge current-limiting resistor R12/R14 of the grid electrode of the NMOS tube is respectively connected with a fast recovery diode D4/D5 in parallel, which is used for realizing the fast discharge of grid charges so as to realize the fast start of the power tube, and is respectively connected with a larger resistor R13/R15 (the resistance k omega level) to the source electrode of the NMOS tube (the upper tube is correspondingly connected with the VS end and the Vout end of the grid voltage driver, and the lower tube is grounded), so that the 'negative voltage' of the fast discharge is relieved, and the chain reaction such as locking failure of the grid voltage driver caused by the negative voltage is prevented. Further, the gate driver NThe RDT pin of 1 is grounded through a resistor R16, the EN pin is connected with +3.3V voltage through a serial connection R2, an external TTL modulation pulse is input through the IN pin and is connected to the ground IN parallel through a resistor R1, and the RDT pin is used for preventing false triggering.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.
Claims (10)
1. A GaN power amplifier power supply drive control circuit, comprising: the grid voltage driving circuit, the grid current return voltage stabilizing circuit, the grid voltage monitoring circuit, the positive and negative voltage power-on time sequence protection circuit and the drain voltage driving control circuit;
the grid voltage driving circuit is electrically connected with the grid electrode of the power amplifier and generates grid electrode driving voltage Vg required by driving the power amplifier;
the grid current return voltage stabilizing circuit is electrically connected with the grid voltage driving circuit and absorbs grid return current of the power amplifier;
the grid voltage monitoring circuit is respectively and electrically connected with the grid voltage driving circuit and the positive and negative voltage power-on time sequence protection circuit, monitors the grid voltage of the grid electrode of the power amplifier output by the grid voltage driving circuit, and outputs a grid voltage monitoring signal Vg-BIT to the positive and negative voltage power-on time sequence protection circuit when the grid voltage exceeds a preset upper and lower threshold value;
the positive and negative voltage power-on time sequence protection circuit is electrically connected with the leakage voltage driving control circuit, and generates a protection level and outputs the protection level to the leakage voltage driving control circuit;
the drain voltage driving control circuit is electrically connected with the drain electrode of the power amplifier and generates pulse drain electrode driving voltage Vd required by the power amplifier.
2. The GaN power amplifier power supply driving control circuit of claim 1, wherein the gate voltage driving circuit comprises a wideband low noise operational amplifier N1, a resistor R2, a resistor R3, an adjustable resistor RP1, a capacitor C1, and a capacitor C2;
the other end of the resistor R1 is connected with the grid power supply voltage VG, the other end of the resistor R1 is respectively connected with an adjustable resistor RP1 and an IN+1 port of the broadband low-noise operational amplifier N1, the other end of the adjustable resistor RP1 is grounded, two ends of the capacitor C1 are connected with the adjustable resistor RP1 IN parallel, two ends of the resistor R2 are respectively connected with an IN-1 port, an OUT1 port of the broadband low-noise operational amplifier N1 and one end of the resistor R3, a V-port of the broadband low-noise operational amplifier N1 is connected with the grid power supply voltage VG, a V+ port of the broadband low-noise operational amplifier N1 is grounded, the other end of the resistor R3 is connected with one end of the capacitor C2, the other end of the capacitor C2 is grounded, and the other end of the resistor R3 outputs the grid driving voltage VG.
3. The GaN power amplifier power supply driving control circuit according to claim 2, wherein the gate-current back-discharge voltage stabilizing circuit comprises a resistor R4 and a zener diode D1, one end of the resistor R4 and the positive electrode of the zener diode D1 are connected with the output end of the gate driving voltage Vg, and the other end of the resistor R4 and the negative electrode of the zener diode D1 are grounded.
4. The GaN power amplifier power supply driving control circuit of claim 1, wherein the gate voltage monitoring circuit comprises a negative pressure monitoring chip N1, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a capacitor C3, and a capacitor C4;
the two ends of the resistor R4 are respectively connected with an ADJ1 port and a REF port of the negative pressure monitoring chip N1, the two ends of the resistor R5 are respectively connected with an ADJ1 port and an ADJ2 port of the negative pressure monitoring chip, one end of the resistor R6 is connected with an ADJ2 port of the negative pressure monitoring chip N1, the other end of the resistor R6 is respectively connected with one end of the capacitor C3 and an output end of gate driving voltage Vg of the gate voltage driving circuit, the other end of the capacitor C3 is grounded, one end of the capacitor C4 is connected with a TMR port of the negative pressure monitoring chip N1, the other end of the capacitor C4 is grounded, the VCC port of the negative pressure monitoring chip N1 is connected with +3.3V voltage, and the RST port of the negative pressure monitoring chip N1 is an output port of gate driving voltage monitoring signal Vg-BIT and is electrically connected to +3.3V voltage through the resistor R7.
5. The GaN power amplifier power supply driving control circuit according to claim 1, wherein the positive and negative voltage power-on timing protection circuit comprises an and gate chip D1 and a resistor R8, an INA port of the and gate chip D1 is connected to an output port of the gate driving voltage monitoring signal Vg-BIT, an INB port of the and gate chip N1 is connected to an external TTL signal, and the INB port is grounded through the resistor R8, a VCC port of the and gate chip N1 is connected to +3.3v, and an OUT port of the and gate chip N1 outputs a protection level VD-ctr.
6. The GaN power amplifier power supply drive control circuit of claim 1, wherein the drain voltage drive control circuit comprises: a gate driver N1, an NMOS transistor Q2, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a diode D2, a diode D3, a diode D4, and a diode D5;
the IN port of the gate driver N1 is connected to the output port of the protection level VD-ctr and is grounded through a resistor R10, the VDD port of the gate driver N1 is respectively connected to the positive electrode of a diode D3, one end of a capacitor C8 and the Vcc terminal, the other end of the capacitor C8 is grounded, the negative electrode of the diode D3 is respectively connected to the HB port of the gate driver N1, one end of a capacitor C9 and the negative electrode of a diode D2, the positive electrode of the diode D2 is connected to the external Vee terminal through a resistor R9, the other end of the capacitor C9 is connected to the HS terminal of the gate driver N1, the EN port of the gate driver N1 is connected to +3.3v through a resistor R11, the HO port of the gate driver N1 is respectively connected to one end of a resistor R12 and one end of a capacitor D4, the other end of a resistor R12 is respectively connected to the positive electrode of a diode D4, the gate of a MOS transistor Q1 and one end of a resistor R13, the other end of a resistor R13 is respectively connected to the HS port of the gate driver N1, the source of a transistor Q1 and the drain of a transistor Q2, the drain of the capacitor C1 and the other end of a capacitor C6 is connected to the drain terminal of a capacitor C7, and the other end of a capacitor C5 is connected to the drain terminal of a pulse of the capacitor C1 is connected to the other end of the capacitor C6;
the LO port of the gate driver N1 is respectively connected with the cathode of the diode D5 and one end of the resistor R14, the anode of the diode D5 is respectively connected with the other end of the resistor R14, one end of the resistor R15 and the gate of the MOS tube Q2, the other end of the resistor R15 is grounded, the source electrode of the MOS tube Q2 is grounded, the RDT port of the gate driver N1 is connected with one end of the resistor R16, and the VSS port of the gate driver N1 is grounded after being connected with the other end of the resistor R16.
7. The GaN power amplifier power supply driving control circuit of claim 6, wherein the gate driver N1 is model LM5106.
8. The GaN power amplifier power supply driving control circuit of claim 4, wherein said negative pressure monitor chip N1 is model LTC2909ITS8-3.3.
9. The GaN power amplifier power supply driving control circuit of claim 1, wherein the wideband low noise operational amplifier N1 model is AD8615.
10. A GaN power amplifier power supply drive control apparatus comprising the GaN power amplifier power supply drive control circuit of any one of claims 1-9.
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| CN202310732916.5A CN116938164A (en) | 2023-06-19 | 2023-06-19 | GaN power amplifier power supply driving control circuit and equipment |
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| CN202310732916.5A CN116938164A (en) | 2023-06-19 | 2023-06-19 | GaN power amplifier power supply driving control circuit and equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119787999A (en) * | 2025-03-03 | 2025-04-08 | 合肥芯谷微电子股份有限公司 | Broadband harmonic suppression power amplifier with resistive filter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119787999A (en) * | 2025-03-03 | 2025-04-08 | 合肥芯谷微电子股份有限公司 | Broadband harmonic suppression power amplifier with resistive filter |
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