CN1169217C - Electrostatic Discharge Protection Device - Google Patents
Electrostatic Discharge Protection Device Download PDFInfo
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- CN1169217C CN1169217C CNB011095296A CN01109529A CN1169217C CN 1169217 C CN1169217 C CN 1169217C CN B011095296 A CNB011095296 A CN B011095296A CN 01109529 A CN01109529 A CN 01109529A CN 1169217 C CN1169217 C CN 1169217C
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- 229910021332 silicide Inorganic materials 0.000 claims abstract description 48
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims description 69
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 5
- 230000003068 static effect Effects 0.000 description 47
- 230000001681 protective effect Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 230000009429 distress Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000004484 Briquette Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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Abstract
An electrostatic discharge protection device comprises a first N-well region, a second N-well region, a first N + doped region, a first P + doped region, a second N + doped region, a third N + doped region, a fourth N + doped region, a second P + doped region and a gate region. The metal silicide layer is deposited on the first N + doped region, the second N + doped region, the third N + doped region, the fourth N + doped region, the first P + doped region and the second P + doped region. The first N + doping region, the fourth N + doping region and the first P + doping region are coupled to a bonding pad of the IC chip, the second N + doping region and the gate region are coupled to a ground terminal, and the second P + doping region is coupled to the ground terminal.
Description
Technical field
The present invention relates to a kind of semiconductor device of IC chip.Be particularly related to a kind of static discharge (Electrostatic Discharge that has; ESD) semiconductor device of protective circuit; above-mentioned ESD protection circuit and IC chip combine, and it can prevent the discharge effect of output, input or I/O pin at semiconductor circuit.
Background technology
The static discharge effect is well known phenomenon, and wherein the unexpected discharge of electrostatic charge can cause very the high electrostatic discharge electric current external pins of flowing through, as an input, an output or an I/O pin of IC chip.Static discharge often be since input, output or the I/O pin of IC chip contact with another object (for example: human body or manufacturing machine) with electrostatic charge produce.
Be very of short duration (usually big approximate number 10-9 second) discharge time of static discharge current, so static discharge current can be greatly to 10 amperes.As a result, high static discharge current like this will damage the many devices on the IC chip.When the semiconducter IC chip continue to dwindle and in be built in device on the IC chip for any reaction when more and more responsive, the static discharge effect can become an important factors concerning the reliability of all IC chips.The static discharge phenomenon is to the existing quite complete research of the infringement of semiconducter IC chip.Split, contact blowing of infringement, leakage current, silicon base infringement and/or line etc. by what the plant failure that static discharge caused can comprise grid oxic horizon.When semiconductor technology when deep-sub-micrometer develops, the IC chip becomes and is very easy to be subjected to the high electric current of static discharge effect and the influence that high electric field is imitated density.Therefore, in the end between decade, develop and the effect that much is used for resisting damage of electrostatic discharge.For example: can on each input, output or the I/O pin of chip, provide an ESD protection circuit,, use the fault that prevents chip functions with the big electric current of avoiding being caused by the static discharge effect.Other conventional art also can comprise: drain electrode doping and/or the drain diffusion degree of dynamic gate coupling device to the CMOS device of IC chip or increase chip are provided.
For electrostatic discharge protective equipment, (Silicon-Controlled Rectifier SCR) makes the ESD protection circuit that is used for as the semiconducter IC chip to thyristor widely.At thyristor after static discharge current triggers, thyristor is during static discharge, become low-impedance mode from high impedance mode, and allow the electrostatic induced current thyristor of flowing through simultaneously, be not coupled to the device that is vulnerable to damage of chip exterior pin and can not flow through.As a result, thyristor can prevent the infringement that the static discharge effect is caused the I/O functional device.According to some research, (for example: N with respect to other electrostatic discharge protective circuit
+/ P-well region, base are received two matrixes, NMOS device), thyristor provide higher electrostatic discharge (ESD) protection ability (that is, higher V/ μ m
2Value).As comparing with other ESD protection circuit, thyristor also has the low advantage of keeping voltage, and it can reduce thermal effect during static discharge and power scatters and disappears.Because most of by static discharge effect cause to the infringement of I/O functional device be and hot relevant fault, so for the deep-sub-micrometer The Application of Technology, thyristor low kept the advantage that voltage provides better electrostatic protection especially.
Basically, thyristor is by CMOS or two-carrier technology, a parasitic-PNP transistor and a parasitic NPN transistor be connected and form.Figure 1A system demonstrates the generalized section of a typical CMOS thyristor.Figure 1B system demonstrates the equivalent circuit diagram of the thyristor of Figure 1A.Shown in Figure 1A, thyristor is essentially the device with two ends, and wherein the collection utmost point of the emitter-base bandgap grading of PNP and NPN links together, and with as anode (Anode) A, and the collection utmost point of the emitter-base bandgap grading of NPN and PNP links together, with as negative electrode (Cathode) K.In addition, one first resistance R
N-wellBe to be connected between the collection utmost point and negative electrode K of NPN, and one second resistance R
SubBe to be connected between the collection utmost point and anode A of PNP.First resistance R
N-wellWith second resistance R
SubBe respectively the N in the CMOS technology
-Well region resistance and a substrate resistance (shown in Figure 1A).
Though thyristor has unique advantage, before the use thyristor provides the protection of IC chip effective electrostatic discharge, still there is the problem that need overcome to exist.Particularly thyristor generally has the breakdown voltage (BV than typical N mos device
1) or typical CMOS technology in N
-Breakdown voltage between well region and P-substrate is wanted high trigger voltage.As a result, if during IC chip generation static discharge, can be because the N of NMOS device or CMOS device
-Well region is done sth. in advance crash reason before thyristor triggers, make the part I/O functional device sustain damage of IC chip.As head it off not, then will make the thyristor protective device is completely written-off to the deep-sub-micrometer technology.
Traditional settling mode at the problems referred to above provides an external pins (as shown in Figure 2) of mixing NMOS-SCR protective device 150 to IC chips.In Fig. 2, an extra N
+Zone 160 is P that are formed at typical CMOS-SCR device
+District 162 and one N
+Between the negative electrode 158.Above-mentioned extra N
+District 160 is to be connected to a N
-P in the well region 152
+ District 156 and one N
+ District 154, and be connected to a joint sheet (PAD) 166, wherein above-mentioned joint sheet 166 is an input, an output or I/O pins that are connected to the IC chip.Above-mentioned extra N
+Zone 160 major function is to reduce the trigger voltage of SCR device, and then the trigger voltage that makes the SCR device is near NMOS or N
-The breakdown voltage BV1 of well region.The I-V curve that Fig. 3 system demonstrates nmos pass transistor, independent SCR and mixes the NMOS-SCR device.As shown in Figure 3, mix NMOS-SCR and have the almost identical voltage of keeping with independent SCR, the two keep voltage ratio NMOS device to keep voltage low.In addition, the breakdown voltage (BV of NMOS-SCR
3) than independent SCR more near the breakdown voltage BV of NMOS
1Therefore, before any infringement that the NMOS device collapse corresponding to an external pins is caused, can trigger the SCR of NMOS-SCR, in order to the protection of static discharge to be provided.
During negative stress (Negative Stress) pattern of static discharge, joint sheet 166 is to be coupled to a negative ESD voltage.Apply the P of forward bias to NMOS
-Substrate 1 and drain electrode end (the initiate N of NMOS-SCR
+District 160), to allow the P of static discharge current via NMOS
-Substrate 1 flows to drain electrode end 160.Therefore, P
-Substrate 1 and drain electrode end 160 provide the discharge circuit of static discharge current.
During direct stress (Positive Stress) pattern of static discharge (that is joint sheet 166 is to be coupled to a positive ESD voltage), static discharge current will flow into P via the drain electrode end 160 of NMOS
-Substrate 1 (path P).Because the breakdown voltage BV of NMOS
1Trigger voltage BV than SCR
3Low, so most static discharge current will flow into P via the drain electrode end of NMOS
-Substrate 1, and the P of the SCR that can not flow through
+District 156.Then, electrostatic induced current can become a substrate current, is as the trigger current that triggers SCR.But in case trigger SCR, the anode tap A of SCR and the voltage between cathode terminal K will drop to keeps voltage.As mentioned above, SCR keep voltage ratio NMOS device to keep voltage low.Therefore, in case trigger SCR, most of ESD electric current SCR that will flow through, and can the not flow through NMOS of NMOS-SCR150 or the NMOS device of external pins.Therefore, as a foreign current rip into device, it is used for ON/OFF SCR with the NMOS that mixes NMOS-SCR device 150.As a result, in the static discharge effect, NMOS-SCR150 will provide the protection of the NMOS or the CMOS device of the external pins that is coupled to joint sheet 166.
If need not add the additional metal silicide layer to the semiconductor device of IC chip, then above-mentioned conventional hybrid formula NMOS-SCR can provide suitable electrostatic discharge (ESD) protection at the external pins of IC chip.In case on semiconductor device, increase by a metal silicide layer, then can reduce the ability of the electrostatic discharge (ESD) protection that conventional hybrid formula NMOS-SCR technology provided.The general speed of using metal silicide layer to improve the IC chip, with the unilateral resistance that reduces contact point with and/or the contact that improves the IC chip integrate.Though metal silicide provides many advantages, metal silicide layer has negative impact to the electrostatic discharge (ESD) protection ability of IC chip.
Fig. 4 demonstrates the conventional hybrid formula NMOS-SCR device 180 similar to Fig. 2, but it has the metal silicide layer 194 on the different area that is deposited on device.Metal silicide has the sheet resistor value lower than silicon, and wherein above-mentioned silicon constitutes the deposition region of substrate and device.In the NS of static discharge pattern, more need not consider the electrostatic discharge (ESD) protection ability that this deposits the NMOS-SCR device 180 of metal silicide layer.This is that static discharge current is the N from the NMOS device because during the NS pattern
+Drain electrode 190 P that surrounded
- Substrate 1 is so the current density in the drain region 190 of NMOS device can have uniform distribution.But in the static discharge of PS pattern, this NMOS-SCR device 180 that deposits metal silicide layer can suffer from big problem.
During the static discharge of PS pattern, flow to the N of NMOS from joint sheet 196 when static discharge current
+During drain region 190, most static discharge current will flow along disilicide layer 194, that is along the surf zone of drain region, and flow towards the channel region 198 of NMOS, rather than via N
+Drain region 190 and flow to P
-In the substrate, so trigger the SCR protective device.Fig. 4 B system demonstrates the amplifier section of the NMOS among Fig. 4 A, conveniently to be described in the current concentration effect in the PS pattern.Shown in Fig. 4 B, most static discharge current flow into channel region 198 via metal silicide layer 194, and the static discharge current that has only fraction is via N
+Drain region 190 and flow into P
-Substrate 1.Therefore, this NMOS that deposits metal silicide provides the required electric current of injecting to trigger SCR no longer for the protection of static discharge.Moreover, because static discharge current is the surface area that concentrates near the drain region 190 of the channel region 198 of NMOS device, so this NMOS that deposits metal silicide itself also is subjected to the infringement of static discharge easily.
Traditional solution at the problems referred to above is to provide a silico briquette (for example: an oxidation block), flow towards NMOS channel region 198 along metal silicide layer 194 to prevent static discharge current on the two ends of NMOS channel region.But the method has needs to increase the shortcoming that an additional technical steps is made the IC chip, and this additional step needs an extra face shield technology, therefore can increase the manufacturing cost of semiconducter IC chip.Other electrostatic discharge protection method that solves conventional hybrid formula NMOS-SCR device also has the problem that needs to increase one or more additional technical steps and/or increase manufacturing cost.
Summary of the invention
One of the object of the invention is: improvement one deposits the electrostatic discharge (ESD) protection ability of the SCR and/or the hybrid N MOS-SCR of silicon layer.That is, improve the electrostatic discharge (ESD) protection ability of SCR and/or NMOS-SCR, and need not increase any additional technical steps.Therefore manufacturing cost can be saved, and the electrostatic discharge (ESD) protection ability of electrostatic discharge protective equipment can be improved simultaneously.Can reach above-mentioned purpose according to improved device of the present invention.
Therefore, the invention provides a device, it comprises a NMOS-SCR device, and above-mentioned NMOS-SCR device has a new N
+The district, it is formed at P
-In the substrate and a new N
-Well region.Above-mentioned new N
+Draining to small part of district and nmos pass transistor is positioned at above-mentioned new N
-In the well region.Moreover joint sheet PAD is not couple to the drain region of nmos pass transistor.Replace, joint sheet is to be couple to above-mentioned new N+ district.Therefore, in the static discharge of PS pattern, most of electric current can not flow into the channel region of nmos pass transistor, but from above-mentioned new N
+The district is via new N
-Well region and flow into P
-Substrate is so that can trigger SCR at electrostatic discharge (ESD) protection.
Addressing additional features and advantage on of the present invention can be by appended graphic detailed description the in detail, and will become becomes apparent.In graphic and explanation, numerical chracter is represented the different structure of the present invention, the identical identical structure of numerical chracter representative.
For above and other objects of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and conjunction with figs., be described in detail below:
Description of drawings
Figure 1A one has the simplification tradition SCR device of PNPN structure;
Figure 1B is the traditional SCR manipulated or operated apparatus among Figure 1A;
Fig. 2 is the generalized section of a traditional NMOS-SCR device;
Fig. 3 is that the typical case of traditional SCR, traditional NMOS-SCR and NMOS device is collapsed curve;
Fig. 4 A demonstrates a traditional NMOS-SCR device with metal silicide layer, and above-mentioned metal silicide layer is the surface that is deposited on the different area of NMOS-SCR device;
Fig. 4 B is that the part of the NMOS device among Fig. 4 A is amplified icon;
Fig. 5 is according to a modified form NMOS-SCR device of the present invention;
Fig. 6 is that the part of the present invention among the 5th figure is amplified graphic;
Fig. 7 is an alternate embodiment of the present invention;
Fig. 8 is another alternate embodiment of the present invention.
Wherein, parts and Reference numeral are respectively:
1-P
-Substrate;
10-modified form NMOS-SCR electrostatic discharge protective equipment;
20-the one N
-Well region;
22-the one N
+ District 22;
24-the one P
+ District 24;
The 26-metal silicide layer;
30-the 2nd N
-Well region;
32-the 2nd N
+The district;
34-the 3rd N
+The district;
36-the 4th N
+The district;
38-oxidation sept;
The 40-polysilicon gate;
46-the 2nd P
+The district;
The 48-joint sheet;
The raceway groove of 50-NMOS;
52-self-aligned silicide grids;
60,100-modified form NMOS-FLVSCR device;
70-the one N
-Well region;
72-the 2nd N
-Well region;
74-the one P
+The district;
76-the one N
+The district;
78-the 2nd N+ district;
80-the 3rd N+ district;
82-the 2nd P
+The district;
The 84-metal silicide layer;
90-self-aligned silicide grids;
102-the one N
-Well region;
104-the 2nd N
-Well region;
106-the one P
+The district;
108-the one N district;
110-the 2nd N
+The district;
112-the 3rd N
+The district;
114-the 2nd P
+The district;
116-the 3rd P
+The district;
The 120-metal silicide layer; And
122-self-aligned silicide grids.
Embodiment
Embodiment one
Fig. 5 demonstrates the modified form NMOS-SCR electrostatic discharge protective equipment 10 according to a preferred embodiment of the present invention.In Fig. 5, electrostatic discharge protective equipment 10 comprises a P
-Substrate 1, it has one the one N
-Well region 20 and one the 2nd N
-Well region 30, above-mentioned both at P
-Be separated from one another in the substrate 1.One the one N
+District 22 and 1 the one P
+District 24 is respectively to be formed at a N
-In the well region 20.One metal silicide layer 26 covers a N
+District the 22 and the one P
+The surface (as shown in Figure 5) in district 24.
One the 2nd N
+District 32 is to be formed at P
-In the substrate 1, and with a N
-Well region 20 is separated from one another.One the 3rd N
+District 34 and 1 the 4th N
+District 36 to small part is formed at P
-Substrate 1 and the 2nd N
-In the well region 30 (as shown in Figure 5).The 2nd N
+District the 32 and the 3rd N
+District 34 is respectively as the source area and the drain region of NMOS device.Similarly, source area 32 is covered by above-mentioned metal silicide layer 26 with drain region 34.Moreover a self-aligned silicide grids 52 is the P that are positioned at raceway groove 50 tops of NMOS
-Substrate 1 surface, and part covers the source area 32 and drain region 34 of NMOS device.Have oxidation sept 38 at the two ends of self-aligned silicide grids 52, it is used for covering the part source area 32 and drain region 34 of NMOS.Self-aligned silicide grids 52 comprises that more a polysilicon gate 40 and is formed at the metal silicide layer 42 on the polysilicon gate 40.Metal silicide layer 26 also covers the 4th N
+District 36.At the 4th N
+Metal silicide layer 26 in the district 36 is to be couple to a N
+District the 22 and the one P
+The metal silicide layer 26 and the joint sheet (PAD) 48 in district 24.Above-mentioned joint sheet 48 is an input, an output or I/O pins that are connected to the IC chip.
One the 2nd P
+District 46 is to be formed at P
-In the substrate 1, it is positioned at the 4th N
+The next door in district 36, and be positioned at the 2nd N
+The opposition side in district 32.The 2nd P+ district 46 is the negative electrodes as SCR.Gold layer silicide layer 26 also is deposited on the 2nd P
+In the district 46.With the 2nd P
+District the 46, the 2nd N
+District's 32 (source electrodes of NMOS) and self-aligned silicide grids 52 ground connection.
Fig. 6 demonstrates the part of Fig. 5 and amplifies graphic.During the static discharge of PS pattern, static discharge current flows to the 4th N from joint sheet 48
+ District 36 flows into the 2nd N then
- Well region 30 or P
-Substrate 1 (as shown in Figure 6).The 4th N district 36 and the 3rd N
+District 34 is by the 2nd N
-Well region 30 is isolated.Therefore, in case leave the 4th N
+District 36, most of electrostatic induced current will be towards the 2nd N
-Dissipating in the bottom of well region 30, and can not concentrate on the 2nd N
-The surface of well region 30.At last, the partial electrostatic electric current will arrive the N of NMOS
+Drain region 34, but most of static discharge stream will arrive P
-Substrate 1, with provide trigger SCR required inject electric current.As a result, can solve the problem of relatively poor electrostatic discharge performance that tradition has the NMOS-SCR device of metal silicide layer according to Improvement type NMOS-SCR of the present invention.
Therefore, compare with the technology that solves the relatively poor electrostatic discharge performance that metal silicide causes, the invention provides a unique solution, and need not increase the required additional technical steps of conventional electrostatic discharge protector with tradition.The 2nd N
-Well region 30 can with a N
-Well region 20 is formed in the one first identical processing step.The 4th N
+District 36 can with first, second and the 3rd N
+District 22,32,34 is formed in the one second identical processing step.As a result, the present invention only needs to revise a little the face shield that uses in first and second processing step.Compare with the electrostatic discharge protective equipment that deposits metal silicide that solves relatively poor electrostatic discharge performance problem with tradition, the present invention does not need extra face shield step, and can fall the cost of the electrostatic discharge protective equipment of this manufacturing modified form.
Embodiment two:
Idea of the present invention also can be applicable in the NMOS-FLVSCR device.Fig. 7 demonstrates according to a kind of modified form NMOS-FLVSCR device 60 of the present invention.In Fig. 7, at a P
-Form one the one N separated from one another in the substrate 1
- Well region 70 and one the 2nd N
-Well region 72.One the one P
+District 74 is formed at a N
-In the well region 70, and one the one N
+District 76 is formed at a N
-The P on well region next door
-In the substrate 1.One the 2nd N
+District 78 and 1 the 3rd N
+District 80 is formed at a N to small part respectively
+Distinguish 76 next doors and, a N
-The P substrate 1 of the opposition side of well region 70 and the 2nd N
-In the well region 72 (as shown in Figure 7).At the 3rd N
+District 80 other and the 2nd N
+The opposition side in district 78 forms one the 2nd P
+District 82.One metal silicide layer 84 covers first, second P
+District 74,82 and first, second, third N
+District 76,78,80.First and second N
+The source electrode and the drain electrode of NMOS device regarded in district 76,78 respectively.
At first and second N
+District 76,78 and P
-Substrate 1 top forms a self-aligned silicide grids 90.With the 2nd P
+District the 82, the one N
+District 76, self-aligned silicide grids 90 ground connection.The one P
+District the 74 and the 3rd N
+District 80 is an input, an output or I/O joint sheets that are couple to the IC chip.
According to the present invention, modified form NMOS-FLVSCR device 60 is similar to modified form NMOS-SCR device 10.In the static discharge of PS pattern, most of static discharge current flows into the 3rd N
+District 80, and via the 2nd N
-Well region 72 and towards P
-Substrate 1 is flowed.Therefore, in the static discharge of PS pattern, the required trigger current of SCR can be via the 2nd N
-Well region 72 and the 3rd N
+Distinguish 80, and the NMOS device and the required protection of external pins of IC chip are provided.
Moreover, the 2nd N
-A well region 72 and a N
-Well region 70 is formed at one first identical processing step; And the 3rd N
+District 80 and first and second N
+District 76,78 is formed at one second identical processing step.When making the IC chip, need not extra face shield step according to the present invention.Therefore, compare with conventional art, the present invention can reduce manufacturing cost.
In another alternate embodiment, idea of the present invention also can be applicable in the NMOS-FLVSCR device of one second kenel.Fig. 8 demonstrates according to a kind of second modified form NMOS-FLVSCR device 100 of the present invention.In Fig. 8, one the one N
-Well region 102 and one the 2nd N
-Well region 104 is to be formed at a P
-In the substrate 1, and separated from one another.One the one P
+District 106 is to be formed at a N
-In the well region 102, and one the one N district 108 is formed at P
-In the substrate 1, and be positioned at a N
-Well region 102 is other.One the 2nd N
+District 110 is formed at a N
-The opposition side of well region 102, and be positioned at P to small part
-In the substrate 1 and part be positioned at the 2nd N
-In the well region 104.Simultaneously, above-mentioned the 2nd N
+District 110 is positioned at a N
+District 108 is other, and with a N
+Distinguished for 108 (as shown in Figure 8) separated from one another.One the 3rd N
+District 112 is to be formed at the 2nd N
-In the well region 104, and with the 2nd N
+District 110 separates.One the 2nd P
+District 114 is formed at the 2nd N
+The 2nd N on the opposition side in district 110
-Well region 104 is other.In addition, one the 3rd P
+District 116 is to be formed at a N
+N on the opposition side in district 108
-Well region 102 is other.One metal silicide layer 120 covers first, second, third P
+District 106,114,116 and first, second, third N
+District 108,110,112.First and second N
+The source area and the drain region of NMOS device regarded in district 108,110 respectively.
One self-aligned silicide grids 122 is to be formed at P
-First and second N of substrate 1 top
+Between district 108,110.With the 2nd P
+District the 114, the one N
+District 108 and self-aligned silicide grids 122 ground connection.The one P
+District the 106 and the 3rd N
+District 112 is an input, an output one I/O joint sheets that are couple to the IC chip.The 3rd P
+District 116 is the V that are couple to the IC chip
SsNode.The functional similarity of the second modified form NMOS-FLVSCR device 100 is in foundation modified form NMOS-FLVSCR device 10 of the present invention.In the static discharge of PS pattern, most of static discharge current flows into the 3rd N
+District 112, and via the 2nd N
-Well region 104 and towards P
-Substrate 1 is flowed.Therefore, in the static discharge of PS pattern, the required trigger current of SCR is via the 2nd N
-Well region 104 and the 3rd N district 112 are with NMOS device and the required protection of external pins that the IC chip is provided.
Moreover, the 2nd N
-A well region 104 and a N
-Well region 102 is to be formed at one first identical processing step, and the 3rd N
+District 112 and first, second N
+District the 108, the 110th is formed at one second identical processing step.In addition, the 3rd P
+District 116 and first, second P
+District the 106, the 114th is formed at one the 3rd identical processing step.Manufacturing according to semiconducter IC chip of the present invention does not need extra face shield step.Therefore, compare, can reduce the manufacturing cost of IC chip according to the present invention with conventional art.
According to top described, can recognize: though specific embodiment of the present invention has been described out, knowing this operator can do different improvement in not breaking away from spirit of the present invention and/or scope.Idea particularly of the present invention can be used to assist to trigger any kenel SCR or NMOS-SCR device, and therefore preferable electrostatic discharge (ESD) protection performance is provided.According to different alternate embodiments, the 2nd N
-Well region also can part or the initiate N of whole encirclement
+The district.Moreover, use what processing step to form different doped regions in the present invention or well region unimportant.Therefore, in IC technology, know this operator and can use distinct methods to form above-mentioned district and well region.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011095296A CN1169217C (en) | 2001-03-30 | 2001-03-30 | Electrostatic Discharge Protection Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011095296A CN1169217C (en) | 2001-03-30 | 2001-03-30 | Electrostatic Discharge Protection Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1378277A CN1378277A (en) | 2002-11-06 |
| CN1169217C true CN1169217C (en) | 2004-09-29 |
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ID=4657976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011095296A Expired - Fee Related CN1169217C (en) | 2001-03-30 | 2001-03-30 | Electrostatic Discharge Protection Device |
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| Country | Link |
|---|---|
| CN (1) | CN1169217C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349291C (en) * | 2004-05-13 | 2007-11-14 | 威盛电子股份有限公司 | Electrostatic discharge protection circuit |
| CN102097431B (en) * | 2009-12-10 | 2012-10-03 | 新唐科技股份有限公司 | Chip and its electrostatic discharge protection components |
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2001
- 2001-03-30 CN CNB011095296A patent/CN1169217C/en not_active Expired - Fee Related
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