CN116828083A - Protocol signal transmission method, device, equipment and storage medium - Google Patents
Protocol signal transmission method, device, equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
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Abstract
The application provides a protocol signal transmission method, device, equipment and storage medium, and relates to the technical field of servers. The method comprises the following steps: the BMC on the host device sends at least one protocol signal to the first complex programmable logic device; the first complex programmable logic device transmits at least one protocol signal to the second complex programmable logic device through a low voltage differential signal line LVDS; the second complex programmable logic device determines a protocol type of each protocol signal and transmits each protocol signal to a slave device corresponding to the respective protocol type through a plurality of protocol interfaces. Since a plurality of protocol signals can be simultaneously transmitted through the low-voltage differential signal line LVDS, protocol signals of various protocol types can be transmitted through only a few interfaces, and therefore complexity of hardware layout is reduced.
Description
Technical Field
The present application relates to the field of server technologies, and in particular, to a method, an apparatus, a device, and a storage medium for transmitting a protocol signal.
Background
With the development of server technology, the types of data processed by the server are more and more diversified. Currently, in order to improve data processing efficiency, a host device and a plurality of slave devices are provided in a server, and diversified data is processed by the host device and the plurality of slave devices.
In the prior art, a plurality of interfaces are provided on a master device and a plurality of slave devices, and the interfaces are connected through cables to transmit data of various protocol types. Wherein one interface only transmits data of one protocol type.
However, the inventors found that the prior art has at least the following technical problems: when the types of protocols of data to be transmitted are more, the number of occupied interfaces is more, and therefore, a plurality of cables are needed to connect the interfaces, so that the layout of the server is more complex.
Disclosure of Invention
The application provides a protocol signal transmission method, a device, equipment and a storage medium, which can reduce the complexity of the layout of a server.
In a first aspect, the present application provides a transmission method of a protocol signal, applied to a protocol signal transmission system, where the protocol signal transmission system includes a first complex programmable logic device connected to a host device, a second complex programmable logic device connected to a plurality of slave devices, and a low voltage differential signal line LVDS for connecting the first complex programmable logic device and the second complex programmable logic device; the method comprises the following steps:
the BMC on the host device sends at least one protocol signal to the first complex programmable logic device;
the first complex programmable logic device transmits at least one protocol signal to the second complex programmable logic device through a low voltage differential signal line LVDS;
the second complex programmable logic device determines the protocol type of each protocol signal, and transmits each protocol signal to the slave device corresponding to the respective protocol type through a plurality of protocol interfaces.
In one possible design, the low voltage differential signal line LVDS includes a transmit clock signal line and a transmit data signal line; the protocol signal includes a first clock signal and a first data signal; accordingly, the first complex programmable logic device transmits at least one protocol signal to a second complex programmable logic device through a low voltage differential signal line LVDS, comprising: the first complex programmable logic device transmits the first clock signal in each protocol signal to the second complex programmable logic device through a transmission clock signal line, and transmits the first data signal in each protocol signal to the second complex programmable logic device through a transmission data signal line.
In one possible design, the protocol signal includes a data start flag, valid data, and a data end flag, wherein the valid data includes a plurality of byte bits, one byte bit range for each protocol type of protocol signal; accordingly, the second complex programmable logic device determines a protocol type of each protocol signal, and transmits each protocol signal to a slave device corresponding to the respective protocol type through a plurality of protocol interfaces, including: the second complex programmable logic device determines at least one byte bit of valid data in each protocol signal; determining a byte bit range to which the at least one byte bit belongs; determining the protocol type of each protocol signal according to the corresponding relation between the protocol type and the byte bit range; and transmitting each protocol signal to the slave device corresponding to the respective protocol interface through the protocol interface corresponding to the protocol type of each protocol signal.
In one possible design, the protocol interfaces include one or more of an I2C protocol interface, an SPI protocol interface, a JATG protocol interface, and a UART protocol interface, and the protocol types include one or more of an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal; correspondingly, the transmitting each protocol signal to the slave device connected with the protocol interface through the protocol interface corresponding to the protocol type of each protocol signal comprises the following steps: if the protocol type of the protocol signal is an I2C protocol signal, transmitting the protocol signal to a slave device connected with the I2C protocol interface through an I2C protocol interface corresponding to the I2C protocol signal; or if the protocol type of the protocol signal is an SPI protocol signal, transmitting the protocol signal to slave equipment connected with the SPI protocol interface through an SPI protocol interface corresponding to the SPI protocol signal; or if the protocol type of the protocol signal is a UART protocol signal, transmitting the protocol signal to a slave device connected with the UART protocol interface through a UART protocol interface corresponding to the UART protocol signal; or if the protocol type of the protocol signal is a JATG protocol signal, transmitting the protocol signal to a slave device connected with the JATG protocol interface through a JATG protocol interface corresponding to the JATG protocol signal.
In one possible design, the data start flag includes 16 byte bits, the data end flag includes 16 byte bits, and the valid data includes 64 byte bits.
In one possible design, the method further comprises: the slave device feeds back a response data signal to the second complex programmable logic device through a corresponding protocol interface; the second complex programmable logic device transmits the response data signal to the first complex programmable logic device through the low voltage differential signal line LVDS; the first complex programmable logic device sends the response data signal to a baseboard management controller BMC on the host device.
In one possible design, the low voltage differential signal line LVDS includes a receive clock signal line and a receive data signal line; the response data signal includes a second clock signal and a second data signal; accordingly, the second complex programmable logic device transmitting the response data signal to the first complex programmable logic device through the low voltage differential signal line LVDS includes: the second complex programmable logic device transmits a second clock signal in the response data signal to the first complex programmable logic device through the receiving clock signal line, and transmits a second data signal in the response data signal to the first complex programmable logic device through the receiving data signal line.
In a second aspect, the present application provides a transmission apparatus for a protocol signal, which is applied to a protocol signal transmission system, where the protocol signal transmission system includes a first complex programmable logic device connected to a host device, a second complex programmable logic device connected to a plurality of slave devices, and a low voltage differential signal line LVDS for connecting the first complex programmable logic device and the second complex programmable logic device; the device comprises: the sending module is used for sending at least one protocol signal to the first complex programmable logic device by the baseboard management controller BMC on the host equipment;
the transmission module is used for transmitting at least one protocol signal to the second complex programmable logic device through the low-voltage differential signal line LVDS by the first complex programmable logic device;
the determining module is used for determining the protocol type of each protocol signal by the second complex programmable logic device, and transmitting each protocol signal to the slave equipment corresponding to the respective protocol type through a plurality of protocol interfaces.
In a third aspect, the present application provides an electronic device comprising: a processor and a memory;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory, causing the processor to perform the transmission method of protocol signals as described above in the first aspect and in the various possible designs of the first aspect.
In a fourth aspect, the present application provides a computer storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the transmission method of protocol signals according to the first aspect and the various possible designs of the first aspect.
In a fifth aspect, the present application provides a computer program product comprising a computer program which, when executed by a processor, implements the transmission method of protocol signals according to the first aspect and the various possible designs of the first aspect.
The protocol signal transmission method, the device, the equipment and the storage medium are applied to a protocol signal transmission system, wherein the protocol signal transmission system comprises a first complex programmable logic device connected with a host device, a second complex programmable logic device connected with a plurality of slave devices and a low-voltage differential signal line LVDS used for connecting the first complex programmable logic device and the second complex programmable logic device. Because a plurality of protocol signals can be transmitted simultaneously through the low-voltage differential signal line LVDS, protocol signals of various protocol types can be transmitted through only a plurality of interfaces without arranging independent interfaces and cables for each protocol signal, and therefore the complexity of hardware layout is reduced.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is an application scenario schematic diagram of a transmission method of a protocol signal according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a transmission method of a protocol signal according to an embodiment of the present application;
fig. 3 is a schematic flow chart of a transmission method of a protocol signal according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a transmission device for protocol signals according to an embodiment of the present application;
fig. 5 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with related laws and regulations and standards, and provide corresponding operation entries for the user to select authorization or rejection.
With the development of server technology, the types of data processed by the server are more and more diversified. Currently, in order to improve data processing efficiency, a host device and a plurality of slave devices are provided in a server, and diversified data is processed by the host device and the plurality of slave devices.
In the prior art, a plurality of interfaces are provided on a master device and a plurality of slave devices, and the interfaces are connected through cables to transmit data of various protocol types. Wherein one interface only transmits data of one protocol type. However, when the protocol types of the data to be transmitted are more, the number of occupied interfaces is more, which requires a plurality of cables to connect the interfaces, resulting in a complex layout of the server. In addition, the existing transmission method requires more cables and has higher transmission cost.
Illustratively, a BMC (Baseboard Manager Controller, baseboard management controller) on a master device is connected to multiple slaves via an SMBUS (System Management Bus ). Whereas the SMBUS may only transmit protocol signals of one protocol type. Therefore, a large number of cables and connectors are required to transmit various types of protocol signals, resulting in an increase in hardware cost and complexity of hardware layout. The Master device may be represented by a Master device, and the slave device may be represented by a slave device. Therefore, how to reduce the number of interfaces, reduce the layout complexity and the transmission cost of the server is a technical problem to be solved.
In order to solve the above technical problems, the embodiments of the present application provide the following technical ideas: first, a baseboard management controller on a host device sends at least one protocol signal to a first complex programmable logic device; then, the first complex programmable logic device transmits at least one protocol signal to the second complex programmable logic device through the low voltage differential signal line; finally, the second complex programmable logic device determines the protocol type of each protocol signal, and transmits each protocol signal to the slave device corresponding to the respective protocol type through a plurality of protocol interfaces. Because a plurality of protocol signals can be transmitted simultaneously through the low-voltage differential signal line, protocol signals of various protocol types can be transmitted through only a plurality of interfaces without arranging independent interfaces and cables for each protocol signal, and therefore the complexity of hardware layout is reduced.
Fig. 1 is an application scenario schematic diagram of a transmission method of a protocol signal according to an embodiment of the present application. As shown in fig. 1, the protocol signal transmission system includes a first complex programmable logic device 102 connected to a master device 101, a second complex programmable logic device 104 connected to a plurality of slave devices 103, and an LVDS (Low-Voltage Differential Signaling, low voltage differential signaling line) 105 for connecting the first complex programmable logic device 102 and the second complex programmable logic device 104. Data transmission between the master device 101 and the plurality of slave devices 103 can be performed by a protocol signal transmission system. The step of specifically transmitting may include: the host device 101 transmits various types of protocol signals to the first complex programmable logic device 102, and then the first complex programmable logic device 102 transmits the various types of protocol signals to the second complex programmable logic device 104 through the low voltage differential signal line 105 and transmits the protocol signals to the slave device 103 through the second complex programmable logic device 104. Since a plurality of protocol signals can be simultaneously transmitted through the low-voltage differential signal line LVDS, protocol signals of various protocol types can be transmitted through only a few interfaces, and therefore complexity of hardware layout is reduced. The transmission method of the protocol signal proposed by the present application is described in detail below through detailed embodiments.
Fig. 2 is a schematic flow chart of a protocol signal transmission method according to an embodiment of the present application, where the embodiment is applied to a transmission system for transmitting protocol signals. The protocol signal transmission system comprises a first complex programmable logic device connected with the host device, a second complex programmable logic device connected with the plurality of slave devices and a low-voltage differential signal line used for connecting the first complex programmable logic device and the second complex programmable logic device. As shown in fig. 2, the method includes:
s201, a baseboard management controller BMC on a host device sends at least one protocol signal to a first complex programmable logic device.
In this step, the BMC is connected to the first complex programmable logic device, and the BMC and the first complex programmable logic device may transmit protocol signals. Wherein the protocol signal may be a low speed protocol signal. Optionally, the low speed protocol signal includes at least one of: I2C (Inter-Integrated Circuit, integrated circuit bus) protocol signals, JATG (Joint Test Action Group, joint test working group) protocol signals, SPI (Serial Peripheral Bus ) protocol signals, and UART (Universal Asynchronous Receiver Transmitter, universal asynchronous receiver/transmitter) protocol signals. Accordingly, the at least one protocol signal includes one or more of an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal.
Wherein, the first complex programmable logic device can be represented by IO-CPLD, which is a shorthand for Complex Programmable Logic Device.
S202, the first complex programmable logic device transmits at least one protocol signal to the second complex programmable logic device through a low voltage differential signal line LVDS.
Optionally, the low voltage differential signal line LVDS includes a transmit clock signal line and a transmit data signal line; the protocol signal includes a first clock signal and a first data signal; correspondingly, the method comprises the following steps: the first complex programmable logic device transmits the first clock signal in each protocol signal to the second complex programmable logic device through the transmission clock signal line, and transmits the first data signal in each protocol signal to the second complex programmable logic device through the transmission data signal line.
Wherein the transmit clock signal line may be represented by tx_clk and the transmit DATA signal line may be represented by tx_data. Wherein the first clock signal and the first data signal are protocol signals transmitted by the host device to the slave device. Wherein the second complex programmable logic device may be represented by MB-CPLD, abbreviated as Complex Programmable Logic Device.
It should be noted that, the transmission clock signal line and the transmission data signal line each occupy one interface, that is, only 2 interfaces are required for transmitting a plurality of protocol signals through the low voltage differential signal line LVDS. Wherein, the low voltage differential signal line LVDS bandwidth is above 100Mbps, and the system management bus SMBUS in the prior art is only 100Kbps. That is, the low voltage differential signal lines may accommodate more than 100 sets of SMBUS channels.
S203, the second complex programmable logic device determines the protocol type of each protocol signal, and transmits each protocol signal to the slave device corresponding to the respective protocol type through a plurality of protocol interfaces.
Optionally, the protocol signal includes a data start flag, valid data and a data end flag, wherein the valid data includes a plurality of byte bits, and each protocol type of protocol signal corresponds to a byte bit range; correspondingly, the method comprises the following steps: the second complex programmable logic device determines at least one byte bit of valid data in each protocol signal; determining a byte bit range to which at least one byte bit belongs; determining the protocol type of each protocol signal according to the corresponding relation between the protocol type and the byte bit range; and transmitting each protocol signal to the slave device corresponding to the respective protocol interface through the protocol interface corresponding to the protocol type of each protocol signal.
It should be noted that, the corresponding relationship between the protocol type and the byte bit range is stored in the server. In the present application, a byte bit range corresponding to each protocol type may be preset. For example, the protocol types include an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal. Presetting a byte bit range corresponding to each protocol type as follows: the byte bit range 0-5bit corresponds to the I2C protocol signal, the byte bit range 6-10bit corresponds to the JATG protocol signal, the byte bit range 10-15bit corresponds to the SPI protocol signal, and the byte bit range 16-20bit corresponds to the UART protocol signal.
Optionally, a protocol signal of a protocol type corresponds to a protocol interface and is transmitted to the slave device via the protocol interface. The slave device and the protocol interface are connected in advance, and the protocol signal can be directly transmitted through the protocol interface.
The number and type of protocol interfaces are not particularly limited in the present application, and may be set as needed. Optionally, the protocol interfaces include one or more of an I2C protocol interface, an SPI protocol interface, a JATG protocol interface, and a UART protocol interface. Optionally, the protocol type of the protocol signal includes one or more of an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal.
Correspondingly, transmitting each protocol signal to a slave device connected with the protocol interface through the protocol interface corresponding to the protocol type of each protocol signal, including: if the protocol type of the protocol signal is an I2C protocol signal, transmitting the protocol signal to a slave device connected with the I2C protocol interface through an I2C protocol interface corresponding to the I2C protocol signal; or if the protocol type of the protocol signal is SPI protocol signal, transmitting the protocol signal to the slave equipment connected with the SPI protocol interface through the SPI protocol interface corresponding to the SPI protocol signal; or if the protocol type of the protocol signal is UART protocol signal, transmitting the protocol signal to the slave device connected with the UART protocol interface through the UART protocol interface corresponding to the UART protocol signal; or if the protocol type of the protocol signal is a JATG protocol signal, transmitting the protocol signal to a slave device connected with the JATG protocol interface through the JATG protocol interface corresponding to the JATG protocol signal.
It should be noted that, the data start flag in the protocol signal includes a plurality of byte bits, and the data end flag includes a plurality of byte bits. The number of byte bits of the data start flag and the data end flag may be the same, for example, the data start flag includes 16 byte bits and the data end flag includes 16 byte bits. Wherein the valid data includes a greater number of byte bits. Alternatively, the valid data includes 64 byte bits.
The transmission method of the protocol signal is applied to a protocol signal transmission system, and the protocol signal transmission system comprises a first complex programmable logic device connected with a host device, a second complex programmable logic device connected with a plurality of slave devices and a low-voltage differential signal line LVDS used for connecting the first complex programmable logic device and the second complex programmable logic device. Because a plurality of protocol signals can be transmitted simultaneously through the low-voltage differential signal line LVDS, protocol signals of various protocol types can be transmitted through only a plurality of interfaces without arranging independent interfaces and cables for each protocol signal, and therefore the complexity of hardware layout is reduced.
Fig. 3 is a schematic diagram of a transmission method of a protocol signal according to an embodiment of the present application. In an embodiment of the present application, based on the embodiment provided in fig. 2, the slave device may also feed back the response data signal to the master device through the low voltage differential signal line. As shown in fig. 3, the method further includes:
s204, the slave device feeds back a response data signal to the second complex programmable logic device through the corresponding protocol interface.
In the embodiment of the application, the response data signal can comprise the response and replied data of the slave device.
S205, the second complex programmable logic device transmits the response data signals to the first complex programmable logic device through the low-voltage differential signal line LVDS.
Optionally, the low voltage differential signal line LVDS includes a reception clock signal line and a reception data signal line; the response data signal includes a second clock signal and a second data signal; correspondingly, the method comprises the following steps: the second complex programmable logic device transmits a second clock signal in the response data signal to the first complex programmable logic device through the reception clock signal line, and transmits a second data signal in the response data signal to the first complex programmable logic device through the reception data signal line.
Wherein the receive clock signal line may be represented by rx_clk and the receive DATA signal line may be represented by rx_data. Wherein the second clock signal and the second data signal are protocol signals fed back from the slave device to the host device. It should be noted that, the receiving clock signal line and the receiving data signal line each occupy one interface, that is, only 2 interfaces are required for transmitting the response data signal through the low voltage differential signal line LVDS.
S206, the first complex programmable logic device sends a response data signal to the baseboard management controller BMC on the host device.
In the embodiment of the application, since the low-voltage differential signal line LVDS can simultaneously transmit the response data signals of a plurality of protocol types, only a plurality of interfaces (particularly 2 interfaces) can transmit protocol signals of various protocol types, and independent interfaces and cables are not required to be distributed for each protocol signal, thus reducing the complexity of hardware layout.
Fig. 4 is a schematic structural diagram of a transmission device for protocol signals according to an embodiment of the present application. The protocol signal transmission system comprises a first complex programmable logic device connected with a host device, a second complex programmable logic device connected with a plurality of slave devices and a low-voltage differential signal line LVDS used for connecting the first complex programmable logic device and the second complex programmable logic device; the transmission device includes: a sending module 401, a transmitting module 402 and a determining module 403;
the sending module 401 is configured to send at least one protocol signal to the first complex programmable logic device by using the baseboard management controller BMC on the host device;
a transmission module 402, configured to transmit at least one protocol signal to a second complex programmable logic device through a low voltage differential signal line LVDS by using the first complex programmable logic device;
the determining module 403 is configured to determine a protocol type of each protocol signal by using the second complex programmable logic device, and transmit each protocol signal to a slave device corresponding to the respective protocol type through a plurality of protocol interfaces.
In one possible design, the low voltage differential signal line LVDS includes a transmit clock signal line and a transmit data signal line; the protocol signal includes a first clock signal and a first data signal; accordingly, the transmission module 402, configured to transmit at least one protocol signal to the second complex programmable logic device through the low voltage differential signal line LVDS, specifically includes: the first complex programmable logic device transmits the first clock signal in each protocol signal to the second complex programmable logic device through the transmission clock signal line, and transmits the first data signal in each protocol signal to the second complex programmable logic device through the transmission data signal line.
In one possible design, the protocol signal includes a data start flag, valid data, and a data end flag, wherein the valid data includes a plurality of byte bits, one byte bit range for each protocol type of protocol signal; accordingly, the determining module 403, configured to determine a protocol type of each protocol signal by using the second complex programmable logic device, transmit each protocol signal to a slave device corresponding to a respective protocol type through a plurality of protocol interfaces, specifically includes: the second complex programmable logic device determines at least one byte bit of valid data in each protocol signal; determining a byte bit range to which at least one byte bit belongs; determining the protocol type of each protocol signal according to the corresponding relation between the protocol type and the byte bit range; and transmitting each protocol signal to the slave device corresponding to the respective protocol interface through the protocol interface corresponding to the protocol type of each protocol signal.
In one possible design, the protocol interfaces include one or more of an I2C protocol interface, an SPI protocol interface, a JATG protocol interface, and a UART protocol interface, and the protocol types include one or more of an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal; accordingly, the determining module 403 transmits, through the protocol interface corresponding to the protocol type of each protocol signal, each protocol signal to the slave device connected to the protocol interface, and specifically includes: if the protocol type of the protocol signal is an I2C protocol signal, transmitting the protocol signal to a slave device connected with the I2C protocol interface through an I2C protocol interface corresponding to the I2C protocol signal; or if the protocol type of the protocol signal is SPI protocol signal, transmitting the protocol signal to the slave equipment connected with the SPI protocol interface through the SPI protocol interface corresponding to the SPI protocol signal; or if the protocol type of the protocol signal is UART protocol signal, transmitting the protocol signal to the slave device connected with the UART protocol interface through the UART protocol interface corresponding to the UART protocol signal; or if the protocol type of the protocol signal is a JATG protocol signal, transmitting the protocol signal to a slave device connected with the JATG protocol interface through the JATG protocol interface corresponding to the JATG protocol signal.
In one possible design, the data start flag includes 16 byte bits, the data end flag includes 16 byte bits, and the valid data includes 64 byte bits.
In one possible design, the transmission device further comprises: and a feedback module. The feedback module is used for the slave equipment to feed back response data signals to the second complex programmable logic device through the corresponding protocol interface; the second complex programmable logic device transmits response data signals to the first complex programmable logic device through a low voltage differential signal line LVDS; the first complex programmable logic device sends a response data signal to the baseboard management controller BMC on the host device.
In one possible design, the low voltage differential signal line LVDS includes a receive clock signal line and a receive data signal line; the response data signal includes a second clock signal and a second data signal; correspondingly, the feedback module is used for the second complex programmable logic device to transmit the response data signal to the first complex programmable logic device through the low voltage differential signal line LVDS, and specifically comprises the following steps: the second complex programmable logic device transmits a second clock signal in the response data signal to the first complex programmable logic device through the reception clock signal line, and transmits a second data signal in the response data signal to the first complex programmable logic device through the reception data signal line.
The device provided in this embodiment may be used to implement the technical solution of the foregoing method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
Fig. 5 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application. The electronic device may be a server. The server comprises a host device, a slave device and a protocol signal transmission system. As shown in fig. 5, the electronic apparatus of the present embodiment includes: a processor 501 and a memory 502; wherein, the memory 502 is used for storing computer execution instructions; the processor 501 is configured to execute computer-executable instructions stored in the memory to implement the steps performed by the electronic device in the above-described embodiments. Reference may be made in particular to the relevant description of the embodiments of the method described above.
Alternatively, the memory 502 may be separate or integrated with the processor 501.
When the memory 502 is provided separately, the electronic device further comprises a bus 503 for connecting the memory 502 and the processor 501.
The embodiment of the application also provides a computer storage medium, wherein computer execution instructions are stored in the computer storage medium, and when a processor executes the computer execution instructions, the transmission method of the protocol signals of the method embodiments is realized.
The embodiment of the application also provides a computer program product, which comprises a computer program, and when the computer program is executed by a processor, the transmission method of the protocol signals of the method embodiments is realized.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to implement the solution of this embodiment.
In addition, each functional module in the embodiments of the present application may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The units formed by the modules can be realized in a form of hardware or a form of hardware and software functional units.
The integrated modules, which are implemented in the form of software functional modules, may be stored in a computer readable storage medium. The software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or processor to perform some of the steps of the methods of the various embodiments of the application.
It should be understood that the above processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, abbreviated as DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile memory NVM, such as at least one magnetic disk memory, and may also be a U-disk, a removable hard disk, a read-only memory, a magnetic disk or optical disk, etc.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component Interconnect, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or to one type of bus.
The storage medium may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). It is also possible that the processor and the storage medium reside as discrete components in an electronic device or a master device.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A transmission method of a protocol signal, which is characterized by being applied to a protocol signal transmission system, wherein the protocol signal transmission system comprises a first complex programmable logic device connected with a host device, a second complex programmable logic device connected with a plurality of slave devices, and a low-voltage differential signal line LVDS for connecting the first complex programmable logic device and the second complex programmable logic device; the method comprises the following steps:
the BMC on the host device sends at least one protocol signal to the first complex programmable logic device;
the first complex programmable logic device transmits at least one protocol signal to the second complex programmable logic device through a low voltage differential signal line LVDS;
the second complex programmable logic device determines the protocol type of each protocol signal, and transmits each protocol signal to the slave device corresponding to the respective protocol type through a plurality of protocol interfaces.
2. The method of claim 1, wherein the low voltage differential signal line LVDS includes a transmit clock signal line and a transmit data signal line; the protocol signal includes a first clock signal and a first data signal;
accordingly, the first complex programmable logic device transmits at least one protocol signal to a second complex programmable logic device through a low voltage differential signal line LVDS, comprising:
the first complex programmable logic device transmits the first clock signal in each protocol signal to the second complex programmable logic device through a transmission clock signal line, and transmits the first data signal in each protocol signal to the second complex programmable logic device through a transmission data signal line.
3. The method of claim 1, wherein the protocol signal comprises a data start flag, valid data and a data end flag, wherein the valid data comprises a plurality of byte bits, one byte bit range for each protocol type of protocol signal;
accordingly, the second complex programmable logic device determines a protocol type of each protocol signal, and transmits each protocol signal to a slave device corresponding to the respective protocol type through a plurality of protocol interfaces, including:
the second complex programmable logic device determines at least one byte bit of valid data in each protocol signal;
determining a byte bit range to which the at least one byte bit belongs;
determining the protocol type of each protocol signal according to the corresponding relation between the protocol type and the byte bit range;
and transmitting each protocol signal to the slave device corresponding to the respective protocol interface through the protocol interface corresponding to the protocol type of each protocol signal.
4. A method according to claim 3, wherein the protocol interface comprises one or more of an I2C protocol interface, an SPI protocol interface, a JATG protocol interface, and a UART protocol interface, and the protocol type comprises one or more of an I2C protocol signal, a JATG protocol signal, an SPI protocol signal, and a UART protocol signal;
correspondingly, the transmitting each protocol signal to the slave device connected with the protocol interface through the protocol interface corresponding to the protocol type of each protocol signal comprises the following steps:
if the protocol type of the protocol signal is an I2C protocol signal, transmitting the protocol signal to a slave device connected with the I2C protocol interface through an I2C protocol interface corresponding to the I2C protocol signal; or,
if the protocol type of the protocol signal is an SPI protocol signal, transmitting the protocol signal to slave equipment connected with the SPI protocol interface through an SPI protocol interface corresponding to the SPI protocol signal; or,
if the protocol type of the protocol signal is UART protocol signal, transmitting the protocol signal to a slave device connected with the UART protocol interface through a UART protocol interface corresponding to the UART protocol signal; or,
if the protocol type of the protocol signal is a JATG protocol signal, transmitting the protocol signal to a slave device connected with the JATG protocol interface through the JATG protocol interface corresponding to the JATG protocol signal.
5. The method of claim 3, wherein the data start flag comprises 16 byte bits, the data end flag comprises 16 byte bits, and the valid data comprises 64 byte bits.
6. The method of any one of claims 1-5, further comprising:
the slave device feeds back a response data signal to the second complex programmable logic device through a corresponding protocol interface;
the second complex programmable logic device transmits the response data signal to the first complex programmable logic device through the low voltage differential signal line LVDS;
the first complex programmable logic device sends the response data signal to a baseboard management controller BMC on the host device.
7. The method of claim 6, wherein the low voltage differential signal line LVDS includes a receive clock signal line and a receive data signal line; the response data signal includes a second clock signal and a second data signal;
accordingly, the second complex programmable logic device transmitting the response data signal to the first complex programmable logic device through the low voltage differential signal line LVDS includes:
the second complex programmable logic device transmits a second clock signal in the response data signal to the first complex programmable logic device through the receiving clock signal line, and transmits a second data signal in the response data signal to the first complex programmable logic device through the receiving data signal line.
8. A transmission apparatus for a protocol signal, which is applied to a protocol signal transmission system, wherein the protocol signal transmission system comprises a first complex programmable logic device connected with a host device, a second complex programmable logic device connected with a plurality of slave devices, and a low voltage differential signal line LVDS for connecting the first complex programmable logic device and the second complex programmable logic device; the device comprises:
the sending module is used for sending at least one protocol signal to the first complex programmable logic device by the baseboard management controller BMC on the host equipment;
the transmission module is used for transmitting at least one protocol signal to the second complex programmable logic device through the low-voltage differential signal line LVDS by the first complex programmable logic device;
the determining module is used for determining the protocol type of each protocol signal by the second complex programmable logic device, and transmitting each protocol signal to the slave equipment corresponding to the respective protocol type through a plurality of protocol interfaces.
9. An electronic device, comprising: a processor and a memory;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory, causing the processor to perform the method of transmitting protocol signals according to any one of claims 1 to 7.
10. A computer storage medium having stored therein computer executable instructions which, when executed by a processor, implement the method of transmitting protocol signals according to any one of claims 1 to 7.
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| CN202310793550.2A CN116828083A (en) | 2023-06-29 | 2023-06-29 | Protocol signal transmission method, device, equipment and storage medium |
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| CN202310793550.2A CN116828083A (en) | 2023-06-29 | 2023-06-29 | Protocol signal transmission method, device, equipment and storage medium |
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