CN1168128C - Structure of critical dimension test strip - Google Patents

Abstract

A structure of key size test strip is prepared as forming a bottom layer on a part of base in test region and forming a patterned key material layer on crystal and test region, setting bottom layer thickness to be same as height difference of base surface in crystal. The critical material layer on the crystal, the bottom layer and the substrate outside the bottom layer in the test area has crystal pattern, the first test pattern and the second test pattern, which are obtained by the crystal mask pattern, the first test mask pattern and the second test mask pattern. The photomask patterns have the same pattern type and have the first pattern width.

Description

Construction of Critical Dimensions Test Strips

The present invention relates to a structure of a monitoring tool for a Lithography & Etching Process, and in particular to a structure of a critical dimension bar (Critical Dimension Bar; CDBar).

In each stage of the semiconductor (Semiconductor) manufacturing process, the photolithography process is the most important link, and the purpose of the photolithography process is to form a patterned photoresist layer (Photo Resist) on the material layer to be patterned. Layer); and the etching process uses the patterned photoresist layer as a mask (Mask) to etch the exposed material layer to form a patterned material layer. When the pattern width of the formed patterned material layer is an important parameter of the characteristics of the electronic component (or when the pattern width is the smallest among the patterned wafer layers), this width is called the critical dimension (Critical Dimension; CD), And this material layer may be called a key material layer. Since changes in critical dimensions have a significant impact on the characteristics of electronic components, the error of critical dimensions must be strictly controlled within a certain range to avoid reducing the quality of components.

Please refer to FIG. 1, in a general photolithography etching process, in order to monitor the critical dimension error of the patterned key material layer, the scribe line (Scribe Line, that is, each crystal square) between the crystal squares 110 on the wafer 100 is often A critical dimension test strip 120 with a simple critical material layer pattern is simultaneously formed on the thick dotted line between 110). This is because the integrated circuit pattern on the surface of the wafer 110 is usually very complex, making it difficult to directly measure the critical dimension of the patterned critical material layer, so the critical dimension of the simple critical material layer pattern on the critical dimension test strip 120 must be measured first. , and then deduce the critical dimension of the pattern of the critical material layer on the crystal square 110 .

Please refer to FIG. 2A , which is a schematic cross-sectional view of the structure of a conventional critical dimension test strip 120 , and its manufacturing process is roughly described as follows. First, in the photolithographic etching process of each layer before the critical material layer is formed, the photomask used does not have the pattern of the critical dimension test strip 120, so the surface of the substrate 200 of the critical dimension test strip 120 is flat . Next, when an unpatterned key material layer is formed on the wafer, the base 200 of the CD test strip 120 is simultaneously covered with a layer of key material layer 210 . Next, a photolithography process is performed, wherein the photoresist layer (not shown) above the critical dimension test strip 120 has a test photomask pattern of "the same type as the pattern on the wafer (here, a hole-like pattern is used as an example)" The test photomask pattern has the same pattern width as the wafer photomask pattern, but its pattern arrangement is relatively simple, so as to facilitate the measurement of the CD of the test pattern on the CD test strip 120 .

Please continue to refer to FIG. 2A , after subsequent processing steps such as developing, photoresist drying, and etching process, a test opening 220 a is formed in the key material layer 210 . Since the critical dimension test strip 120 and the wafer area are both exposed with the pattern of the same pattern width, and both receive the same post-processing steps and etching process, as long as the critical dimension of the test opening 220a on the critical dimension test strip 120 is measured, it can be deduced. The critical dimensions of the openings on the wafer 110 are obtained.

However, referring to FIG. 3A , in a general manufacturing process, before the key material layer 210 is formed, the substrate 300 in the area of the wafer 110 must have undergone many different patterning steps, so that the surface of the substrate 300 has obvious ups and downs. Therefore, when the photoresist layer 215 is coated on the key material layer 210 and then exposed, the focus of the bottom of the photoresist layer 215 at the high position (P position) and the low position (Q position) of the substrate 300 is shifted. Focus Offset, that is, the distance between the bottom of the photoresist layer 215 at the two locations and the focus of the exposure light source will be different. Therefore, please refer to FIG. 3B, the opening width of the patterned photoresist layer 215 at the P position and the Q position, that is, the critical dimensions _d1 and _d2 of the openings 220b and 220c of the key material layer 210 after the etching process are There will be differences.

As mentioned above, the surface of the substrate 200 ( FIG. 2A ) of the CD test strip 120 is not patterned in the previous step, so the surface of the substrate 300 of the wafer 110 cannot simulate the ups and downs of the substrate 300 . Therefore, the test opening 220a on the CD test strip 120 has only one critical dimension, and the CD difference between the openings 220b and 220c in the critical material layer 210 on the wafer 110 cannot be monitored. This is a problem with the existing CD test strip structure. one.

In addition, for the second problem of the prior art, please refer to FIG. 2B , which is a top view of the existing critical dimension test strip 120 . As shown in FIG. 2B, in the test pattern of the existing critical dimension test strip 120, there are only a few test openings 220a at a great distance, so it cannot be used to monitor the dense arrangement of the openings 220b/c in the critical material layer on the chip. In the case of critical dimension deviation, this deviation phenomenon is caused by mutual interference of transmitted light of adjacent hole photomask patterns during exposure.

The present invention proposes a structure of a critical dimension test strip, which can solve the problem of the existing critical dimension test strip, that is, it can be used to monitor the "crystal square key material layer" with high and low surface undulations and pattern distribution. Pattern" key dimensions. The structure is fabricated in a test area on a substrate, and the test area is located between several wafers, and the structure includes a bottom layer and a part of a key material layer patterned. Wherein the bottom layer is located on a part of the substrate in the test area, the thickness of the bottom layer is about the same as the height difference of the surface of a wafer, and the substrate outside the bottom layer in the test area is called a low-level area; and the key material layer Covering the crystal square and the test area, wherein in the chip, the bottom layer in the test area and the key material layer on the low-level area, there are respectively a crystal square pattern, a first test pattern and a second test pattern, which are respectively formed by the crystal square. The photomask pattern, the first test photomask pattern and the second test photomask pattern are obtained. These photomask patterns all have the same type of pattern, and all have the first pattern width.

The present invention also proposes a method for manufacturing critical dimension test strips, which are manufactured in a test area on a substrate and located between several crystal squares. The steps of this method are as follows: first, a part of the substrate in the test area and a bottom layer is formed on a part of the substrate in each wafer square, and the part of the test area where the bottom layer is not formed is called a low-level region. Then a conformal key material layer is formed on the wafer and the test area, and then exposed using a photomask having a chip photomask pattern, a first test photomask pattern and a second test photomask pattern, so as to A chip pattern, a first test pattern, and a second test pattern are respectively formed in the crystal square, the bottom layer in the test area, and the key material layer above the low position area, wherein the chip photomask pattern, the first test photomask pattern and the second The pattern types of the test photomask patterns are the same, and all have the first pattern width.

In addition, in the above-mentioned structure and manufacturing method of the critical dimension test strip, when the crystal square pattern includes the first type of area and the second type of area with different graphics density, the first test pattern and the second test pattern are still Two kinds of regions with the same pattern density can be included, so as to accurately simulate the influence of the change of pattern distribution density on the crystal square on the critical dimension of the key material layer.

In addition, in the above-mentioned structure and manufacturing method of the critical dimension test strip of the present invention, the key material layer is, for example, an insulating layer, and at this time, the crystal square pattern is a pattern of a contact window opening or a via hole; the key material layer is, for example, A conductor layer, and at this time, the crystal square pattern is a pattern of a gate line or a conductive line.

The present invention further proposes a method for monitoring critical dimension deviation, which is carried out using the aforementioned critical dimension test strip proposed by the present invention, and the method is to measure the first test pattern and the second test pattern on the critical dimension test strip respectively. The critical dimensions of the graphics are then compared to obtain the deviation value of the critical dimensions of the graphics in the wafer pattern. In addition, if the crystal square pattern contains the first and second regions with different pattern densities, and the first and second test patterns also have two regions with the same pattern densities, this method measures In the first test pattern and the second test pattern, the critical dimensions in the first and second regions are used to derive the deviation values of the critical dimensions in the corresponding parts of the crystal square patterns.

As mentioned above, the structure of the critical dimension test strip proposed by the present invention has the following advantages. One, because in the design of the critical dimension test strip of the present invention, simulate the height gap of the crystal square surface with a bottom layer, and form the first and second test patterns respectively on the bottom layer and the substrate of another part, so can It is used to measure the error value of the critical dimension on the surface of the wafer with high and low relief. Its two, because when the graphic distribution of the key material layer on the surface of the crystal square has density points, the first and second test patterns on the critical dimension test strip of the present invention also include two kinds of areas with the same density, so It can indeed reflect the critical dimension variation of the critical material layer on the chip.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below and described in detail with accompanying drawings. In the attached picture:

FIG. 1 shows the relative positions of each wafer and each critical dimension test strip on the wafer.

2A-2B illustrate the structure of a conventional critical dimension test strip, wherein FIG. 2A is a cross-sectional view thereof, and FIG. 2B is a top view thereof.

FIGS. 3A-3B are schematic diagrams of forming a key material layer and then performing a photolithographic etching process when the surface of a wafer has ups and downs.

FIGS. 4A-C illustrate the situation in which a field oxide layer, a polysilicon gate line, an insulating layer, and a contact window opening in the insulating layer are sequentially formed on the corresponding crystal squares in the first embodiment of the present invention.

5A-5C are cross-sectional views of the manufacturing process of the critical dimension test strip according to the first embodiment of the present invention.

FIG. 6 is a schematic diagram showing the relationship between critical dimension and focus offset (FocusOffset) in a general photolithography etching process.

FIG. 7 is a schematic diagram showing the structure of the test opening pattern of the critical dimension test strip according to the first embodiment of the present invention.

FIGS. 8A-8B illustrate the situation in which a field oxide layer and polysilicon gate lines are sequentially formed on corresponding crystal squares in the second embodiment of the present invention.

9A-9B are cross-sectional views of the manufacturing process of the critical dimension test strip according to the second embodiment of the present invention.

FIG. 10 is a schematic diagram of the structure of the polysilicon gate line pattern of CD test strips in the second embodiment of the present invention.

Explanation of the labeling of the diagram:

100: Wafer

110, 402, 802: crystal square (Die)

120, 404, 704, 804, 904: Critical Dimension Test Strip (CD Bar)

200, 300, 400, 700, 800, 900: Base

210: Critical Layer

215, 460, 860: Photoresist Layer (Photo Resist Layer)

220a, 470c, 470d, 710a, 710b, 710c, 710d: Test openings

220b, 220c: opening (Opening)

410: Pad Oxide

420: Mask Layer

425: mask layer opening

430a, 830a: Field Oxide (FOX)

430b, 705, 830b, 930: thermal oxide layer

440a, 440b, 840a, 840b: polysilicon gate lines

440c, 706, 840: polysilicon layer

450, 708: Insulating Layer (Insulating Layer)

470a, 470b: Contact Opening

840c, 840d: Test leads

940a, 940b: sparse test line area

940c, 940d: dense test line area

a, b: photoresist depth

d ₁ , d ₂ , α, β, α′, β′, α 1 , α 2 , β ₁ , _{β 2 ,} u, v, u _′ , v′, u ₁ , u ₂ , v ₁ , v ₂ : Critical Dimension (CD)

δ ₁ , δ ₂ : Test opening spacing

m ₁ , m ₂ : distance between test lines

P, Q: position label

first embodiment

In the first embodiment of the present invention, the structure and manufacturing process of the critical dimension test strip used to monitor the critical dimension of the contact window opening will be described, which is supplemented by Fig. 5A-5C; and the structure of each layer on the corresponding crystal square And the description of the production process is supplemented by Figures 4A-4C.

Please refer to FIG. 4A and FIG. 5A , firstly, a pad oxide layer 410 is formed on the wafer 402 and the substrate 400 of the CD strip 404 at the same time, and then a mask is formed on the wafer 402 and the pad oxide layer 410 of the CD strip 404 The material of the layer 420 is, for example, silicon nitride (SiN). Then mask layer openings 425 are formed in the pad oxide layer 410 and the mask layer 420 of the wafer 402 , and the pad oxide layer 410 and the mask layer 420 of the CD strip 404 are patterned at the same time to expose the CD strip 404 part of the substrate 400 . A high temperature oxidation step (Thermal Oxidation) is then carried out to form a field oxide layer (Field Oxide; FOX) 430a on the substrate 400 in the mask layer opening 425, and at the same time form the exposed part of the substrate 400 of the critical dimension test strip 404 thermal oxide layer 430b. Since the field oxide layer 430a and the thermal oxide layer 430b are formed at the same time, their thicknesses are approximately the same.

Referring to FIG. 4B and FIG. 5B , a conformal polysilicon layer (not shown) is then formed and patterned on the wafer 420 and the CD strip 404 to form a polysilicon gate line 440 a on the substrate 400 of the wafer 402 , the part of which crosses the field oxide layer 430a is labeled 440b; meanwhile, a polysilicon layer 440c is formed on the thermal oxide layer 430b of the critical dimension test strip 404 . Since the polysilicon gate lines 440a, 440b and the polysilicon layer 440c are patterned from a conformal polysilicon layer, they have the same thickness. Next, a conformal insulating layer 450 is formed on the die cube 402 and the CD strip 404 , and then a photoresist layer 460 is coated on the die cube 402 and the CD strip 404 .

Referring to FIG. 4C and FIG. 5C , the photoresist layer 460 located on the die square 402 and the CD test strip 404 is then patterned to form several photoresist layer openings therein. The photomask (not shown) used in this patterning process has a wafer photomask pattern, a first test photomask pattern and a second test photomask pattern, which respectively correspond to the wafer 402, CD The pattern to be formed on the high position area (the area of the polysilicon layer 440c ) and the low position area (the area of the substrate 400 other than the polysilicon layer 440c ) of the test strip 404 . The above three photomask patterns are all patterns of contact window openings, and the pattern widths of the three patterns are the same.

Referring to FIG. 4C and FIG. 5C , next, the insulating layer 450 is etched using the patterned photoresist layer 460 as a mask to simultaneously achieve the following four purposes:

(1). Form a contact window opening 470a in the insulating layer 450 on both sides of the polysilicon gate line 440a;

(2). Form a contact window opening 470b in the insulating layer 450 above the polysilicon gate line 440b of the wafer 402;

(3). Form a test opening 470c in the insulating layer 450 above the substrate 400 of the critical dimension test strip 404; and

(4). Form a test contact opening 470 d in the insulating layer 450 above the polycrystalline layer 440 c of the critical dimension test strip 404 .

Please continue to refer to FIG. 4B and FIG. 5B, since the thickness of the field oxide layer 430a and the thermal oxide layer 430b are approximately the same, and the thicknesses of the polysilicon gate lines 440a, 440b and the polysilicon layer 440c are all the same, and the thickness of the conformal insulating layer 450 It is also the same everywhere, so the position of the upper edge of the insulating layer 450 above the base 400 of the critical dimension test strip 404 is also flush with the positions of the upper edge of the insulating layer 450 on both sides of the polysilicon gate 440a, and the position of the insulating layer 450 above the polysilicon layer 440c The position of the upper edge is also flush with the position of the upper edge of the insulating layer 450 above the polysilicon gate 440b. Therefore, please continue to refer to FIG. 4C and FIG. 5C, after the photolithography etching process, the test opening 470c of the critical dimension test strip 404 has the same critical dimension α as the contact window openings 470a on both sides of the polysilicon gate line 440a, and the polysilicon layer The test opening 470d above 440c has the same CD as the contact opening 470b above the polysilicon gate line 440b.

Since the critical dimensions of the contact opening 470a and the test opening 470c are the same, and the critical dimensions of the contact opening 470b and the test opening 470d are the same, measuring the critical dimensions α and β of the test openings 470c and 470d can determine the critical dimensions of the contact openings 470a and 470b. critical size. Please refer to FIG. 4B, 5B and FIG. 6. When the values of α and β are very close, it indicates the focus position of the exposure light source, that is, the position where the focus offset is 0 is located in the "lower area (substrate 400 area) on the wafer 402. Between the position of the upper edge of the insulating layer 450" and "the position of the upper edge of the insulating layer 450 in the high position region (polysilicon gate line 440b region), that is, on the critical dimension test strip 404 of the "low position region (substrate 400 region) Between the position of the upper edge of the insulating layer 450" and "the position of the upper edge of the insulating layer 450 in the high-level region (polysilicon layer 404c region)", here is the preferred position. Conversely, when the values of the two critical dimensions differ greatly, it means that the focus position of the exposure light source is below the upper edge position of the insulating layer 450 in the lower region of the wafer 402 (critical dimension test strip 404) (where the focus offset is less than 0 , that is, the positions of α' and β' in FIG. The focusing position of the light source thereon makes the contact window openings 470a and 470b of the lower region and the upper region on the wafer square have the critical dimension with the least difference.

Furthermore, referring to FIG. 7 , in addition to the above-mentioned critical dimension test strip with a simple distribution pattern of contact window openings, another structure of a critical dimension test strip 704 is shown here, the formation method of which is the same as that of the aforementioned FIG. 5A The one shown in -5C is the same, but in the contact window opening pattern of the insulating layer 708 on the upper region (the area of the polysilicon layer 706, under which the polysilicon layer 706 still has a thermal oxide layer 705) and the lower region (substrate 700), both Two types of regions with different densities of contact openings are further distinguished, and the width-to-distance ratio (Duty Ratio) of the contact openings in these two regions is the same as the width-to-distance ratio of the contact openings in the insulating layer on the wafer. In addition, in the previous process of patterning the insulating layer 708, the photomasks used include a crystal square photomask pattern, a first test photomask pattern and a second test photomask pattern, which correspond to the crystal square photomask pattern respectively. , the patterns to be formed on the high position region (polysilicon layer 706 region) and the low position region (substrate 700 region) of critical dimension test strip 704, these three photomask patterns are all in the form of contact window openings, and these three photomask patterns The graphic widths of the die patterns are all the same, and both can distinguish two kinds of regions with different graphic densities.

Please continue to refer to FIG. 7 , the pattern on the critical dimension test strip 704 can be divided into four regions, wherein the lower region (substrate 700 region) on the left of the figure has:

1. Sparsely arranged contact window openings 710a, the critical dimension is α ₁ , the pitch is δ ₁ , and the width-to-distance ratio of the contact window openings α ₁ : δ ₁ is, for example, 1:3.0, to simulate the isolated contact window openings; and

2. Closely arranged contact window openings 710b, the critical dimension is α ₂ , the pitch is δ ₂ , and the width-to-distance ratio of the contact window openings α ₂ : δ ₂ is, for example, 1:1.5, so as to simulate the adjacent Contact window opening.

And in the high position region (polysilicon layer 706 region) on the right of the figure, there are:

3. Closely arranged contact window openings 710c, the critical dimension is β ₂ , the pitch is δ ₂ , and the width-to-distance ratio of the contact window openings β ₂ : δ ₂ is, for example, 1:1.5, so as to simulate the adjacent Contact window opening.

4. It also has sparsely arranged contact openings 710d, the critical dimension of which is β ₁ , the pitch is δ ₁ , and the width-to-distance ratio of the contact openings β ₁ : δ ₁ is, for example, 1:3.0, to simulate the high position region of the crystal square Isolated contact window opening.

In this way, the critical dimensions of the adjacent contact window openings and isolated contact window openings at the height of the wafer can be deduced from the critical dimensions α ₁ , α ₂ , β ₁ and β ₂ on the critical dimension test strip 704, and then the obtained Key dimension to determine whether it is necessary to adjust the focus position during exposure.

As mentioned above, since in the first embodiment of the present invention, the thermal oxide layer 430b (705) is formed on the part of the substrate 400 (700) of the critical dimension test strip 404 (704), and then the thermal oxide layer 430b ( 705 ), a polysilicon layer 440c ( 706 ) is formed, and then a conformal insulating layer 450 ( 708 ) is covered, so that the height difference between the surface of the critical dimension test strip 404 ( 704 ) is the same as that of the wafer 402 . Therefore, by measuring the test openings 470c (710a/b) and 470d (710c/d) formed in the insulating layer 450 (708) on the CD strip 404 (704), the wafer square 402 can be deduced. The variation of the critical dimensions of the contact openings 470 a and 470 b formed in the insulating layer 450 . In addition, when the opening pattern of the contact window in the insulating layer 450 of the wafer 402 is divided into density and density, the opening pattern of the contact window in the high position area and the low position area of the critical dimension test strip 704 in the first embodiment of the present invention also includes density (710a and 710d) and dense (710b and 710c) regions, so the variation of the critical dimension of the contact window opening on the wafer can be accurately simulated.

second embodiment

In this second embodiment, the structure and manufacturing process of the critical dimension test strip with a linear pattern will be described, supplemented by FIGS. 8A-8B ; 9A-9B is supplemented.

Please refer to FIG. 8A and FIG. 9A. Firstly, a field oxide layer 830a and a thermal oxide layer 830b are formed on the crystal cube 802 and the substrate 800 of the critical dimension test strip 804 by thermal oxidation at the same time. Since the field oxide layer 830a and the thermal oxide layer 830b are simultaneously Formed, so the thickness of the two is roughly the same. A conformal polysilicon layer 840 is then formed on the die square 802 and the CD strip 804 , and then a photoresist layer 860 is formed on the polysilicon layer 840 of the die cube 802 and the CD strip 804 .

Please refer to FIG. 8B and FIG. 9B, then a photolithography process is performed to pattern the photoresist layer 860, and the photomask used in this patterning process has a crystal square photomask pattern, a first test photomask pattern and the second test photomask pattern, these three correspond to the wafer square 802, the CD strip 804 high position area (the area of the thermal oxide layer 830b) and the low position area (the substrate 800 area of the CD test strip 804) respectively. For the formed graphics, the three photomask patterns are all linear, and the pattern widths of the three photomask patterns are the same.

Please continue referring to FIG. 8B and FIG. 9B , and then use the patterned photoresist layer 860 as a mask to etch the underlying polysilicon layer 840 to form a polysilicon gate line 840 a on the substrate 800 of the wafer 802 , which spans the field The portion above the oxide layer 830a is 840b; at the same time, a linear polysilicon layer 840c is formed on the substrate 800 of the CD strip 804, and a linear polysilicon layer 840d is formed on the thermal oxide layer 830b of the CD strip 804.

Please refer to FIG. 8A and FIG. 9A at the same time. Since the thickness of the field oxide layer 830a and the thermal oxide layer 830b are approximately the same, and the thickness of the conformal polysilicon layer 840 is the same everywhere, the high position area of the crystal square 802 and the critical dimension test strip 804 The position of the upper edge of the polysilicon layer 840 (the area of the field oxide layer 830a and the area of the thermal oxide layer 830b) is flush with each other. In addition, the position of the upper edge of the polysilicon layer 840 in the lower area of the critical dimension test strip 804 (that is, the surface of the substrate 800 ) is also flush with the wafer square 802 . Therefore, "the linear polysilicon layer 840c on the substrate 800 of the critical dimension test strip 804" and "the polysilicon gate line 840a on the substrate 800 of the wafer square 802" will have the same critical dimension u, and the "critical dimension test strip 804 The linear polysilicon layer 840d above the thermal oxide layer 830b" and the "polysilicon gate line 840b above the field oxide layer 830a of the wafer 802" will have the same critical dimension v.

Next please refer to FIG. 8B and FIG. 9B at the same time. Since the linear polysilicon layer 840c has the same critical dimension as the polysilicon gate line 840a, and the linear polysilicon layer 840d has the same critical dimension as the polysilicon gate line 840b, the measurement of the linear polysilicon The widths u and v of the layers 840c and 840d are the critical dimensions of the polysilicon gate lines 840a and 840b. Please refer to the schematic diagram of FIG. 6 again. When the values of u and v are very close, it means that the focus position of the exposure light source is on the crystal square 802 between the "upper edge position of the polysilicon layer 840 in the lower region (substrate 800 region)" and the "higher position". Between the position of the upper edge of the polysilicon layer 840 in the area (field oxide layer 830a), that is, the position of the upper edge of the polysilicon layer 840 in the lower area (substrate 800 area) on the critical dimension test strip 804" and the "higher area ( Between the upper edge of the polysilicon layer 840 in the field oxide layer 830b region), this is the preferred position. Conversely, when the values of the two critical widths differ greatly, it means that the focus position of the exposure light source is below the upper edge position of the polysilicon layer 840 in the lower region of the crystal square 820 (critical dimension test strip 804) (where the focus offset is less than 0, That is, the positions of u' and v' in FIG. The focus position on the crystal square 802 minimizes the critical dimension difference between the polysilicon gate lines 840 a and 840 b in the lower and upper regions of the wafer 802 .

In addition, referring to FIG. 10 , in addition to the aforementioned critical dimension test strips with isolated polysilicon gate lines, another critical dimension test strip 904 according to the second embodiment of the present invention is shown here. The ones shown in 9A-9B are the same, but the density of the pattern is further distinguished in the linear polysilicon layer pattern on the high-level area (the thermal oxide layer 930 area on the right in the figure) and the low-level area (the substrate 900 area on the left in the figure). The two different regions have the same pattern density as that of the crystal square pattern. In addition, in the previous process of patterning the polysilicon layer, the photomasks used include a crystal square photomask pattern, a first test photomask pattern and a second test photomask pattern, which respectively correspond to the crystal square, The patterns to be formed on the high-position area (thermal oxide layer 930 area) and the low-position area (substrate 900 area) of critical dimension test strip 904, these three photomask patterns are all in the form of lines, and these three photomask patterns The width of the linear graphics is the same, and can distinguish two kinds of areas with different graphics density.

Please continue to refer to FIG. 10 , the pattern of the critical dimension test strip 904 can be divided into four areas, wherein in the lower area (substrate 900 area) on the left of the figure are:

1. Sparsely arranged linear polysilicon layer pattern 940a, wherein the width of the linear polysilicon layer is u ₁ , the pitch is m ₂ , and the line width-to-distance ratio u ₁ : m ₂ is, for example, 1:4.0 to simulate the low-level region of the crystal square isolated polysilicon gate lines; and

2. Closely arranged linear polysilicon layer pattern 940c, wherein the width of the linear polysilicon layer is u ₂ , the pitch is m ₁ , and the line width-to-distance ratio u ₂ : m ₁ is, for example, 1:2.0 to simulate the low-level region of the crystal square in the immediate vicinity of the polysilicon gate line.

And in the high-level area on the right of the figure (thermal oxide layer 930 area) there are:

3. A closely arranged linear polysilicon layer pattern 940d, wherein the width of the linear polysilicon layer is v ₂ , the pitch is m ₁ , and the line width-to-distance ratio v ₂ : m ₁ is, for example, 1:2.0 to simulate the high-level region of the crystal square the immediately adjacent polysilicon gate lines; and

4. Sparsely arranged linear polysilicon layer pattern 940b, wherein the width of the linear polysilicon layer is v ₁ , the pitch is m ₂ , and the line width-to-distance ratio v ₁ : m ₂ is, for example, 1:4.0 to simulate the high-level area of the crystal square isolated polysilicon gate lines.

In this way, the critical dimensions of the adjacent polysilicon gate lines and isolated polysilicon gate lines in the high-level area and the low-level area of the crystal square can be obtained from the line widths in the linear polysilicon layer patterns 940a, 940c, 940b, and 940b on the corresponding critical dimension test strip 904. u ₁ , u ₂ , v ₁ and v ₂ are deduced, and then it is determined whether it is necessary to adjust the focus position during exposure based on the obtained critical dimensions.

As mentioned above, in the design of the critical dimension test strip of the second embodiment of the present invention, the thermal oxide layer 830b (930) is formed on the critical dimension test strip 804 (904), and then the thermal oxide layer 830b (930) is formed on the critical dimension test strip 804 (904). A conformal polysilicon layer 840 ( 940 ) is formed on it, so that the CD strip 804 ( 904 ) surface has the same height difference as the die cube 802 surface. Therefore, by measuring the line width u (u ₁ , u ₂ ) and v (v ₁ , v ₂ ) on the substrate 800 ( 900 ) and the thermal oxide layer 830 b ( 930 ) of the critical dimension test strip 804 ( 904 ), it can be The CD variation of the polysilicon gate lines 840 a and 840 b on the die 804 is obtained. In addition, when the patterns of the polysilicon gate lines on the surface of the wafer have density and density, the test patterns of the high position area and the low position area of the critical dimension test strip 904 of the present invention also include sparse (940a and 940b) and dense (940c and 940d) Two, but can truly reflect the critical dimension change of the critical material layer on the wafer.

To sum up, the structure of the critical dimension test strip proposed by the two preferred embodiments of the present invention has the following advantages. One, because in the design of the critical dimension test strip of preferred embodiment of the present invention, simulate the height gap of the crystal square surface with a bottom layer (thermal oxide layer+polysilicon layer, or only have thermal oxide layer), and on the bottom layer A contact window opening (or line) test pattern is formed separately from another part of the key material layer on the substrate, so it can be used to measure the critical dimensions of the contact window opening (or line) pattern on the surface of the wafer with ups and downs error value. Its two, when the pattern distribution of the contact window opening (or linear) of the key material layer on the surface of the crystal square has a difference in density, the contact window opening form of the high position area and the low position area on the critical dimension test strip of the present invention The (or linear) test pattern also includes two types of regions with the same density, so it can truly reflect the critical dimension variation of the critical material layer on the wafer.

Although the present invention has been disclosed above in conjunction with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be defined by the appended claims.

Claims (22)

1. The structure of a critical dimension test strip is suitable for a substrate, on which a plurality of crystal squares and a test area between the plurality of crystal squares are distinguished, and the structure is made on the test area, wherein each A plurality of first crystal square regions and a plurality of second crystal cube regions can be distinguished on the plurality of crystal cubes, wherein the height of the base in each of the plurality of first crystal cube regions is a first height, The height of the substrate in each of the plurality of second crystal cube regions is a second height, and the height of the substrate in the test area is a third height, wherein the second height is greater than the first height, and the third height is equal to the first height, the structure includes: A bottom layer, which is located on a part of the substrate in the test area, and the thickness of the bottom layer is approximately equal to the difference between the first height and the second height, and the other part of the substrate in the test area is called a low-lying areas; and A part of a patterned key material layer, the key material layer is located on the plurality of crystal squares and the test area, and the thickness of the key material layer is the same everywhere, wherein Each of the plurality of crystal cubes, the bottom layer in the test area, and the key material layer above the low position area respectively have a crystal cube pattern, a first test pattern and a second test pattern, which are respectively composed of a The crystal square photomask pattern, a first test photomask pattern and a second test photomask pattern are obtained, and the pattern types of the multiple photomask patterns are the same, and all have the same pattern width. 2. The critical dimension test strip structure of claim 1, wherein the critical material layer is an insulating layer, and the crystal square pattern is a pattern of contact openings or via holes. 3. The critical dimension test strip structure as claimed in claim 1, wherein the critical material layer is a conductive layer, and the crystal square pattern is a pattern of a gate line or a conductive line. 4. The structure of the critical dimension test strip as claimed in claim 1, wherein in the crystal square pattern, the first test pattern and the second test pattern, a first pattern with different density and density can be distinguished. One type of area and one second type of area, the first type of area has a first pattern width-to-pitch ratio on average, and the second type of area has a second pattern width-to-pitch ratio on average. 5. The critical dimension test strip structure as claimed in claim 1, the crystal square pattern is a contact opening pattern, and a plurality of field oxide layers and a plurality of polysilicon gate lines are formed on the substrate in the plurality of crystal cubes , the plurality of polysilicon gate lines cross over the plurality of field oxide layers; The bottom layer includes a thermal oxide layer and a polysilicon layer: The thermal oxide layer is located on a part of the substrate in the test area, the thickness of the thermal oxide layer is the same as the thickness of the plurality of oxide layers, and another part of the substrate in the test area is called a lower area; The polysilicon layer is located only on the thermal oxide layer, and the thickness of the polysilicon layer is the same as the thickness of the plurality of polysilicon gate lines; The key layer is an insulating layer, the insulating layer is located on the plurality of wafers and the test layer, and the thickness of the insulating layer is the same everywhere; and In the plurality of crystal squares, the polysilicon layer in the test area and the insulating layer above the low position area, there are respectively a chip pattern, a first test pattern and a second test pattern in the form of contact window openings, which They are respectively obtained from a chip photomask pattern, a first test photomask pattern and a second test photomask pattern, and the plurality of photomask patterns have the same pattern width. 6. The structure of the critical dimension test strip as claimed in claim 5, wherein in the chip pattern, the first test pattern and the second test pattern, it is possible to distinguish a first test pattern with different density of contact window openings. One type of area and a second type of area, the first type of area has a first contact window opening width-to-distance ratio on average, and the second type of area has a second contact window opening width-to-distance ratio on average. 7. The critical dimension test strip structure as claimed in claim 6, wherein the opening width-to-distance ratio of the first contact window is 1:3, and the opening width-to-distance ratio of the second contact window is 1:1.5. 8. The critical dimension test strip structure according to claim 1, wherein the square pattern is a gate line pattern, and a plurality of field oxide layers and crossing the plurality of field oxide layers are formed on the plurality of crystal squares. Multiple polysilicon gate lines above; The bottom layer includes a thermal oxide layer and a patterned first linear polysilicon layer: The thermal oxide layer is located on a part of the substrate in the test area, and the thickness of the thermal oxide layer is the same as the thickness of the plurality of oxide layers, and another part of the substrate in the test area is called a low-level area ; The first linear polysilicon layer has a first test pattern, and the first linear polysilicon layer is located on the thermal oxide layer; The key layer is a second linear polysilicon layer with a second test pattern, and the second linear polysilicon layer is located on the substrate in the lower region; wherein The thickness of the first linear polysilicon layer is the same as that of the second linear polysilicon layer, and the plurality of polysilicon gate lines, the first test pattern and the second test pattern are respectively formed by a square photomask with a linear pattern. A pattern, a first test photomask pattern and a second test photomask pattern are obtained, and the plurality of photomask patterns all have the same line pattern width. 9. The structure of the critical dimension test strip as claimed in claim 8, wherein in the pattern of the plurality of polysilicon gate lines, the first test pattern and the second test pattern, it is possible to distinguish the density of the line pattern A first type area and a second type area of different degrees, the first type area has a first pattern width-to-distance ratio on average, and the second type area has a second pattern width-to-distance ratio on average. 10 . The gate line critical dimension test strip structure as claimed in claim 9 , wherein the width-to-distance ratio of the first pattern is 1:4.0, and the width-to-distance ratio of the second pattern is 1:2.0. 11. A method for monitoring critical dimension deviations, applicable to a substrate on which a plurality of wafers and a test area between the plurality of wafers are distinguished, the method comprising the following steps: forming a bottom layer on a part of the substrate in the test area, and forming a patterned bottom layer on the substrate in each of the plurality of wafer cubes at the same time, the material and thickness of the patterned bottom layer and the bottom layer are the same, And another part of the substrate in the test area is called a lower area; A patterned key material layer is formed on the plurality of crystal squares and the test area, the thickness of the key material layer is the same everywhere, wherein each of the plurality of crystal squares, the bottom layer in the test area and the In the key material layer above the low position area, there are respectively a crystal square pattern, a first test pattern and a second test pattern, which respectively consist of a crystal square photomask pattern, a first test photomask pattern and a obtained from the second test photomask pattern, the plurality of photomask patterns have the same pattern type, and all have the same pattern width; and The CDs of the patterns in the first test pattern and the second test pattern are respectively measured and compared to obtain a deviation value of the CDs of the patterns in the crystal square pattern. 12. The method for detecting critical dimension deviation as claimed in claim 11, wherein the crystal square pattern is a contact window opening pattern, then the method comprises the following steps: Forming a plurality of field oxide layers on the substrate in the plurality of crystal squares, and simultaneously forming a thermal oxide layer on a part of the substrate in the test area, the thickness of the thermal oxide layer is the same as that of the plurality of field oxide layers The same thickness, and another part of the substrate in the test area is called a low-lying area; forming a plurality of polysilicon gate lines on the substrate in the plurality of crystal squares, and forming a polysilicon layer on the thermal oxide layer at the same time, wherein the plurality of polysilicon gate lines cross over the plurality of field oxide layers, and The thickness of the polysilicon layer is the same as the thickness of the plurality of polysilicon gate lines; forming a patterned insulating layer on the plurality of crystal squares and the test area, the thickness of the insulating layer is the same everywhere, wherein the polysilicon layer and the low-level area in the plurality of crystal squares, the test area In the upper insulating layer, there are respectively a chip pattern, a first test pattern and a second test pattern in the contact window opening type, which are composed of a chip photomask pattern, a first test photomask pattern and A second test photomask pattern is obtained, and the plurality of photomask patterns all have the same pattern width; and The critical dimensions of the contact window openings in the first test pattern and the second test pattern are respectively measured and compared to obtain a deviation value of the critical dimension of the contact window openings in the chip pattern. 13. The method for monitoring critical dimension deviation as claimed in claim 11, wherein the crystal square pattern is a gate line pattern, then the method comprises the following steps: Forming a plurality of field oxide layers on the substrate in the plurality of crystal squares, and simultaneously forming a thermal oxide layer on a part of the substrate in the test area, the thickness of the thermal oxide layer is the same as that of the plurality of field oxide layers The same thickness, and another part of the substrate in the test area is called a low-lying area; forming a plurality of polysilicon gate lines on the plurality of crystal squares, simultaneously forming a patterned first linear polysilicon layer on the thermal oxide layer, and simultaneously forming a patterned second linear polysilicon layer on the On the substrate in the lower region, wherein the plurality of polysilicon gate lines cross over the plurality of field oxide layers, the first linear polysilicon layer has a first test pattern, and the second linear polysilicon layer has a second test pattern, and the plurality of polysilicon gate lines, the first test pattern and the second test pattern are respectively composed of a crystal square photomask pattern with a line pattern, a first test photomask pattern and a second test pattern obtained by testing photomask patterns, the plurality of photomask patterns all having the same line pattern width; and The critical dimensions of the first test pattern and the second test pattern are respectively measured and compared to obtain the deviation value of the critical dimensions of the plurality of polysilicon gate lines. 14. A method for manufacturing critical dimension test strips, suitable for a substrate, on which a plurality of crystal squares and a test area between the plurality of crystal squares are distinguished, the method comprising the following steps: A bottom layer is formed on a part of the substrate in the test area and a part of the substrate in each of the plurality of wafers, and the substrate other than the bottom layer in the test area is called a lower area ; forming a conformal critical material layer over the plurality of die squares and the test area; Exposure is performed by using a photomask having a chip photomask pattern, a first test photomask pattern and a second test photomask pattern, so as to respectively expose the plurality of crystal squares, the bottom layer and the bottom layer in the test area A crystal square pattern, a first test pattern and a second test pattern are formed in the key material layer above the low position region, wherein the crystal square photomask pattern, the first test photomask pattern and a second test pattern The pattern types of the photomask patterns are all the same, and all have the same pattern width. 15. The method of manufacturing a critical dimension test strip as claimed in claim 14, wherein the critical material layer is an insulating layer, and the first pattern is a pattern of contact openings or via holes. 16. The method of manufacturing a critical dimension test strip as claimed in claim 14, wherein the critical material layer is a polysilicon layer, and the first pattern is a pattern of a gate line or a conductive line. 17. The manufacturing method of critical dimension test strips as claimed in claim 14, wherein a first type with different pattern density can be distinguished in the chip pattern, the first test pattern and the second test pattern. and a second type of area, the first type of area has a first pattern width-to-distance ratio on average, and the second type of area has a second pattern width-to-distance ratio on average. 18. The method of manufacturing a critical dimension test strip as claimed in claim 17, wherein the critical material layer is an insulating layer, and the first pattern is a pattern of contact openings or via holes. 19. The method of manufacturing a critical dimension test strip as claimed in claim 17, wherein the critical material layer is a polysilicon layer, and the first pattern is a pattern of a gate line or a conductive line. 20. A method of manufacturing a contact window opening critical dimension test strip, which is suitable for a substrate, on which a plurality of crystal squares and a test area between the plurality of crystal squares are distinguished, and the method comprises the following steps: forming a patterned field oxide layer on a portion of the substrate in each of the plurality of crystal squares, and simultaneously forming a thermal oxide layer on a portion of the substrate in the test area, and in the test area The substrate outside the thermal oxide layer is called a lower region; forming a plurality of polysilicon gate lines on the plurality of wafers, the plurality of polysilicon gate lines spanning over the plurality of field oxide layers, and simultaneously forming a polysilicon layer on the thermal oxide layer in the test area; forming an insulating layer conformally over the plurality of die squares and the test area; and Exposure is performed using a photomask having a wafer photomask pattern, a first test photomask pattern, and a second test photomask pattern to respectively expose on the plurality of wafer cubes, the polysilicon layer, and the lower region In the insulating layer above, a crystal square pattern, a first test pattern and a second test pattern are formed, wherein the plurality of photomask patterns are all contact window opening patterns, and all have the same pattern width . 21. The manufacturing method of contact window opening critical dimension test strip as claimed in claim 20, wherein the degree of density of contact window openings can be further distinguished in the crystal square pattern, the first test pattern and the second test pattern A first type of region and a second type of region are different, the first type of region has a first contact window opening width-to-distance ratio on average, and the second type of area has a second contact window opening width-to-distance ratio on average. 22 . The method for manufacturing the contact opening critical dimension test strip as claimed in claim 21 , wherein the width-to-distance ratio of the first contact opening is 1:3, and the width-to-distance ratio of the second contact opening is 1:1.5.

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