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CN116819277A - SIP integrated circuit reliability test batch monitoring system and testing method thereof - Google Patents

SIP integrated circuit reliability test batch monitoring system and testing method thereof Download PDF

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Publication number
CN116819277A
CN116819277A CN202310689793.1A CN202310689793A CN116819277A CN 116819277 A CN116819277 A CN 116819277A CN 202310689793 A CN202310689793 A CN 202310689793A CN 116819277 A CN116819277 A CN 116819277A
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China
Prior art keywords
control module
test
power supply
dut
gpib
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CN202310689793.1A
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Chinese (zh)
Inventor
陈相洪
史凡萍
吉星宇
黄晓宗
杨晓强
彭伟
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CETC 24 Research Institute
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CETC 24 Research Institute
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Priority to CN202310689793.1A priority Critical patent/CN116819277A/en
Publication of CN116819277A publication Critical patent/CN116819277A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
    • G01M7/00—Vibration-testing of structures; Shock-testing of structures
    • G01M7/02—Vibration-testing by means of a shake table
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2881—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to environmental aspects other than temperature, e.g. humidity or vibrations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

The invention relates to the technical field of SIP integrated circuit reliability test batch monitoring, in particular to a SIP integrated circuit reliability test batch monitoring system and a test method thereof, wherein the system comprises a detection box, a test motherboard GPIB program control module, a PC upper computer and a power supply, wherein the detection box comprises a pair of tooling carrier plates, and each tooling carrier plate is provided with a plurality of SIP integrated circuits and carrier plate components; the test motherboard comprises an FPGA signal control module, a multi-channel signal switching and power supply control module; the PC upper computer comprises an RS232 control module, a JTAG control module, a GPIB control module and an IO control module; the monitoring system provided by the invention has the on-line programmable multifunctional real-time monitoring capability and the 32-group multi-core monitoring capability of the SIP integrated circuit reliability test, can effectively improve the test precision and the test efficiency of the SIP integrated circuit reliability test, and reduces the production cost.

Description

SIP integrated circuit reliability test batch monitoring system and testing method thereof
Technical Field
The invention relates to the technical field of SIP integrated circuit reliability test batch monitoring, in particular to a SIP integrated circuit reliability test batch monitoring system and a testing method thereof.
Background
The adoption of new technologies in the national army semiconductor industry and the general institutes of China has put new demands on the technology of chip supply units. With the miniaturization, localization, multifunction and high reliability device demands of the general institutes, SIP (system in package) products are rapidly developed, and some advanced circuit users are required to manufacture SIP functional modules comprising devices such as power supply, operational amplifier, ADDA, SRAM, FLASH, MCU and the like. According to relevant standard, the module item needs to be monitored on line with full parameters in reliability screening such as vibration, temperature circulation, aging and the like so as to ensure that the module can keep extremely high reliability when dealing with various severe environments. Therefore, in the mass production of the SIP, the convenient, stable, reliable and efficient full-parameter on-line monitoring is realized, and meanwhile, the number of circuits monitored in parallel on line in a single round is increased, so that the efficient mass production of the circuits can be realized.
The domestic whole machine unit and the micro-module production unit usually only monitor important parameters such as voltage, current, functions and the like in real time when carrying out environmental experiments, and people must watch in the experimental process. The number of on-line monitoring circuits which are simultaneously carried out is usually small, and a large-scale full-automatic parallel on-line monitoring scheme of a large-scale high-complexity circuit is not currently available.
With the rapid increase of market demands of SIP integrated circuit devices and the rapid increase of demands of various SIP integrated circuits for screening indexes, the manufacturing and production of SIP integrated circuits must also undergo accurate reliability tests and screening before leaving the factory. The SIP integrated circuit is widely used due to its features of multiple functions and strong system structure, but the existing SIP integrated circuit reliability screening evaluation and mass production test have become one of the main bottlenecks restricting the development of the SIP integrated circuit in terms of screening quantity and efficiency. The reliability test screening of the SIP integrated circuit needs to provide a more complex and stable test environment and can accurately monitor on line, and the test is also provided for the batch monitoring production of the reliability test of the SIP integrated circuit.
Disclosure of Invention
In order to perform reliability test batch monitoring on an SIP integrated circuit while being stable and reliable, the invention provides a system and a method for monitoring the reliability test batch of the SIP integrated circuit, wherein the system comprises a detection box, a test motherboard GPIB program control module, a PC upper computer and a power supply, the detection box comprises a pair of tool carrier boards, and each tool carrier board is provided with a plurality of SIP integrated circuits and carrier board assemblies; the test motherboard comprises an FPGA signal control module, a multi-channel signal switching and power supply control module; the PC upper computer comprises an RS232 control module, a JTAG control module, a GPIB control module and an IO control module; wherein:
The detection box is used for providing a test environment for the tool carrier plate and adopting RS232 program control to detect test parameters of the detection box;
the test mother board is used for carrying out parallel input and output of a plurality of signals and power supply switching on different DUTs, namely when different DUT boards work, the FPGA signal control module and the multi-channel signal switching are used for respectively controlling and switching, and the power supply control module is used for supplying power to the tool carrier board;
the RS232 control module is used for controlling parameters of the detection box through an RS232 protocol and displaying the read-back temperature, the read-back impact frequency, the read-back vibration frequency and the read-back direction through an upper computer;
the JTAG control module is communicated with the FPGA signal control module through a JTAG protocol, and the acquired FPGA digital signals are simulated and displayed in real time by the Chipscop;
the GPIB control module is used for storing the data tested by the GPIB program control module through a GPIB interface protocol program control detection instrument and controlling a power supply through the GPIB interface protocol program control module;
and the IO control module controls the analog switch ADG732BSUZ to conduct input and output digital signals through an IO interface protocol, and the program-controlled power supply control module provides high and low levels for ULN2003 driving to realize switching of the RT424012 relay and provides a power supply and a voltage reference for the DUT.
The invention also provides a testing method of the SIP integrated circuit reliability test batch monitoring system, which specifically comprises the following steps:
step one: the method for building the reliability test batch monitoring system specifically comprises the following steps:
the 32 groups of SIP integrated circuits to be tested for reliability are respectively fixed in a temperature circulation box or an aging box or a vibrating table through an overload board;
the bus wire with 34 pins is connected to the test motherboard and is used for connecting the multichannel signal switching and power supply control module;
connecting a power line on the test motherboard to a corresponding channel of a power supply, and connecting an output signal to an oscilloscope in the GPIB program control module through a coaxial line;
connecting an output signal to a port corresponding to a universal meter in the GPIB program control module, and connecting a temperature tracking box or an aging box or a vibrating table with an RS232 control module of a PC upper computer;
connecting the FPGA signal control module with a JTAG control module of the PC upper computer, and connecting the GPIB program control module, the power supply and the GPIB control module of the PC upper computer;
connecting the multichannel signal switching module and the power supply control module with the IO control module of the PC upper computer through the 50-pin IO card to complete the construction of a batch monitoring system;
step two: configuring an FPGA signal control module through JTAG programming, programming a temperature tracking box or an aging box or a vibrating table through an RS232 control module, setting the corresponding box body environment temperature and impact frequency, vibration frequency and direction, and displaying by an upper computer; the GPIB control module is used for respectively performing program control according to different addresses set by instruments such as a universal meter, an oscilloscope and a frequency spectrum, and simultaneously, a program control power supply is used for setting corresponding power supply voltage and limiting current; the written Verilog HDL program is programmed to the FPGA through the JTAG control module, and is used for generating differential and high-speed signals, simulating the acquired FPGA digital signals and displaying the acquired FPGA digital signals in real time by the upper computer;
Step three: when a certain DUT needing to be subjected to reliability test is selected, 14 analog switches ADG732BSUZ with 32 selected 1 are required to be controlled to conduct input and output digital signals on the selected DUT through an IO interface protocol, and meanwhile, a power supply control module is operated to provide control voltages with high level 5V and low level 0V for ULN2003 to realize switching of an RT424012 relay, so that power supply and voltage reference are provided for different DUTs;
step four: the method comprises the steps of receiving monitoring instructions, respectively switching and starting specified DUT devices to work normally, entering a circulation and waiting for the arrival of the monitoring instructions, starting a monitoring mode if the monitoring instructions arrive, inputting digital signals and time sequences into the specified DUT devices, and powering up the DUT devices to enable the DUT devices to work normally;
step five: and after receiving the monitoring instruction, the program control GPIB module performs parameter monitoring according to the instruction content program control multimeter, oscilloscope, frequency spectrum and other instruments, and then uploads the read-back result to the PC upper computer in real time through the GPIB protocol, the PC upper computer records the test result and corresponding data of the DUT, and the steps one to four are repeated until all DUTs are tested.
The invention has the on-line monitoring capability and the multi-core test capability of the SIP integrated circuit, can effectively improve the production efficiency of the SIP integrated circuit and reduce the production cost. Compared with the prior art, the invention has the following beneficial effects:
1. the SIP integrated circuit reliability test batch monitoring system has the characteristics of low cost, simple and convenient operation, multiple test functions, high production efficiency, lower screening cost and the like;
2. the invention adopts a mode of cooperation of time-sharing power supply and software and hardware. By adopting a time-sharing power supply mode, under the condition that the single SIP current exceeds 2A, up to 32 SIP integrated circuits can be powered by using a single programmable power supply. By adopting a software and hardware cooperative mode, the system has the characteristics of high integration level and high automation.
3. The invention realizes programmable multifunctional real-time monitoring. The purpose of high flexibility of function test is achieved by utilizing the characteristic of reprogramming configuration of the FPGA. The digital function test part of the monitoring system can be flexibly changed according to the change of the requirements and definitions of the user products, so that the secondary development of hardware is avoided, and the iteration speed of the products is increased.
4. The invention innovatively realizes multi-platform adaptation application. The system can be suitable for vibrating tables, temperature circulation boxes and aging boxes of various models, and has short installation time and high operation reliability. The method not only works well on the existing environment test platform, but also has good effect in the scheme of recommending SIP integrated circuit test to the whole machine user.
5. The invention reduces the cost. The PCB is adopted to manufacture the test motherboard, and the electronic devices are all conventional circuits, so that the maintenance cost is low. The invention uses the conventional equipment such as the temperature-circulating aging box, the universal meter, the oscilloscope and the like, the use cost of the equipment is obviously reduced, and the equipment can be popularized and used.
Drawings
Fig. 1 is a block diagram of a batch monitoring system for a reliability test of a SIP integrated circuit according to embodiment 1 of the present invention;
fig. 2 is a block diagram of a vibration table control system of a batch monitoring system for a reliability test of a SIP integrated circuit according to embodiment 1 of the present invention;
fig. 3 is a block diagram of a temperature cycle control system of a batch monitoring system for a reliability test of a SIP integrated circuit according to embodiment 1 of the present invention;
fig. 4 is a tooling carrier of the SIP integrated circuit reliability test batch monitoring system provided in embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a test motherboard of the SIP integrated circuit reliability test batch monitoring system provided in embodiment 1 of the present invention;
fig. 6 is a control schematic diagram of a test motherboard device of the SIP integrated circuit reliability test batch monitoring system provided in embodiment 1 of the present invention;
fig. 7 is a schematic diagram of a control end of an upper computer of the SIP integrated circuit reliability test batch monitoring system provided in embodiment 1 of the present invention;
Fig. 8 is a test flow chart of the SIP integrated circuit reliability test batch monitoring system provided in embodiment 1 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a batch monitoring system and a testing method for a reliability test of a Session Initiation Protocol (SIP) integrated circuit. The temperature tracking box or aging box or vibrating table comprises 32 groups of work loading plates and a plurality of SIP integrated circuits and carrier plate assemblies which are arranged on the work loading plates; the test motherboard comprises an FPGA signal control module, a multichannel signal switching and power supply control module, and the PC upper computer comprises an RS232 control module, a JTAG control module, a GPIB control module and an IO control module, wherein:
The temperature circulation box, the aging box or the vibration table is used for providing test environments for 32 groups of tool carrier plates, and adopting RS232 to carry out program control test on temperature, vibration frequency and the like. And the 32-component loading plate is used for fixedly placing the SIP integrated circuit to be tested in the temperature circulation box or the aging box or the vibrating table device through the loading plate. The carrier plate adopts duralumin for processing design, and the tooling carrier plate capable of fixing the DUT is designed according to the outline dimension of the SIP, so that the DUT can stably work in a reliability test environment.
And the test motherboard is used for carrying out parallel input and output and power supply switching of a plurality of signals for different DUTs. When different DUTs work, the operation of the DUTs is realized by controlling the multi-channel signal switching and power supply control module respectively, so that the communication and data reading of each DUT can be realized, and the reading and writing operation of the register can be carried out.
The RS232 control module is used for carrying out temperature program control on the temperature tracking box or the aging box or the vibrating table through an RS232 protocol, and displaying the read-back temperature, the impact frequency, the vibration frequency and the direction by an upper computer;
the JTAG control module is communicated with the FPGA signal control module through a JTAG protocol, and the acquired FPGA digital signals are simulated and displayed in real time by the Chipscop;
The GPIB control module is used for programming the universal meter, the oscilloscope, the frequency spectrum and other instruments through the GPIB interface protocol, storing the data tested by the GPIB programming module, and programming the power supply through the GPIB interface protocol.
The IO control module controls the analog switch ADG732BSUZ to conduct input and output digital signals through an IO interface protocol, and meanwhile, the power supply control module can be operated to provide high and low levels for ULN2003 driving to realize switching of the RT424012 relay, so that a power supply and a voltage reference are respectively provided for the DUT.
Example 1
As shown in FIG. 1, in order to achieve the above purpose, a batch monitoring system for reliability test of SIP integrated circuits comprises a power supply, a temperature tracking box or aging box or vibration table, a 32-component loading board, a test motherboard, a GPIB program control module and a PC host computer. Wherein:
1. the SIP integrated circuit reliability test batch monitoring system is characterized by comprising a power supply, a temperature-tracking box or aging box or vibrating table, a test mother board, a GPIB program control module and a PC upper computer, wherein the temperature-tracking box or aging box or vibrating table comprises 32 groups of work loading boards, and a plurality of SIP integrated circuits and carrier board assemblies which are arranged on the work loading boards; the test motherboard comprises an FPGA signal control module, a multichannel signal switching and power supply control module, and the PC upper computer comprises an RS232 control module, a JTAG control module, a GPIB control module and an IO control module.
(1) The power supply is used for providing power for the test motherboard and the 32-group tool carrier board, and adopts GPIB to carry out program control voltage and current limiting, the program control power supply adopts IT6332B type multifunctional power supply, the maximum output voltage is 30V, and the maximum output current is 6A, so that the requirement of a measurement system is met;
(2) the temperature circulation box, the aging box or the vibration table is used for providing test environments for 32 groups of tool carrier plates, and adopting RS232 to carry out program control test on temperature, vibration frequency and the like. The temperature circulation box selects star topology temperature circulation test box AT-408, designs and meets the GB international technical standard GB/T10592-2008 technical conditions of high and low temperature test boxes, the temperature range is-70 ℃ to +150 ℃, the temperature fluctuation degree is +/-0.5 ℃, RS232 is selected as a remote control port, and the execution program codes, the segments, the residual time and the circulation times can be displayed, and the running time is displayed. The aging box is a CLM-GD (J) W-500 high-temperature thermal aging experimental box, and the design meets the national standards of GB/T3512-01 UL-1581 and the like. Temperature range-70-300 ℃, temperature control is carried out by using a platinum resistor PT100, and temperature fluctuation degree is as follows: 0.5%. The vibration table selects EDM-3200 of a hundred million constant electric vibration test system, is designed to meet the GB4857-GJB150A vibration test standard, has the test functions of sine, random, impact, mixed modes and the like, and is a full-digital power amplifier, and a computer can be used for vibration control.
(3) And the 32-component loading plate is used for placing the SIP integrated circuit to be tested, and the SIP integrated circuit to be tested is fixedly placed in the temperature circulation box or the aging box or the vibrating table device through the loading plate. Wherein the 32 groups of work load boards respectively comprise 32 groups of SIP integrated circuits (DUTs) and 32 groups of load boards. Characterized by comprising the following steps:
the DUT, which is made into a SIP functional module containing power supply, op amp, ADDA, SRAM, FLASH, MCU and other devices, is firmly placed in a temperature tracking box or aging box or a vibrating table in a manner of being physically fixed with a carrier plate so as to be capable of performing reliability tests. The DUT is connected with the test mother board by using two 34-pin flat cables in a switching joint mode, so that the configuration, reading and writing of registers, the configuration of differential high-speed signals and the supply of power supply are realized, and meanwhile, the voltage and current and signals of the DUT can be output.
The carrier plate adopts duralumin for processing design, and the tooling carrier plate capable of fixing the DUT is designed according to the outline dimension of the SIP, so that the DUT can work stably in a reliability test environment.
The tooling comprises a carrier plate, a positioning bolt and a positioning pin, wherein the carrier plate comprises a vertical plate and a horizontal plate, the horizontal plate is arranged between the two vertical plates, the horizontal plate is vertically arranged at the middle position of the two vertical plates, the top of the vertical plate is provided with a bolt hole, the bottom equipment is provided with a screw hole, the horizontal plate is provided with only a pin hole, and the carrier plate is fixed in the temperature circulation box through the screw hole; the positioning pin is a rectangular block, two sides of the bottom of the positioning pin outwards extend to form a sheet structure, a pin hole is formed in the sheet structure, the pin hole is matched with the pin hole in the horizontal plate, and the positioning pin is fixedly arranged on the horizontal plate through the pin hole; the positioning bolt comprises two rectangular blocks and a rectangular sheet, wherein the two rectangular blocks are connected through the holding sheet, the rectangular blocks are provided with bolt holes matched with the bolt holes on the vertical plates, and the two rectangular blocks of the positioning bolt are respectively and fixedly arranged on the two vertical plates through the bolt holes. In this embodiment, the SIP integrated circuit is to be placed on the carrier plate, and the carrier plate is fixed on the temperature-tracking box, the vibrating table and the aging box through the screw holes, and the SIP integrated circuit is fixed by selecting the positioning pins and the positioning pins, and the positioning pins and the carrier plate are fixed through the corresponding pin holes. The carrier plate, the positioning bolt and the positioning pin are all machined by adopting hard aluminum, and through deburring, sand blasting and natural-color oxidation treatment, the vibration test and the high-low temperature cycle test can be resisted, and meanwhile, the heat dissipation effect on the power type SIP integrated circuit can be achieved.
(4) And the test motherboard is used for carrying out parallel input and output and power supply switching of a plurality of signals for different DUTs. When different DUTs work, the operation of the DUTs is realized by controlling the multi-channel signal switching and power supply control module respectively, so that the communication and data reading of each DUT can be realized, and the reading and writing operation of the register can be carried out. Characterized by comprising the following steps:
the FPGA signal control module selects XC6SLX9-2TQG144I type of Xilinx as a signal control chip. By utilizing the characteristic of the FPGA of reprogramming configuration, a high-speed differential signal and a logic signal required by the DUT can be programmed and generated, and then the generated logic signal is transmitted to the multi-channel signal switching module, so that all DUTs can be shared at the same time, and the purpose of high functional test flexibility is achieved.
The multi-channel signal switching is used for controlling and conducting the parallel signals input to the DUT and the signals output by the DUT, 14 analog switches ADG732BSUZ with the number of 32 being 1 are selected for switching the signals, so that the conduction of 14 x 32 digital signals with the number of high-speed, single-ended and differential inputs and outputs to a single DUT can be realized, and the analog switches are controlled through the IO control module.
A power control module for providing different power and voltage references for the DUT. The LT1764A fast transient response, low noise, LDO voltage regulator and the LT1763CS8 low noise LDO micropower voltage regulator are selected as the devices for power supply and voltage reference generation. LT1764A can provide 3A's output current and a 340mV differential voltage at maximum, and the operating quiescent current is 1mA, and output voltage range is 1.21V to 20V, and this device can provide 1.5V, 1.8V, 2.5V, 3.3V, 5V's fixed output voltage to can be used as a section of adjustable device that has 1.21V reference voltage, can satisfy the voltage and the power demand of different DUTs completely. Here, RT424012 is selected as a switching relay for power supply and voltage, and the two channels of the relay share a current which can pass through 8A, and the control voltage is 12V. The ULN2003 is selected to drive the relays, and the maximum driving current of each unit can reach 500mA, so that 7 relays can be controlled simultaneously.
(5) The GPIB program control module comprises a universal meter capable of performing GPIB program control, an oscilloscope, a frequency spectrum and other instruments, wherein the universal meter is 34410A type, the oscilloscope is DSO6102A type, and the frequency spectrum is Rode and Schvalz FSV3013 type.
(6) And the PC upper computer is used for storing the data after the GPIB program control module is tested, and controlling and communicating the power supply, the temperature-tracking box or the aging box or the vibrating table, the universal meter, the oscillograph, the frequency spectrum and other instruments and the test mother board. Characterized by comprising the following steps:
The RS232 control module is used for carrying out temperature program control on the temperature tracking box or the aging box or the vibrating table through an RS232 protocol, and displaying the read-back temperature, the impact frequency, the vibration frequency and the direction by an upper computer;
the JTAG control module is communicated with the FPGA signal control module through a JTAG protocol, the well-written Verilog HDL program is programmed into the FPGA, and then the acquired FPGA digital signals are simulated through a Chipscop and displayed in real time by an upper computer;
and the GPIB control module is used for programming instruments such as a multimeter, an oscilloscope, a frequency spectrum and the like through a GPIB interface protocol and storing data after the GPIB programming module is tested. Meanwhile, the power supply can be programmed through the GPIB interface protocol, and different voltages can be generated through programming, so that the test motherboard and the 32-group work loading board can be respectively powered.
The IO control module controls 14 analog switches ADG732BSUZ of 32 optional 1 to conduct input and output digital signals through an IO interface protocol, and meanwhile, the power supply control module can be operated to provide high-level 5V and low-level 0V control voltage for ULN2003 to realize switching of the RT424012 relay, so that power and voltage references are respectively provided for the DUT.
Example 2
In order to achieve the above object, the present invention also provides a control system block diagram of a vibration table of a batch monitoring system for testing reliability of SIP integrated circuits, as shown in fig. 2. Vibration tables, also known as vibration exciters or vibration generators, vibration control systems simulate the various environments encountered by a product during its manufacturing, assembly, transportation, and use execution stages for identifying the ability of the product to withstand environmental vibrations. It is a device that uses electric, electro-hydraulic, piezoelectric or other principles to obtain mechanical vibrations. The principle is that an excitation signal is input into a coil placed in a magnetic field to drive a workbench connected with the coil, and the vibrating table can be used for calibrating an accelerometer.
The vibration table control system belongs to a typical closed-loop feedback control system, and the feedback quantity is obtained by sampling sensors involved in control, and comprises a PC upper computer, a vibration table, a vibration acceleration sensor, a signal modulator, a vibration controller, a power amplifier and the like. The SIP integrated circuit which needs to be monitored in batches of reliability is fixed on the vibration table through the loading board, the vibration table is used for providing a reliability test environment for the DUT, and the vibration table has test functions of sine, random, impact, mixed modes and the like, and can be controlled in a vibration mode through RS232 communication by using a PC upper computer.
The vibration table senses vibration frequency through the vibration acceleration sensor, then signals are output to the vibration controller through the signal modulator, the vibration controller equalizes low-power driving electric signals according to the requirements of a control spectrum and then sends the low-power driving electric signals to the power amplifier, the power amplifier amplifies the low-power driving electric signals and then provides the low-power driving electric signals to the driving coil of the vibration table, the vibration acceleration sensor senses vibration frequency and in turn pushes the signal modulator to transmit the vibration signals to the vibration controller, and the vibration controller corrects the electric signals in real time and then sends the electric signals to the power amplifier, so that closed-loop control is formed. The cooling device is arranged in the vibrating table to cool (air-cool and water-cool) the vibrating table, so that heat in the vibrating table is discharged in time.
Example 3
In order to achieve the above objective, the present invention also provides a block diagram of a temperature cycle control system of a batch monitoring system for testing reliability of SIP integrated circuits, as shown in fig. 3. The temperature circulation control system changes external environmental stress by applying temperature acceleration techniques (when the product is circulated within upper and lower limit extreme temperatures) under the design strength limit, so that thermal stress and strain are generated in the product, and flaws existing in the product are enabled to emerge through the acceleration stress, thereby avoiding unnecessary loss caused by failure when the product is subjected to the test of the environmental stress in the use process, and achieving the standard of a reliability test.
The temperature circulation control system comprises a PC upper computer, a temperature controller, a driving circuit, a power conversion circuit, a temperature sensor, a detection head, a Peltier, a DUT tool carrier plate and the like. The PC upper computer gives a temperature control curve to a temperature controller through RS232, the temperature controller transmits the real-time temperature of the box body to the temperature controller through digital-to-analog (A/D) conversion by a temperature sensor (platinum resistor PT 100) in the box body, the temperature controller comprehensively processes and then sends a control signal to a driving circuit, and the driving circuit further controls a power conversion circuit to control Peltier (semiconductor electronic refrigeration is also called thermoelectric refrigeration or thermoelectric refrigeration) in the temperature box, so that the Peltier effect is utilized. The DUT tool carrier plate platform is used for placing a SIP integrated circuit platform carrier for a temperature cycle reliability test.
Example 4
In order to achieve the above objective, as shown in fig. 4, the present invention further provides a tooling carrier of the SIP integrated circuit reliability test batch monitoring system, where the carrier is used to provide vibration, temperature cycle and burn-in test carriers for 32 groups of DUTs, so as to fix and stabilize DUTs. The tool mainly comprises a three-part carrier plate, a positioning bolt and a positioning pin, all adopts hard aluminum for machining, can resist vibration test and high-low temperature cycle test through deburring, sand blasting and natural-color oxidation treatment, and can play a role in heat dissipation on a power type SIP integrated circuit. The SIP integrated circuit is placed on the carrier plate, the SIP integrated circuit is fixed by selecting a positioning bolt and a positioning pin, the positioning pin and the carrier plate are fixed through corresponding pin holes, and the positioning bolt and the carrier plate are fixed through corresponding bolt holes.
Example 5
In order to achieve the above object, the present invention also provides a test motherboard of a SIP integrated circuit reliability test batch monitoring system, as shown in fig. 5. The test motherboard is 10 layers of PCB boards (including 2 power layers, 2 layers of stratum and other signal layers). 32 flat cables are placed in the middle of the overall layout of the test motherboard for connection communication with the DUT. 14 analog switches ADG732BSUZ of 32-1 are placed between the two rows of flat cables and are respectively used for leading different signals to corresponding flat cable ports through the analog switches, so that the layout has the advantage that the signals can run the shortest thread, the quality of high-speed signals can be ensured, and meanwhile, the interference between the signals can be avoided.
The FPGA signal control module selects XC6SLX9-2TQG144I type of xilinx as a signal control chip, and further comprises a JTAG interface, a Flash circuit, a crystal oscillator and an LDO. The JTAG interface is used for communicating with a JTAG control module of the upper computer; the Flash circuit adopts M25P16 type and is used for storing and solidifying FPGA programs; the crystal oscillator adopts 50M signal output for providing a clock for the FPGA; the LDO adopts ASM1117-1.2 and ASM1117-3.3, and can provide core voltages of 1.2V and 3.3V for the FPGA. The FPGA signal control module is placed at the lower end of the whole test motherboard and is used for generating high-speed differential signals and logic signals required by the DUT, and the layout of the FPGA signal control module in the place can lead the wiring of the whole board to be more reasonable, and simultaneously, the centralized control and the processing of signals are convenient.
The IO control card is connected with the IO control module of the upper computer and is placed at the lowest end of the whole test motherboard, so that the IO port flat cable can be conveniently plugged and pulled out. The IO control card respectively carries out switching control on signals of 14 analog switches ADG732BSUZ, and simultaneously controls the on and off of 8 RT424012 relays and 1 output control relay through 2 ULN2003 drivers.
A power control module for providing different power and voltage references for the DUT. 8 LDO regulators LT1764A and 1 LT1763CS8 low noise LDO micropower regulators are selected as the power supply and voltage reference of the DUT to generate adjustable devices. Switching of the DUT supply voltage is performed by a high voltage, high current relay of RT 424012. The system also adopts 5 DUT power supply sockets which respectively comprise 4 DUT power supply sockets and are respectively used for providing high-voltage and low-voltage power supply selection for 1-32 DUTs, so that the external unified control on the power-on of a single DUT is facilitated; and the 1 ADG732BSUZ power supply socket is used for uniformly powering up the 14 ADG732BSUZ power supply sockets. 4 DUT power supply sockets, 8 LT1764A and 8 RT424012 are respectively placed around the test motherboard, wherein LT1764A and RT424012 are placed close to each other, and can provide power supply voltage for 4 nearby flat cable ports, so that less wiring is avoided, the quality of the power supply voltage is ensured, and the DUT is prevented from generating too large overshoot.
The signal output interface is characterized in that two BNC plugs are arranged on the uppermost surface of the testing motherboard and used for being respectively connected with an oscilloscope, a universal meter, a frequency spectrum and other instruments in the GPIB program control module, and meanwhile, a relay is adopted for switching output signals. The signal output module is arranged at the top to generate interference with the input FPGA signal module. And routing and overall layout are also facilitated.
Example 6
In order to achieve the above objective, the present invention also provides a test motherboard device control schematic diagram of the SIP integrated circuit reliability test batch monitoring system, as shown in fig. 6. The test motherboard adopts a Flash circuit M25P16, the LDO adopts ASM1117-1.2 and ASM1117-3.3 to respectively provide a control program, a 1.2V kernel reference and a 3.3V power supply for the FPGA; the ULN2003 driver controls the RT424012 relay, the LDO regulator LT1764A and 1 LT1763CS8 provide the supply voltage and reference to the DUT through the RT424012 relay; the analog switch ADG732BSUZ switches the input signal of the FPGA and turns on the output signal of the DUT to the BNC interface.
Example 7
As shown in fig. 7, in order to achieve the above objective, the present invention further provides an upper computer control end of the SIP integrated circuit reliability test batch monitoring system. When the reliability test is carried out, the upper computer monitors and tests the reliability test of 32 SIP integrated circuits in batches according to different test items; the interface of the upper computer control end is shown in fig. 7, wherein the block diagram is as follows:
(1) Displaying an input batch, and inputting a production batch number of the SIP integrated circuit to be tested;
(2) displaying database setting, wherein the same number record can be selected from the group consisting of automatic deletion of the same number record, manual deletion of the same number record and reservation of the same number record;
(3) the diagnosis control before display can be used for testing instruments such as a universal meter, an oscilloscope, a frequency spectrum and the like, and detecting parameters such as a power supply, a signal source and the like before power-on. The standard test can test the whole parameters of the sample, so that the connectivity and the complete passage of the whole system are ensured;
(4) the test control is displayed, batch test and stop operations can be selected, and program circulation can be continuously tested by checking the circulation enabling to realize the program circulation of 32 SIP circuits, so that batch on-line monitoring is realized. The waiting time of each circuit interval can be set, and one or a plurality of circuits can be selected for monitoring through the start and the end;
(5) and the RS232 control module is displayed, the vibration table can realize the test functions of emitting sine, random, impact, mixed modes and the like, and the PC upper computer is used for controlling the vibration table through RS232 communication. The temperature control can be carried out on the temperature control box and the aging box through RS232, and the box body temperature is fed back to the upper computer;
(6) The display JTAG control module can realize communication to the FPGA, and SPI transmission or UART transmission is carried out on a register of the SIP integrated circuit through the FPGA;
(7) the display GPIB control module, the program-controlled universal meter and the program-controlled oscilloscope can monitor whether addresses of the universal meter and the oscilloscope can be read or not and rapidly test current, current and waveform parameters of the SIP integrated circuit;
(8) and the display IO control module controls the analog switch to conduct input and output digital signals through an IO interface protocol. "Power supply voltage control" provides power and voltage references to the DUT via the IO interface protocol;
(9) displaying test parameters, wherein the window can display batch test results of 32 SIP integrated full parameters;
and displaying test statistics results, and displaying the test total number, the PASS number, the FALL number and the qualification rate in real time.
Example 8
The embodiment also provides a test method of the SIP integrated circuit reliability test batch monitoring system on the basis of the embodiments 1 to 5. As shown in fig. 8, the test flow chart includes the following steps:
step one: the method comprises the steps of building a reliability test batch monitoring system, and firstly, fixing 32 groups of SIP integrated circuits to be subjected to the reliability test in a temperature circulation box or an aging box or a vibration table through a loading plate. And then connected to the test motherboard through a 34-pin flat cable for connecting the multi-channel signal switching and power supply control module. And connecting the power line on the test motherboard to the corresponding channel of the power supply. And then connecting the output signal to an oscilloscope in the GPIB program-controlled module through a coaxial line, and connecting the output signal to a port corresponding to a universal meter in the GPIB program-controlled module. And then the temperature tracking box or the aging box or the vibrating table is connected with an RS232 control module of the PC upper computer, the FPGA signal control module is connected with a JTAG control module of the PC upper computer, and the GPIB program control module, the power supply and the GPIB control module of the PC upper computer are connected. And connecting the multichannel signal switching module and the power supply control module with the IO control module of the PC upper computer through the 50-pin IO card, and finally completing the construction of the batch monitoring system.
Step two: and (3) initializing the RS232, the GPIB and the like, and configuring the FPGA signal control module through JTAG programming. Program control is carried out on the temperature tracking box or the aging box or the vibrating table through the RS232 control module, and the corresponding box body environment temperature, impact frequency, vibration frequency and direction are set and displayed by an upper computer; the GPIB control module is used for respectively performing program control according to different addresses set by instruments such as a universal meter, an oscilloscope and a frequency spectrum, and simultaneously, a program control power supply is used for setting corresponding power supply voltage and limiting current; and programming the written Verilog HDL program to the FPGA through the JTAG control module, and generating differential and high-speed signals, and simulating the acquired FPGA digital signals and displaying the acquired FPGA digital signals in real time by the upper computer.
Step three: the signals and power supply of the DUT are switched through the IO control module. When a DUT to be tested for reliability is selected, 14 analog switches ADG732BSUZ of 32 choices 1 are required to be controlled to conduct input and output digital signals on the selected DUT through an IO interface protocol, and meanwhile, a power supply control module is operated to provide control voltages of high level 5V and low level 0V for ULN2003 to realize switching of RT424012 relay, so that power and voltage references are provided for different DUTs.
Step four: and receiving the monitoring instructions, and respectively switching and starting the appointed DUT devices to work normally. And entering a loop to wait for the arrival of the monitoring instruction, if the monitoring instruction arrives, namely starting a monitoring mode, inputting a digital signal and a time sequence to a designated DUT, and powering up the DUT to enable the DUT to work normally.
Step five: the program-controlled GPIB module reads the output signal of the DUT and transmits the output signal back to the upper computer. After receiving the monitoring instruction, performing parameter monitoring according to the instruction content program-controlled multimeter, oscilloscope, frequency spectrum and other instruments, uploading the read-back result to the PC upper computer in real time through the GPIB protocol, recording the test result and corresponding data of the DUT by the PC upper computer, and repeating the steps one to four until all DUTs of the DUT are completely tested.
The invention relates to a batch monitoring system for a SIP integrated circuit reliability test. The system comprises a temperature circulation box or an aging box or a vibrating table, a test motherboard, a GPIB program control module, a power supply and a PC upper computer, wherein the temperature circulation box or the aging box or the vibrating table comprises 32 groups of work loading boards and a plurality of SIP integrated circuits and carrier board assemblies which are arranged on the work loading boards; the test motherboard comprises an FPGA signal control module, a multichannel signal switching and power supply control module, and the PC upper computer comprises an RS232 control module, a JTAG control module, a GPIB control module and an IO control module; the invention has the on-line monitoring capability and the multi-core testing capability of the SIP integrated circuit reliability test, can effectively improve the testing precision of the SIP integrated circuit reliability test, improve the testing efficiency and reduce the production cost.
While the foregoing is directed to embodiments, aspects and advantages of the present invention, other and further details of the invention may be had by the foregoing description, it will be understood that the foregoing embodiments are merely exemplary of the invention, and that any changes, substitutions, alterations, etc. which may be made herein without departing from the spirit and principles of the invention.

Claims (7)

1.一种SIP集成电路可靠性试验批量监测系统，其特征在于，包括检测箱、测试母板GPIB程控模块、PC上位机以及电源，检测箱中包括对个工装载板，每个工装载板上安装有多个SIP集成电路和载板组件；测试母板包括FPGA信号控制模块、多通道信号切换以及供电控制模块；PC上位机包括RS232控制模块、JTAG控制模块、GPIB控制模块以及IO控制模块；其中：1. A SIP integrated circuit reliability test batch monitoring system, which is characterized in that it includes a detection box, a test motherboard GPIB program control module, a PC host computer and a power supply. The detection box includes a pair of individual work loading boards, and each work loading board Multiple SIP integrated circuits and carrier board components are installed on it; the test motherboard includes FPGA signal control module, multi-channel signal switching and power supply control module; the PC host computer includes RS232 control module, JTAG control module, GPIB control module and IO control module ;in: 检测箱，用于为工装载板提供测试环境，采用RS232程控检测箱试验参数；Detection box, used to provide a testing environment for industrial loading boards, using RS232 program-controlled detection box test parameters; 测试母板，用于对各个不同的DUT进行多个信号的并行输入输出和供电切换，即当不同的DUT板进行工作时，利用FPGA信号控制模块、多通道信号切换分别进行控制和切换，供电控制模块用于对工装载板进行供电；The test motherboard is used for parallel input and output of multiple signals and power supply switching for different DUTs. That is, when different DUT boards are working, the FPGA signal control module and multi-channel signal switching are used to control and switch respectively, and the power supply is The control module is used to power the work loading board; RS232控制模块，通过RS232协议对检测箱参数进行控制，并将回读回来的温度和冲击频率、振动频率和方向进行上位机显示；The RS232 control module controls the parameters of the detection box through the RS232 protocol, and displays the temperature, impact frequency, vibration frequency and direction read back on the host computer; JTAG控制模块，通过JTAG协议和FPGA信号控制模块进行通讯，通过Chipscop对采集的FPGA数字信号进行仿真和上位机实时显示；The JTAG control module communicates with the FPGA signal control module through the JTAG protocol, and uses Chipscop to simulate the collected FPGA digital signals and display them in real time on the host computer; GPIB控制模块，通过GPIB接口协议程控检测仪器，保存GPIB程控模块测试完成的数据，通过GPIB接口协议程控电源；The GPIB control module program-controls the testing instrument through the GPIB interface protocol, saves the completed test data of the GPIB program-controlled module, and program-controls the power supply through the GPIB interface protocol; IO控制模块，通过IO接口协议控制模拟开关ADG732BSUZ进行输入输出数字信号的导通，程控供电控制模块，为ULN2003驱动提供高低电平用于实现RT424012继电器的切换，给DUT提供电源和电压基准。The IO control module controls the analog switch ADG732BSUZ through the IO interface protocol to conduct input and output digital signals. The program-controlled power supply control module provides high and low levels for the ULN2003 driver to realize the switching of the RT424012 relay, and provides power and voltage reference for the DUT. 2.根据权利要求1所述的一种SIP集成电路可靠性试验批量监测系统，其特征在于，若利用检测箱进行振动测试，则检测箱为一个振动台，振动台上安装有振动加速度传感器、信号调制器、振动控制仪、功率放大器，进行测试时，将需要进行可靠性批量监测的SIP电路通过载板固定在振动台上面，PC上位机通过RS232发送给振动台，振动加速度传感器感应振动台的振动频率，通过信号调制器将信号输出给振动控制仪，振动控制仪根据控制谱的要求，将小功率的驱动电信号均衡后发送给功率放大器，功率放大器将其放大后提供给振动台的驱动线圈，振动加速度传感器感应振动频率，又依次来推动信号调制器传输给振动控制器，振动控制器对电信号进行实时修正，然后再发送给功率放大器，从而形成闭环控制。2. A SIP integrated circuit reliability test batch monitoring system according to claim 1, characterized in that, if a detection box is used for vibration testing, the detection box is a vibration table, and a vibration acceleration sensor is installed on the vibration table. Signal modulator, vibration controller, power amplifier, when testing, the SIP circuit that needs to be batch monitored for reliability is fixed on the vibration table through the carrier board, the PC host computer sends it to the vibration table through RS232, and the vibration acceleration sensor senses the vibration table The vibration frequency is output to the vibration controller through the signal modulator. The vibration controller balances the low-power driving electrical signal and sends it to the power amplifier according to the requirements of the control spectrum. The power amplifier amplifies it and provides it to the vibration table. The driving coil and the vibration acceleration sensor sense the vibration frequency, and in turn push the signal modulator to transmit it to the vibration controller. The vibration controller corrects the electrical signal in real time and then sends it to the power amplifier, thus forming a closed-loop control. 3.根据权利要求1所述的一种SIP集成电路可靠性试验批量监测系统，其特征在于，若利用检测箱进行温度测试，则检测箱为温循箱，温循箱内安装有温度控制器、驱动电路、功率变换电路、温度传感器、检测头、帕尔贴、DUT工装载板台，在进行测试时，PC上位机将通过RS232将温度控制曲线传输给温度控制器，温度传感器通过数模转换实时将箱体的温度传递给温度控制器，温度控制器根据实时采集数据与温度控制曲线进行对比输出控制信号到驱动电路，驱动电路控制功率转换电路调整帕尔贴的功率对箱体内部进行升温或者降温。3. A SIP integrated circuit reliability test batch monitoring system according to claim 1, characterized in that, if a detection box is used for temperature testing, the detection box is a temperature cycle box, and a temperature controller is installed in the temperature cycle box. , drive circuit, power conversion circuit, temperature sensor, detection head, Peltier, DUT loading plate. During the test, the PC host computer will transmit the temperature control curve to the temperature controller through RS232, and the temperature sensor will pass through the digital analog The conversion transfers the temperature of the box to the temperature controller in real time. The temperature controller compares the real-time collected data with the temperature control curve and outputs a control signal to the drive circuit. The drive circuit controls the power conversion circuit to adjust the Peltier power to the inside of the box. Warming up or cooling down. 4.根据权利要求1所述的一种SIP集成电路可靠性试验批量监测系统，其特征在于，工装包括载板、定位栓、定位销，载板包括竖直板和水平板，水平板设置在两个竖直板之间，水平板垂直设置于两个垂直板中间位置，竖直板顶部设置有栓孔、底部设备有螺孔，水平板上这只有销孔，通过螺孔将载板固定在温循箱内；定位稍为一个矩形块，其底部的两边向外延伸形成片状结构，片状结构上设置有一个销孔，该销孔与水平板上的销孔匹配，通过销孔将定位稍固定设置在水平板上；定位栓包括两个矩形块和一个矩形片，两个矩形块通过举行片连接，矩形块上设置有与竖直板上栓孔匹配的栓孔，通过该栓孔将定位栓两个矩形块分别固定设置在两个竖直板上。4. A SIP integrated circuit reliability test batch monitoring system according to claim 1, characterized in that the tooling includes a carrier plate, positioning bolts, and positioning pins, the carrier plate includes a vertical plate and a horizontal plate, and the horizontal plate is arranged on Between the two vertical plates, the horizontal plate is set vertically in the middle of the two vertical plates. There are bolt holes on the top of the vertical plate and screw holes on the bottom. There are only pin holes on the horizontal plate. The carrier plate is fixed through the screw holes. In the temperature cycle box; it is positioned as a slightly rectangular block, with both sides of its bottom extending outward to form a sheet structure. A pin hole is provided on the sheet structure, and the pin hole matches the pin hole on the horizontal plate. Through the pin hole, the The positioning is slightly fixed on the horizontal plate; the positioning bolt includes two rectangular blocks and a rectangular piece. The two rectangular blocks are connected by the holding piece. The rectangular block is provided with a bolt hole that matches the bolt hole on the vertical plate. Through the bolt The holes fix the two rectangular blocks of the positioning bolts on the two vertical plates respectively. 5.根据权利要求1所述的一种SIP集成电路可靠性试验批量监测系统，其特征在于，测试母板上设置有32个用于与DUT进行通信连接的排线，14个用于选择切换输入的32选1的模拟开关；FPGA信号控制模块包括信号控制芯片、JTAG接口、Flash电路、晶振、LDO，JTAG接口用于和上位机的JTAG控制模块进行通讯，Flash电路采用M25P16型号，晶振采用50M信号输出，LDO采用ASM1117-1.2和ASM1117-3.3，FPGA信号控制模块放置在整个测试母板的下端；IO控制卡，将和上位机的IO控制模块进行连接，放置在整个测试母板的最下端，IO控制卡分别对14个模拟开关ADG732BSUZ来进行信号的切换，同时通过2个ULN2003驱动器来控制8个RT424012继电器和1个输出控制继电器的导通和关断；供电控制模块，选用了8个LDO稳压器LT1764A和1个LT1763CS8低噪声LDO微功率稳压器作为产生DUT的电源和电压基准可调的器件，通过RT424012高压大电流的继电器，来进行DUT电源电压的切换；DUT供电插座，采用了5个DUT供电插座，分别用来为32个DUT提供高压和低压的供电选择，4个DUT供电插座、8个LT1764A和8个RT424012分别放置在测试母板的四周，其中LT1764A和RT424012靠近放置，能够为就近的4个排线端口提供电源电压，不至于供给给DUT产生太大的过冲；信号输出接口，这里测试母板最上面放置了两个BNC插头，用来分别连接GPIB程控模块中示波器、万用表、频谱等仪器。5. A SIP integrated circuit reliability test batch monitoring system according to claim 1, characterized in that 32 cables for communication connection with the DUT are provided on the test motherboard, and 14 cables are used for selective switching. Input 32-select 1 analog switch; FPGA signal control module includes signal control chip, JTAG interface, Flash circuit, crystal oscillator, LDO. The JTAG interface is used to communicate with the JTAG control module of the host computer. The Flash circuit adopts M25P16 model, and the crystal oscillator adopts 50M signal output, LDO uses ASM1117-1.2 and ASM1117-3.3, the FPGA signal control module is placed at the lower end of the entire test motherboard; the IO control card will be connected to the IO control module of the host computer and placed at the end of the entire test motherboard. At the lower end, the IO control card switches signals respectively for 14 analog switches ADG732BSUZ, and at the same time controls the on and off of 8 RT424012 relays and 1 output control relay through 2 ULN2003 drivers; the power supply control module uses 8 An LDO regulator LT1764A and an LT1763CS8 low-noise LDO micropower regulator are used to generate the power supply of the DUT and the voltage reference is adjustable. The RT424012 high-voltage and high-current relay is used to switch the DUT power supply voltage; the DUT power supply socket , 5 DUT power supply sockets are used to provide high-voltage and low-voltage power supply options for 32 DUTs respectively. 4 DUT power supply sockets, 8 LT1764A and 8 RT424012 are placed around the test motherboard, among which LT1764A and RT424012 Placed close to each other, it can provide power supply voltage to the four nearby cable ports without causing too much overshoot to the DUT. For the signal output interface, two BNC plugs are placed on the top of the test motherboard to connect to GPIB respectively. Instruments such as oscilloscopes, multimeters, spectrums, etc. in the programmable control module. 6.根据权利要求1所述的一种SIP集成电路可靠性试验批量监测系统，其PC上位机控制端特征在于，在进行可靠性试验时，根据不同的试验项目，上位机对32只SIP集成电路进行可靠性试验批量监控和测试；其上位机控制端界面中包括：输入批次、数据库设置、用前诊断控件、测试控件、RS232控制模块、JTAG控制模块、GPIB控制模块、IO控制模块、测试参数，测试统计结果等功能。6. A SIP integrated circuit reliability test batch monitoring system according to claim 1, the PC host computer control terminal is characterized in that during the reliability test, according to different test items, the host computer integrates 32 SIPs The circuit performs batch monitoring and testing of reliability tests; its host computer control interface includes: input batch, database settings, pre-use diagnostic control, test control, RS232 control module, JTAG control module, GPIB control module, IO control module, Test parameters, test statistical results and other functions. 7.一种SIP集成电路可靠性试验批量监测系统的测试方法，其特征在于，具体包括以下步骤：7. A testing method for a SIP integrated circuit reliability test batch monitoring system, which is characterized in that it specifically includes the following steps: 步骤一：搭建可靠性试验批量监测系统，具体包括：Step 1: Build a reliability test batch monitoring system, including: 将待做可靠性试验的32组SIP集成电路通过载板分别固定在温循箱或老化箱或振动台内；Fix the 32 sets of SIP integrated circuits to be tested for reliability in a temperature cycle box or aging box or vibration table through the carrier board; 通过34针的排线连接到测试母板上，用来连接多通道信号切换和供电控制模块；Connect to the test motherboard through a 34-pin cable to connect the multi-channel signal switching and power supply control module; 将测试母板上的电源线连接到电源相应的通道上，输出信号通过同轴线连接GPIB程控模块中的示波器上；Connect the power cord on the test motherboard to the corresponding channel of the power supply, and the output signal is connected to the oscilloscope in the GPIB program control module through the coaxial cable; 将输出信号连接到GPIB程控模块中万用表相应的端口上，将温循箱或老化箱或振动台与PC上位机的RS232控制模块进行连接；Connect the output signal to the corresponding port of the multimeter in the GPIB program control module, and connect the temperature cycle box or aging box or vibration table to the RS232 control module of the PC host computer; 将FPGA信号控制模块和PC上位机的JTAG控制模块进行连接，将GPIB程控模块、电源和PC上位机的GPIB控制模块进行连接；Connect the FPGA signal control module and the JTAG control module of the PC host computer, and connect the GPIB program control module, power supply and the GPIB control module of the PC host computer; 将多通道信号切换模块、供电控制模块通过50针的IO卡和PC上位机的IO控制模块进行连接，完成批量监测系统的搭建；Connect the multi-channel signal switching module and power supply control module through the 50-pin IO card and the IO control module of the PC host computer to complete the construction of the batch monitoring system; 步骤二：通过JTAG烧写对FPGA信号控制模块配置，通过RS232控制模块对温循箱或老化箱或振动台进行程控，设置相应的箱体环境温度和冲击频率、振动频率和方向并进行上位机显示；通过GPIB控制模块根据万用表、示波器、频谱等仪器设置的不同地址分别进行程控，同时程控电源设置相应的电源电压并进行限流；通过JTAG控制模块来将编写好的Verilog HDL程序烧写给FPGA，用于产生差分和高速信号，并对采集的FPGA数字信号进行仿真和上位机实时显示；Step 2: Configure the FPGA signal control module through JTAG programming, program the temperature cycle box or aging box or vibration table through the RS232 control module, set the corresponding box ambient temperature and impact frequency, vibration frequency and direction and conduct the host computer Display; use the GPIB control module to perform program control according to the different addresses set by multimeters, oscilloscopes, spectrum and other instruments. At the same time, the program-controlled power supply sets the corresponding power supply voltage and limits the current; the JTAG control module is used to burn the written Verilog HDL program to FPGA is used to generate differential and high-speed signals, and simulate the collected FPGA digital signals and display them in real time on the host computer; 步骤三：当选择了某一个需要进行可靠性试验的DUT时，需要通过IO接口协议来控制14个32选1的模拟开关ADG732BSUZ对选择的DUT进行输入输出数字信号的导通，同时操作供电控制模块，为ULN2003提供高电平5V和低电平0V的控制电压来实现RT424012继电器的切换，从而选择为不同的DUT提供电源和电压基准；Step 3: When a DUT that needs to be tested for reliability is selected, 14 analog switches ADG732BSUZ, selected 1 from 32, need to be controlled through the IO interface protocol to conduct the input and output digital signals of the selected DUT, and at the same time operate the power supply control. The module provides ULN2003 with high-level 5V and low-level 0V control voltages to switch the RT424012 relay, thereby choosing to provide power and voltage references for different DUTs; 步骤四：收到监测指令，分别切换启动指定DUT器件正常工作，进入循环等待监测指令到来，如果监测指令到来，即开启监测模式，将指定的DUT输入数字信号和时序，并对DUT进行上电使DUT能够正常工作；Step 4: After receiving the monitoring command, switch to start the specified DUT device to work normally, enter the loop and wait for the monitoring command to arrive. If the monitoring command arrives, the monitoring mode is turned on, the designated DUT inputs digital signals and timing, and the DUT is powered on. Enable the DUT to work properly; 步骤五：程控GPIB模块读取DUT的输出信号并回传给上位机，当接收到监控指令后，根据指令内容程控万用表、示波器、频谱等仪器进行参数监测，然后通过GPIB协议将回读的结果实时上传至PC上位机，PC上位机记录好待测器件DUT的测试结果和对应数据，重复步骤一到步骤四，直到所有的待测器件DUT全部完成测试。Step 5: The program-controlled GPIB module reads the output signal of the DUT and transmits it back to the host computer. After receiving the monitoring instruction, it programs the multimeter, oscilloscope, spectrum and other instruments according to the instruction content to monitor parameters, and then reads back the results through the GPIB protocol. Upload to the PC host computer in real time, and the PC host computer records the test results and corresponding data of the device under test DUT, and repeats steps one to four until all the devices under test DUT have been tested.
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CN117115364A (en) * 2023-10-24 2023-11-24 芯火微测(成都)科技有限公司 Microprocessor SIP circuit test status monitoring method, system and storage medium
CN118393326A (en) * 2024-06-26 2024-07-26 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Reliability testing device and method for FPGA device
CN119044732A (en) * 2024-09-03 2024-11-29 中国铁道科学研究院集团有限公司通信信号研究所 Domestic chip environment adaptability test method for train operation control system
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CN117115364A (en) * 2023-10-24 2023-11-24 芯火微测(成都)科技有限公司 Microprocessor SIP circuit test status monitoring method, system and storage medium
CN117115364B (en) * 2023-10-24 2024-01-19 芯火微测(成都)科技有限公司 Microprocessor SIP circuit test status monitoring method, system and storage medium
CN118393326A (en) * 2024-06-26 2024-07-26 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Reliability testing device and method for FPGA device
CN118393326B (en) * 2024-06-26 2024-10-11 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Reliability testing device and method for FPGA device
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