CN116801622A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device includes: a substrate including a first region and a second region; a buried gate located in the substrate of the first region; a dummy gate pattern and The functional gate pattern is located on the base of the second area, and the dummy gate pattern is close to the first area; wherein the dummy gate pattern includes a gate protective layer, and the upper surface of the gate protective layer has a slope.

Description

Semiconductor device and preparation method thereof

This application is a divisional application for a patent with the filing date of "September 11, 2018", the application number being "201811058556.0", and the invention title being "Semiconductor Device and Preparation Method thereof".

Technical field

The invention relates to the field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a preparation method thereof.

Background technique

DRAM (Dynamic Random Access Memory) is a semiconductor memory device. DRAM includes a memory array area and peripheral circuits. The memory array area includes memory, capacitors and other structures, and the peripheral circuits include Circuitry that controls the arrangement of memory cell arrays.

Usually, a dummy transistor (DummyMOS gate) is provided in the boundary area (storage array area and peripheral circuit transition area) to solve the edge effect (boundary edge effect) of the boundary area in the photolithography process and the micro-load in the chemical mechanical polishing process. Micro loading effect, but the setting of virtual transistors will cause the density of integrated circuits to decrease.

Contents of the invention

The main purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof to reduce the area occupied by dummy transistors and increase the density of integrated circuits.

To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, including:

Provide a substrate, the substrate includes a first region and a second region, and a first boundary is provided at the junction of the first region and the second region;

Forming a gate polysilicon layer on the substrate, the gate polysilicon layer being located in the second region and having a second boundary on a side close to the first region;

A gate metal layer and a gate protective layer are sequentially formed on the substrate, the gate metal layer and the gate protective layer cover the gate polysilicon layer, and are formed from the third portion of the gate polysilicon layer. Two boundaries extend into the first area; and

The gate protection layer, the gate metal layer and the gate polysilicon layer are etched in sequence to form mutually separated dummy gate patterns and functional gate patterns on the second area. The gate polysilicon layer of the polar pattern has the second boundary, and the gate metal layer and gate protection layer of the dummy gate pattern cover the gate polysilicon layer and extend to between the second boundary and the first boundary. time, so that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary;

A dielectric layer is formed on the substrate and planarized.

Optionally, in the method of manufacturing a semiconductor device, the steps of forming a dielectric layer on the substrate and performing planarization include:

A dielectric layer is formed on the substrate, the dielectric layer covers the substrate, the dummy gate pattern and the functional gate pattern, and fills the space between the dummy gate pattern and the functional gate pattern. gap;

Planarize the dielectric layer until the dummy gate pattern and the functional gate pattern are exposed.

Optionally, in the method of manufacturing a semiconductor device, the width of the dummy gate pattern between the first boundary and the second boundary accounts for 2% to 2% of the total width of the dummy gate pattern. 60%.

Optionally, in the method of manufacturing a semiconductor device, a buried gate is formed in the substrate in the first region, and the surface of the buried gate is lower than the surface of the substrate. An insulating layer is also formed on the buried gate and the substrate of the first region.

Optionally, in the preparation method of the semiconductor device, before forming the gate polysilicon layer, the method further includes: forming a gate oxide layer on the substrate, and the gate oxide layer covers the second region. of said base.

Optionally, in the method of manufacturing a semiconductor device, the step of forming the gate polysilicon layer on the substrate includes:

Forming a gate polysilicon material layer on the substrate, the gate polysilicon material layer covering the substrate and the gate oxide layer;

Forming a patterned photoresist layer on the gate polysilicon material layer;

Using the patterned photoresist layer as a mask, etch the gate polysilicon material layer, and remove the portion of the gate polysilicon material layer in the first region and the second region close to the first region, to form the gate polysilicon layer.

Optionally, in the method of manufacturing a semiconductor device, after forming the gate polysilicon layer and before forming the gate metal layer, the method further includes: forming a metal adhesion layer on the substrate.

Optionally, in the method of manufacturing a semiconductor device, the step of forming a dummy gate pattern and a functional gate pattern includes:

Forming a patterned photoresist layer on the gate protective layer;

Using the patterned photoresist layer as a mask, etch the gate protective layer, the gate metal layer, the metal adhesion layer and the gate polysilicon layer in sequence until the gate polysilicon layer is exposed. A substrate is formed on the substrate in the second region to form a dummy gate pattern and a functional gate pattern.

Optionally, in the method of preparing a semiconductor device, the gate metal layer is made of tungsten, aluminum or doped polysilicon, and the metal adhesion layer is made of cobalt silicide, titanium silicide or titanium nitride, The gate protection layer is made of silicon dioxide, silicon nitride or silicon nitride carbide, and the dielectric layer is made of silicon dioxide or silicon nitride.

Correspondingly, the present invention also provides a semiconductor device, including:

A substrate, the substrate includes a first region and a second region, and a first boundary is formed at the junction of the first region and the second region;

The virtual gate pattern and the functional gate pattern that are separated from each other are located on the substrate in the second area, and the virtual gate pattern is close to the first area; the virtual gate pattern and the functional gate pattern Both include a gate polysilicon layer, a gate metal layer and a gate protective layer located sequentially on the substrate, and the side of the gate polysilicon layer of the dummy gate pattern close to the first region has a first Two boundaries, the dummy gate pattern gate metal layer and the gate protection layer cover the gate polysilicon layer and extend between the second boundary and the first boundary, so that the height of the dummy gate pattern is from The second boundary gradually decreases from the first boundary;

A dielectric layer is located on the substrate and filled between the dummy gate pattern and the functional gate pattern.

Optionally, in the semiconductor device, the width of the dummy gate pattern between the first boundary and the second boundary accounts for 2% to 60% of the total width of the dummy gate pattern.

Optionally, in the semiconductor device, a buried gate is formed on the substrate in the first region, and a surface of the buried gate is lower than a surface of the substrate. An insulating layer is also formed on the in-type gate electrode and the base of the first region.

Optionally, in the semiconductor device, both the virtual gate pattern and the functional gate pattern further include: a gate oxide layer located between the substrate and the gate polysilicon layer, and the The projection of the gate oxide layer in the virtual gate pattern on the substrate coincides with the projection of the gate metal layer on the substrate.

Optionally, in the semiconductor device, both the virtual gate pattern and the functional gate pattern further include: a metal adhesion layer located between the gate polysilicon layer and the gate metal layer, and the The projection of the metal adhesion layer in the virtual gate pattern on the substrate coincides with the projection of the gate metal layer on the substrate.

Optionally, in the semiconductor device, the gate metal layer is made of tungsten, aluminum or doped polysilicon, the metal adhesion layer is made of cobalt silicide, titanium silicide or titanium nitride. The material of the extreme protective layer includes silicon dioxide, silicon nitride or silicon nitride carbide, and the material of the dielectric layer includes silicon dioxide or silicon nitride.

Compared with the prior art, the present invention has the following beneficial effects:

In the present invention, part of the dummy gate pattern is located between the first boundary and the second boundary, which is different from the dummy gate pattern located on the side of the second boundary away from the first boundary in the prior art. Compared with the above, the virtual gate pattern is closer to the first area, thereby saving the area of the second area, increasing the density of integrated circuits, and improving the area utilization rate of the semiconductor device.

Further, the gate polysilicon layer of the dummy gate pattern has the second boundary, and the gate metal layer and gate protection layer of the dummy gate pattern cover the gate polysilicon layer and extend to the second boundary. between the first boundary and the first boundary, so that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary, so that after the dielectric layer is flattened, the height of the dummy gate pattern The height of the dielectric layer to the first area is close to that of the dielectric layer in the first area, that is, the dielectric layer has a planarized surface to avoid subsequent etching of the dielectric layer in the first area. The problem of uneven etching is caused, and the problem of short circuit at the bottom of the subsequent device formed in the first region can also be avoided, thereby improving the performance of the semiconductor device.

Description of the drawings

Figure 1 is a schematic cross-sectional view of a semiconductor device;

Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

3 is a schematic cross-sectional view of a substrate provided in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

Figure 4 is a schematic cross-sectional view of forming a gate polysilicon material layer on the structure described in Figure 3;

Figure 5 is a schematic cross-sectional view of forming a patterned photoresist layer on the structure described in Figure 4;

Figure 6 is a schematic cross-sectional view of forming a gate polysilicon layer on the structure described in Figure 5;

Figure 7 is a schematic cross-sectional view of forming a gate metal layer and a gate protective layer on the structure described in Figure 6;

Figure 8 is a schematic cross-sectional view of forming a virtual gate pattern and a functional gate pattern on the structure shown in Figure 7;

FIG. 9 is a schematic cross-sectional view of forming a dielectric layer on the structure shown in FIG. 8 and performing planarization.

Among them, the reference signs are as follows:

1-base; 1A-first region; 1B-second region;

10-Buried gate; 11-Buried gate metal layer; 12-Buried gate dielectric layer;

20-Insulation layer;

30-gate oxide layer;

40-gate polysilicon layer;

50-metal adhesion layer;

60-gate metal layer;

70-Gate protection layer;

80-Medium layer;

2-Virtual gate pattern;

3-Functional gate pattern;

100-base; 100A-first region; 100B-second region;

110-buried gate; 111-buried gate metal layer; 112-buried gate dielectric layer;

120-insulation layer;

130-gate polysilicon layer; 130’-gate polysilicon material layer;

140-gate oxide layer;

150-Patterned photoresist layer;

160-metal adhesion layer;

170-gate metal layer;

180-gate protection layer;

190-dielectric layer;

200-Virtual gate pattern;

300-Function gate pattern;

S1-the first boundary; S2-the second boundary.

Detailed ways

Figure 1 is a schematic cross-sectional view of a semiconductor device. As shown in Figure 1, the semiconductor device includes: a substrate 1. The substrate 1 includes a first region 1A and a second region 1B. The first region 1A is used to form a memory cell. A region of the array, the second region 1B is a region where peripheral circuits of the array are formed, and there is a first boundary S1 at the junction of the first region 1A and the second region 1B.

In the first region 1A, a built-in buried gate 10 is formed in the substrate 1 , that is, the buried gate 10 is located in the groove of the substrate 1 . 10 includes a buried gate dielectric layer 12 located at the bottom and sidewalls of the groove and a buried gate metal layer 11 filled in the groove, and the surface of the buried gate 10 Lower than the surface of the substrate 1 , an insulating layer 20 is also formed on the buried gate 10 and the substrate 1 in the first region 1A.

In the second area 1B, a dummy gate pattern 2 and a functional gate pattern 3 are formed on the substrate 1 and are separated from each other. Compared with the functional gate pattern 3, the dummy gate pattern 2 is more precise. Close to the first region 1A, the dummy gate pattern 2 and the functional gate pattern 3 each include a gate oxide layer 30, a gate polysilicon layer 40, a metal adhesion layer 50, and a gate polysilicon layer 40 located on the substrate 1 in sequence. metal layer 60 and gate protection layer 70 . The dummy gate pattern 2 has a second boundary S2 close to the first region 1A.

A dielectric layer is also formed on the substrate 1, and the dielectric layer covers the substrate 1, the insulating layer 20, the dummy gate pattern 2 and the functional gate pattern 3. After that, it is necessary to The dielectric layer is planarized until the dummy gate pattern 2 and the functional gate pattern 3 are exposed, forming a structure as shown in FIG. 1 . The dummy gate pattern 2 is formed to overcome the boundary edge effect of the boundary area in the photolithography process and the micro loading effect in the chemical mechanical polishing process. However, the dummy gate pattern 2 It cannot be used as an effective functional transistor, and its formation will occupy the area of the second region 1B, resulting in a reduction in the density of the integrated circuit.

Moreover, since the second region 1B is formed with the dummy gate pattern 2 and the functional gate pattern 3, and the first region 1A is only formed with the insulating layer 20, the height of the first region 1A is smaller than that of the second region. With a height of 1B, after the dielectric layer 80 is subsequently filled and planarized, the surface of the dielectric layer 80 from the second boundary S2 to the first area 1A will be uneven, as shown in Figure 1. From the second boundary S2 to the first region 1A, the height of the dielectric layer 80 gradually decreases. This will lead to changes in the etching aspect ratio during subsequent etching in the first region 1A, resulting in the The relatively high areas of the dielectric layer 80 are likely to cause short circuits at the bottom of the device.

Based on the above problems, the present invention provides a semiconductor device and a preparation method thereof. It provides a substrate with a first region and a second region. There is a first boundary at the junction of the first region and the second region. A gate polysilicon layer is formed on the substrate. , the gate polysilicon layer is located in the second region, and has a second boundary on the side of the gate polysilicon layer close to the first region, and then a gate metal layer and a gate electrode are sequentially formed on the substrate. protective layer, the gate metal layer and the gate protective layer cover the gate polysilicon layer and extend from the second boundary of the gate polysilicon layer into the first region, and are then engraved in sequence Etching the gate protective layer, the gate metal layer and the gate polysilicon layer to form mutually separated dummy gate patterns and functional gate patterns on the second area, the dummy gate patterns The gate polysilicon layer has the second boundary, and the gate metal layer and gate protective layer of the dummy gate pattern cover the gate polysilicon layer and extend between the second boundary and the first boundary, So that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary, and finally a dielectric layer is formed on the substrate and planarized.

In the present invention, the gate polysilicon layer of the dummy gate pattern has the second boundary, and the gate metal layer and gate protection layer of the dummy gate pattern cover the gate polysilicon layer and extend to the second boundary. and the first boundary, so that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary. In this way, after the dielectric layer is subsequently filled and planarized, the height of the dielectric layer from the dummy gate pattern to the first region is close to the height of the dielectric layer in the first region, That is, the dielectric layer has a planarized surface, which avoids the problem of uneven etching caused by subsequent etching of the dielectric layer in the first region, and can also avoid the problem of short circuit at the bottom of subsequent devices formed in the first region. Thereby improving the performance of semiconductor devices.

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general substitutions known to those skilled in the art are also covered by the protection scope of the present invention.

Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. Secondly, the present invention is described in detail using schematic diagrams. When describing examples of the present invention in detail, for convenience of explanation, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

Please refer to FIG. 2 , which is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in Figure 2, the preparation method of the semiconductor device includes the following steps:

Step S01: Provide a substrate, the substrate includes a first region and a second region, and there is a first boundary at the junction of the first region and the second region;

Step S02: Form a gate polysilicon layer on the substrate, the gate polysilicon layer is located in the second region, and has a second boundary on a side of the gate polysilicon layer close to the first region;

Step S03: Form a gate metal layer and a gate protective layer on the substrate in sequence. The gate metal layer and the gate protective layer cover the gate polysilicon layer, and are formed from the gate polysilicon layer. the second boundary extends into the first area;

Step S04: Etch the gate protection layer, the gate metal layer and the gate polysilicon layer in sequence to form mutually separated virtual gate patterns and functional gate patterns on the second area, so The gate polysilicon layer of the dummy gate pattern has the second boundary, and the gate metal layer and gate protective layer of the dummy gate pattern cover the gate polysilicon layer and extend to the second boundary and the third boundary. between a boundary, so that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary;

Step S05: Form a dielectric layer on the substrate and perform planarization.

FIG. 3 is a schematic cross-sectional view of a substrate provided in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Please refer to FIG. 3 . In step S01 , a substrate 100 is provided. The substrate 100 includes a first region 100A and a second region 100B. There is a first region 100A at the junction of the first region 100A and the second region 100B. A boundary S1.

The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC); it may also be silicon on insulator (SOI) or germanium on insulator (GOI). ; It can also be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is preferably single crystal silicon (Si).

The substrate 100 includes a first region 100A and a second region 100B. The first region 100A is used to form a memory cell array, and the second region 100B is used to form peripheral circuits. There is a first boundary S1 at the junction of the first area 100A and the second area 100B. The height of the base 100 in the second area 100B is higher than the height of the base 100 in the first area 100A, that is, the upper surface of the base 100 in the second area 100B is higher than the base 100 on the upper surface of the first region 100A. In addition, the substrate 100 may also include areas for other functions, such as cutting areas, etc., which will not be detailed here.

A buried gate 110 is formed in the first substrate 100 of the first region 100A. As shown in FIG. 3 , a groove is formed in the first substrate 100 . The buried gate 110 is formed in within the groove. In the embodiment of the present application, the buried gate 110 includes a buried gate dielectric layer 112 and a buried gate metal layer 111. The buried gate dielectric layer 112 is located on the side of the groove. The buried gate metal layer 111 is filled in the groove, and the upper surface of the buried gate dielectric layer 112 is lower than the upper surface of the buried gate metal layer 111 . The upper surface of the buried gate metal layer 111 is lower than the upper surface of the substrate 100 . An insulating layer 120 is also formed on the buried gate 110 and the substrate 100 .

Figure 4 is a schematic cross-sectional view of forming a gate polysilicon material layer on the structure shown in Figure 3 . Figure 5 is a schematic cross-sectional view showing a patterned photoresist layer formed on the structure shown in Figure 4 . Figure 6 is a schematic cross-sectional view of the structure shown in Figure 5 . A schematic cross-sectional view of the gate polysilicon layer formed on the described structure. Please refer to FIG. 4, FIG. 5 and FIG. 6. In step S02, a gate polysilicon layer 130 is formed on the substrate 100. The gate polysilicon layer 130 is located in the second region 100B and is in the second region 100B. The gate polysilicon layer has a second boundary S2 on a side close to the first region 100A.

In this embodiment of the present application, before forming the gate polysilicon layer 130, a gate oxide layer 140 is first formed on the substrate 100 in the second region 100B. The material of the gate oxide layer 140 includes but is not limited to silicon dioxide. Specifically, the gate oxide layer 140 is grown using the ISSG method. This method will only grow SiO ₂ on the surface of exposed silicon, but will not grow on the surface with SiN. That is, it will only grow on all parts of the second region 100B. The gate oxide layer 140 is formed on the substrate 100 .

Then, as shown in FIG. 4 , a gate polysilicon material layer 130' is formed on the substrate, and the gate polysilicon material layer 130' covers the substrate 100 and the gate oxide layer 140.

Next, as shown in FIGS. 5 and 6 , the gate polysilicon material layer 130 ′ is etched to remove portions of the first region 100A and the second region 100B close to the first region 100A. The polysilicon material layer 130' is formed to form a gate polysilicon layer 130. The gate polysilicon layer 130 has a second boundary S2 on a side close to the first region 100A, that is, the gate as shown in FIG. 6 The left side of the polysilicon layer 130 overlaps the second boundary S2.

In the embodiment of the present application, a photoresist layer (not shown) is formed on the gate polysilicon material layer 130', and the photoresist layer is patterned, for example, by exposing and developing the photoresist layer. A patterned photoresist layer 150 is formed, as shown in FIG. 5 . The patterned photoresist layer 150 exposes the gate polysilicon layer 130 in the first region 100A, and exposes a portion of the gate in the second region 100B close to the first region 100A. Polysilicon material layer 130'. Next, the gate polysilicon material layer 130' is etched using the patterned photoresist layer 150 as a mask to remove the gate polysilicon material layer 130' that is not blocked by the patterned photoresist layer 150. The gate polysilicon material layer 130', which is blocked by the patterned photoresist layer 150, remains to form a gate polysilicon layer 130, as shown in FIG. 6. The gate polysilicon layer 130 has a second boundary S2 close to the first region 100A.

So far, in the embodiment of the present application, two boundaries have been set. The first boundary S1 is the boundary between the first area 100A and the second area 100B, and the second boundary S2 is the boundary between the first area 100A and the second area 100B. The gate polysilicon layer 130 is close to one side of the first region 100A.

FIG. 7 is a schematic cross-sectional view of forming a gate metal layer and a gate protective layer on the structure shown in FIG. 6 . Referring to FIG. 7 , in step S03 , a gate metal layer 170 and a gate protection layer 180 are sequentially formed on the substrate 100 , and the gate metal layer 170 and the gate protection layer 180 cover the substrate 100 . The gate polysilicon layer 130 extends from the second boundary S2 of the gate polysilicon layer 130 into the first region 100A.

In this embodiment of the present application, before forming the gate metal layer 170 , a metal adhesion layer 160 is first formed on the substrate 100 to ensure that the subsequently formed gate metal layer 170 is in contact with the gate polysilicon layer. 130 adhesion, the metal adhesion layer 160 covers the substrate 100, the gate oxide layer 140 and the gate polysilicon layer 130. Specifically, the metal adhesion layer 160 covers the first The substrate 100 in the region 100A covers the gate oxide layer 140 between the first boundary S1 and the second boundary S2, and also covers the side of the second boundary S2 away from the first boundary S1. the gate polysilicon layer 130 .

Next, a gate metal layer 170 is formed on the metal adhesion layer 160 , and the gate metal layer 170 covers the metal adhesion layer 160 . Then, a gate protection layer 180 is formed on the gate metal layer 170 , and the gate protection layer 180 covers the gate metal layer 170 . The material of the metal adhesion layer 160 includes but is not limited to cobalt silicide, titanium silicide or titanium nitride. The material of the gate metal layer 170 includes but is not limited to tungsten, aluminum or doped polysilicon. The gate protection layer The materials of 180 include but are not limited to silicon dioxide, silicon nitride or silicon nitride carbide.

It should be noted that since the gate polysilicon layer 130 is not formed between the first boundary S1 and the second boundary S2, the second boundary S2 is close to the second boundary S2 in the second region 100B. The height of the side of the first boundary S1 (the left side of the second boundary S2 as shown in Figure 7) is lower than the height of the side of the second boundary S2 away from the first boundary S1 (the second side of the second boundary S2 as shown in Figure 7). the height of the right side of the boundary S2). Then, after forming the metal adhesion layer 160, the gate metal layer 170 and the gate protection layer 180, in the process from the left side of the second boundary S2 to the first boundary S1, The upper surface of the gate protection layer 180 has a slope, that is, the height of the semiconductor device gradually decreases to a certain height.

FIG. 8 is a schematic cross-sectional view of forming a dummy gate pattern and a functional gate pattern on the structure shown in FIG. 7 . Referring to FIG. 8 , in step S04 , the gate protective layer 180 , the gate metal layer 170 and the gate polysilicon layer 130 are sequentially etched to form a dummy gate pattern 200 and a functional gate. The pattern 300 is on the second area 100B, the gate polysilicon layer 130 of the dummy gate pattern 200 has the second boundary S2, the gate metal layer 170 and the gate protection layer of the dummy gate pattern 200 180 covers the gate polysilicon layer 130 and extends between the second boundary S2 and the first boundary S1, so that the height of the dummy gate pattern 200 is from the second boundary S2 to the first boundary. S1 gradually decreases.

A photoresist layer (not shown) is formed on the gate protection layer 180 , and the photoresist layer is patterned. For example, the photoresist layer is exposed and developed to form a patterned photoresist layer. , the patterned photoresist layer only blocks the area on the gate protection layer 180 where the dummy gate pattern 200 and the functional gate pattern 300 are scheduled to be formed, and then the patterned photoresist layer is used as a mask. , sequentially etching the gate protective layer 180, the gate metal layer 170, the metal adhesion layer 160, the gate polysilicon layer 130 and the gate oxide layer 140 to form a structure as shown in Figure 9 The virtual gate pattern 200 and the functional gate pattern 300.

A part of the dummy gate pattern 200 is located between the first boundary S1 and the second boundary S2. In the embodiment of the present application, the dummy gate pattern 200 is between the first boundary S1 and the second boundary. The width between S2 accounts for 2% to 60% of the total width of the dummy gate pattern 200. The bottom of the dummy gate pattern 200 located between the first boundary S1 and the second boundary S2 does not have the Gate polysilicon layer 130 . In FIG. 1 , the dummy gate pattern 2 is located on the side of the second boundary S2 away from the first boundary S1 , that is, on the right side of the second boundary S2 . In FIG. 9 , the A part of the dummy gate pattern 200 is located between the first boundary S1 and the second boundary S2, that is, the dummy gate pattern 200 intersects the second boundary S2. Compared with FIG. 1 , in the embodiment of the present application, it is equivalent to the virtual gate pattern 200 being closer to the first region 100A, so the area of the second region 100B can be appropriately reduced, thereby increasing the density of integrated circuits. degree, improving the area utilization of semiconductor devices.

The dummy gate pattern 200 includes a gate oxide layer 140 located on the substrate, a gate polysilicon layer 130 located on a portion of the gate oxide layer 140, and a gate polysilicon layer 130 located between the gate oxide layer 140 and the gate electrode. The metal adhesion layer 160 on the polysilicon layer 130 , the gate metal layer 170 on the metal adhesion layer 160 , and the gate protection layer 180 on the gate metal layer 170 . The virtual gate pattern 200 does not have the function of a real gate, but is only used to overcome the boundary edge effect in the photolithography process and the micro loading effect in the chemical mechanical polishing process. That is, the method for manufacturing a semiconductor device provided by the embodiments of the present application can also increase the density of integrated circuits on the basis of overcoming the boundary edge effect and the micro-load effect.

As mentioned above, in the process of forming the metal adhesion layer 160 , the gate metal layer 170 and the gate protection layer 180 , due to the existence of the gate polysilicon layer 130 , each layer formed thereon There is a slope between the first boundary S1 and the second boundary S2. Between the gate protection layer 180, the gate metal layer 170, the metal adhesion layer 160 and the gate electrode After the polysilicon layer 130 is etched, the upper surface of the gate protection layer 180 will also have a slope between the first boundary S1 and the second boundary S2, that is, from the second boundary S2 to At the first boundary S1, the height of the dummy gate pattern 200 gradually decreases.

The functional gate pattern 300 includes a gate oxide layer 140, a gate polysilicon layer 130, a metal adhesion layer 160, a gate metal layer 170 and a gate protection layer 180 located sequentially on the substrate, wherein the gate The oxide layer 140, the gate polysilicon layer 130, the metal adhesion layer 160 and the gate metal layer 170 form a gate electrode, which will form a transistor together with the subsequently formed source and drain electrodes as a device in the second region 100B. , the gate protection layer 180 is used to protect the gate.

FIG. 9 is a schematic cross-sectional view of forming a dielectric layer on the structure shown in FIG. 8 and performing planarization. As shown in FIG. 9 , in step S05 , a dielectric layer 190 is formed on the substrate 100 and planarized.

Specifically, a dielectric layer 190 is deposited on the substrate 100, covering the substrate 100, the insulating layer 120, the dummy gate pattern 200 and the functional gate pattern 300, and fills Fill the gaps between components.

The dielectric layer 190 is then planarized. Since the height of the dummy gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1, after the dielectric layer 190 is planarized, the dummy gate pattern 200 is close to the first boundary S1. The height of the dielectric layer 190 on one side of the boundary S1 is relatively close to the height of the dielectric layer 190 in the first region 100A, that is, the dielectric layer 190 in the first region 100A has better flatness. , the problem of uneven etching caused by subsequent etching of the dielectric layer can be avoided, and the problem of bottom short circuit can also be avoided when the device is subsequently manufactured in the first region 100A, thereby improving the performance of the semiconductor device.

Correspondingly, the present invention also provides a semiconductor device, which is prepared by using the above-mentioned semiconductor device preparation method. As shown in Figure 9, the semiconductor device includes:

Substrate 100. The substrate 100 includes a first region 100A and a second region 100B. There is a first boundary S1 at the junction of the first region 100A and the second region 100B;

The dummy gate pattern 200 and the functional gate pattern 300 are located on the substrate 100 in the second area 100B. The dummy gate pattern 200 and the functional gate pattern 300 are separated from each other, and the dummy gate pattern 200 Close to the first region 100A; the dummy gate pattern 200 and the functional gate pattern 300 each include a gate polysilicon layer 130, a gate metal layer 170 and a gate protective layer 180 located on the substrate 100 in sequence, and The side of the gate polysilicon layer 130 of the dummy gate pattern 200 close to the first region 100A has a second boundary S2, and the gate metal layer 170 of the dummy gate pattern 200 is connected to the first region 100A. The gate protection layer 180 covers the gate polysilicon layer 130 and extends between the first boundary S1 and the second boundary S2, so that the height of the dummy gate pattern 200 is from the second boundary S2 to The first boundary S1 gradually decreases.

It also includes: a dielectric layer 190 located on the substrate 100 and filled between the dummy gate pattern 200 and the functional gate pattern 300 . Since the height of the dummy gate pattern 200 gradually decreases from the second boundary S2 to the first boundary S1, the dielectric layer 190 from the dummy gate pattern 200 to the first region 100A is in contact with the height of the dummy gate pattern 200. The height of the dielectric layer 190 in the first region 100A is close to each other, that is, the dielectric layer 190 has a planar surface, which avoids the problem of uneven etching caused by subsequent etching of the dielectric layer 190 in the first region 100A. , and can also avoid the problem of short circuit at the bottom of the device subsequently formed in the first region 100A, thereby improving the performance of the semiconductor device.

A buried gate 110 is formed on the substrate 100 in the first region 100A. The surface of the buried gate 110 is lower than the surface of the substrate 100 . Between the buried gate 110 and An insulating layer 120 is also formed on the substrate 100 in the first region 100A. Specifically, a groove is formed in the substrate 100, and the buried gate 110 is formed in the groove and partially fills the groove. The buried gate 110 in the groove is An insulating layer 120 is formed on the top of 110 and the substrate 100 . The buried gate 110 includes a buried gate dielectric layer 112 and a buried gate metal layer 111. The buried gate dielectric layer 112 fills the bottom and side walls of the groove. The buried gate metal layer 111 is filled in the groove.

Both the dummy gate pattern 200 and the functional gate pattern 300 further include: a gate oxide layer 140 located between the substrate 100 and the gate polysilicon layer 130 , and all the elements in the dummy gate pattern 200 The projection of the gate oxide layer 140 on the substrate 100 coincides with the projection of the gate metal layer 170 on the substrate 100 . Both the dummy gate pattern 200 and the functional gate pattern 300 further include: a metal adhesion layer 160 located between the gate polysilicon layer 130 and the gate metal layer 170 , and the dummy gate pattern 200 The projection of the metal adhesion layer 160 on the substrate 100 coincides with the projection of the gate metal layer 170 on the substrate 100 .

In the embodiment of the present application, the virtual gate pattern 200 includes a gate oxide layer 140 located on the substrate 100, and a part of the gate oxide layer 140 is located between the first boundary S1 and the second boundary S2. During the period, the gate polysilicon layer 130 is located on part of the gate oxide layer 140. The gate polysilicon layer 130 is located on the side of the second boundary S2 away from the first boundary S1. layer 140 and the metal adhesion layer 160, the gate metal layer 170 and the gate protection layer 180 on the gate polysilicon layer 130. The projections of the gate protection layer 180 , the gate metal layer 170 , the metal adhesion layer 160 and the gate oxide layer 140 on the substrate overlap.

The width of the dummy gate pattern 200 between the first boundary S1 and the second boundary S2 accounts for 2% to 60% of the total width of the dummy gate pattern 200 . Compared with the semiconductor device shown in FIG. 1 , the dummy gate pattern 200 is closer to the first region 100A, thereby saving the area of the second region 100B, increasing the density of integrated circuits, and increasing the area of the semiconductor device. Utilization.

The gate metal layer 170 is made of tungsten, aluminum or doped polysilicon, the metal adhesion layer 160 is made of cobalt silicide, titanium silicide or titanium nitride, and the gate protection layer 180 is made of carbon dioxide. Silicon, silicon nitride or silicon nitride carbide, the material of the dielectric layer 190 includes silicon dioxide or silicon nitride.

To sum up, in the semiconductor device and the preparation method thereof provided by the present invention, a part of the dummy gate pattern is located between the first boundary and the second boundary, which is different from the second boundary in the prior art. Compared with the virtual gate pattern on the side away from the first boundary, the virtual gate pattern is closer to the first area, thereby saving the area of the second area, increasing the density of integrated circuits, and improving the efficiency of semiconductor devices. area utilization rate.

Further, the gate polysilicon layer of the dummy gate pattern has a second boundary, and the gate metal layer and gate protection layer of the dummy gate pattern cover the gate polysilicon layer and extend to the second boundary and the gate protective layer. between the first boundary, so that the height of the dummy gate pattern gradually decreases from the second boundary to the first boundary. After the dielectric layer is subsequently formed and planarized, the dummy gate pattern The height of the dielectric layer to the first area is close to that of the dielectric layer in the first area, that is, the dielectric layer has a planarized surface to avoid subsequent etching of the dielectric layer in the first area. The problem of uneven etching is caused, and the problem of short circuit at the bottom of the subsequent device formed in the first region can also be avoided, thereby improving the performance of the semiconductor device.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of the claims.

Claims (21)

1. A semiconductor device, comprising:

A substrate comprising a first region and a second region;

a buried gate within the substrate of the first region;

a virtual gate pattern and a functional gate pattern on the substrate in the second region, the virtual gate pattern being adjacent to the first region;

the virtual grid pattern comprises a grid protection layer, and the upper surface of the grid protection layer is provided with a slope.

2. The semiconductor device according to claim 1, wherein,

the height of the upper surface of the gate protection layer with the gradient gradually decreases in the direction of the virtual gate pattern towards the boundary of the first region and the second region.

3. The semiconductor device according to claim 1, further comprising:

a dielectric layer covering the substrate; wherein the dielectric layer of the second region between the first region and the dummy gate pattern to the first region has a planarized surface.

4. The semiconductor device of claim 1, wherein the dummy gate pattern further comprises:

the grid metal layer is provided with a gradient;

The grid protection layer is positioned on the grid metal layer.

5. The semiconductor device according to claim 4, wherein,

the height of the upper surface of the gate metal layer with the gradient gradually decreases in the direction of the virtual gate pattern towards the boundary of the first region and the second region.

6. The semiconductor device according to claim 4, wherein the dummy gate pattern further comprises:

a metal adhesion layer, wherein the metal adhesion layer has a gradient;

wherein the gate metal layer is located on the metal adhesion layer.

7. The semiconductor device according to claim 6, wherein,

the metal adhesion layer has a height of the sloped upper surface gradually decreasing in a direction in which the dummy gate pattern faces the boundary of the first region and the second region.

8. The semiconductor device according to claim 6, wherein the metal adhesion layer is made of cobalt silicide, titanium silicide, or titanium nitride.

9. The semiconductor device according to any one of claims 1 to 8, wherein the dummy gate pattern further comprises:

a gate oxide layer on the substrate;

And the grid polycrystalline silicon layer is positioned on the grid oxide layer.

10. The semiconductor device of claim 9, wherein the semiconductor device comprises a semiconductor substrate,

the gate polysilicon layer is located on a portion of the gate oxide layer.

11. The semiconductor device of claim 10, wherein the semiconductor device comprises,

the gate polysilicon layer is located on the gate oxide layer far from the first region, and the width of the portion of the dummy gate pattern excluding the gate polysilicon layer is 2% -60% of the total width of the dummy gate pattern.

12. The semiconductor device of claim 10, wherein the semiconductor device comprises,

the projection of the grid oxide layer on the substrate coincides with the projection of the grid metal layer on the substrate; and/or the number of the groups of groups,

the projection of the metal adhesion layer on the substrate coincides with the projection of the gate metal layer on the substrate.

13. A method of manufacturing a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first area and a second area, and a buried grid is formed in the substrate of the first area;

forming a virtual gate pattern and a functional gate pattern on the substrate in the second region, the virtual gate pattern being adjacent to the first region,

The virtual gate pattern comprises a gate protection layer, and the upper surface of the gate protection layer of the virtual gate pattern has a gradient.

14. The method of claim 13, wherein the process comprises,

the gate protection layer of the dummy gate pattern has a height of the sloped upper surface gradually decreasing in a direction in which the dummy gate pattern faces a boundary of the first region and the second region.

15. The method of manufacturing according to claim 13, further comprising:

forming a dielectric layer, wherein the dielectric layer covers the substrate, the virtual gate pattern and the functional gate pattern and fills a gap between the virtual gate pattern and the functional gate pattern;

and flattening the dielectric layer until the virtual gate pattern and the functional gate pattern are exposed, wherein the dielectric layer positioned in the first region and the second region between the virtual gate pattern and the first region has a flattened surface.

16. The method according to any one of claim 13 to 15, wherein,

a first boundary is arranged at the junction of the first area and the second area;

Forming the dummy gate pattern and the functional gate pattern includes:

forming a gate polysilicon layer on the substrate of the second region and having a second boundary on a side near the first region;

sequentially forming a gate metal layer and a gate protection layer, wherein the gate metal layer and the gate protection layer cover the gate polysilicon layer and extend from the second boundary of the gate polysilicon layer into the first region;

the gate protection layer, the gate metal layer and the gate polysilicon layer are sequentially etched to form a virtual gate pattern and a functional gate pattern, the gate polysilicon layer of the virtual gate pattern has the second boundary, and the gate metal layer and the gate protection layer of the virtual gate pattern cover the gate polysilicon layer and extend to between the second boundary and the first boundary.

17. The method of claim 16, wherein the gate metal layer of the dummy gate pattern has a slope, and a height of an upper surface of the gate metal layer of the dummy gate pattern having the slope gradually decreases in a direction of the dummy gate pattern toward a boundary between the first region and the second region.

18. The method of claim 16, wherein the process comprises,

before forming the gate polysilicon layer, the method further comprises:

forming a gate oxide layer on the substrate, wherein the gate oxide layer covers the substrate of the second region.

19. The method of claim 16, wherein the process comprises,

after forming the gate polysilicon layer, before forming the gate metal layer, further comprising:

and forming a metal adhesion layer, wherein the metal adhesion layer covers the substrate and the gate polysilicon layer.

20. The method of claim 19, wherein the process comprises,

forming the dummy gate pattern and the functional gate pattern, including:

and etching the gate protection layer, the gate metal layer, the metal adhesion layer and the gate polysilicon layer in sequence until the substrate is exposed, so as to form the virtual gate pattern and the functional gate pattern.

21. The method of claim 20, wherein the metal adhesion layer of the dummy gate pattern has a slope, and a height of an upper surface of the metal adhesion layer of the dummy gate pattern has the slope gradually decreases in a direction of the dummy gate pattern toward a boundary between the first region and the second region.