CN1168005C - Method and system for processing local defect memory - Google Patents

Abstract

A processing method of local defect memory scans the original program code, and determines a first break point and a second break point before and after the defect address corresponding to the defect memory cell. Moving the section program code between to the first address and the second address of the program code which do not correspond to the defect address. Connecting the execution sequence of the moved section program code and the unmoved part in the original program code, and adjusting the reference address between the moved section program code and the unmoved part in the original program code or the section program code. The modified program may be loaded into memory. The defective memory cells can be avoided without affecting the execution function of the original program code.

Description

Method and system for processing local defect memory

technical field

The present invention relates to a processing method and system for locally defective memory, and in particular to a processing method and system, which can adjust the program code that has not been loaded into the memory or already exists in the memory, so that the program code is still Can be loaded into memory with partially defective memory cells and executed.

Background technique

In the past, if there were any defective memory cells in the memory IC, such memory IC would not be sold on the market. In order to reduce the scrapping of the entire IC due to a single or a small number of defects, there are currently many technologies that can make a partially defective memory IC operate like a completely normal memory IC.

For example, US Patent No. 4939694 discloses a memory system capable of self-testing and self-repairing. The memory system can be self-tested in the field to locate defective memory cells. Once any defective memory cells are found, the memory system will use a device called an error correction code engine (error correction code engine) to repair these defective memory cells. If the error correction code engine is overwhelmed, the memory system will replace the defective memory cells.

In addition, in US Patent No. 5,644,541, a substitution memory is used to process a semiconductor memory containing defective memory cells. When there are several error bits at known positions in the semiconductor memory, a mapping logic is used to direct all access requests that need to access these error bits to a good storage unit in the replacement memory, thereby replacing Originally defective memory cells.

US Patent No. 5278847 discloses a fault-tolerating memory system using error detecting and correcting code (EDAC). The reliability of stored data can be achieved by adding EDAC codes and adding spare-bits to each data character.

In US Patent No. 5579266, laser repair technology and programmable fuse repair technology are used to deal with defective memory cells, and redundant memory can be used to replace defective memory.

Among them, such as the error detection and repair technology disclosed in US Patent No. 4939694, the encoding and spare bit technology disclosed in US Patent No. 5278847, or the access guidance technology disclosed in US Patent No. 5644541, Not only will it increase the difficulty of hardware design, but it will also cause a burden on program execution each time the executable machine code is executed. In addition, the redundant memory technology disclosed in US Pat. No. 5,579,266 is also very complicated in terms of hardware design and actual repair procedures.

On the other hand, generally executable machine program code is generated from the source code of a computer program using a compiler and a linker. Machine program code can be loaded directly into memory for execution. Figure 1 shows a system configuration diagram of a general single chip computer (single chip computer) or a single chip system (system-on-a-chip). As shown in the figure, this system includes CPU (central processing unit, or microprocessor) 1, RAM (random access memory, random access memory) 3, ROM (read-only memory, read-only memory) 5, I/ O interface 7 and external storage device 9, such as hard disk drive, floppy disk drive or CD-ROM and so on. Under normal operating conditions, the CPU 1 loads the machine program code to be executed into the RAM 3 through the I/O interface 7 or the external storage device 9 through the data/address bus 10 . General machine program code contains three parts, namely instruction (instruction), data (data) and stack (stack). CPU1 will start to execute the machine program code from the program entry point (entry point) of the instruction part.

Fig. 2 shows a flow chart of general machine program code during execution (execution). First, a program entry point is acquired (S1). Then the address (address) of the next instruction is obtained (S2), and according to the address, the operation code (opcode) in the next instruction is read (S3). Then the operation code is decoded (S4), and it is judged whether an operand (operand) is needed according to the instruction form. If the instruction requires an operand, the operand is read from the subsequent address (S5). Finally, the instruction is executed according to the instruction action represented by the operation code and the data content or reference address represented by the operand (S6). If the instruction is a program termination instruction (S7), the execution of the machine program code is completed (S8), otherwise, return to step S2 to obtain the address of the next instruction. It must be noted that each instruction does not necessarily contain the same byte length, which is related to the type of CPU used. The instruction set adopted by the general CPU can be divided into a variable-length codeword instruction set and a fixed-length codeword instruction set.

In the above-mentioned execution flow, it is mainly for the instruction part in the machine program code. If the same execution program is applied to the data part or the stack part, the decoding result will be completely confused. When a data byte is decoded into a wrong opcode by CPU1, the following data will be mistaken for operands according to the wrong opcode. Generally, the CPU 1 cannot identify which is the instruction part, which is the data part or the stack part through standard fetching and decoding operations. In addition, the instruction part and data/stack part of the program code cannot be divided arbitrarily. The division of the instruction part must be determined according to the format of each instruction, that is, the byte length of each instruction (including operands and opcodes). The data/stack part is generally inseparable, which is why the data/stack part may contain data dependencies that can only be judged during execution, such as arrays in data structures.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method and system for processing locally defective memory, which can be used when the program code is not loaded or the program code is not loaded without changing the hardware configuration and without increasing the software execution burden. Where this already exists, modify the way program code is stored in the local defective memory to avoid using defective memory locations.

The object of the present invention can be achieved through the following measures:

A method for loading program code into a memory for execution, applicable to a memory including a plurality of storage units and an original program code to be loaded into the memory, comprising the following steps:

determining whether said memory contains defective memory cells;

When the above-mentioned memory does not contain defective storage units, then load the above-mentioned original program code into the above-mentioned memory;

When the memory includes at least one defective storage unit, the following steps are performed:

Scanning the above-mentioned original program code, before and after a defect address corresponding to the above-mentioned original program code in the above-mentioned defective storage unit, determine a first breaking point and a second breaking point;

Move the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first address and the second address, and the addresses between the above-mentioned first address and the above-mentioned second address do not correspond to the above-mentioned memory The above defect address of ;

When the segment program code includes at least one executable instruction, a connection instruction is provided to connect the execution sequence of the moved segment program code and the unmoved part of the original program code; and

Loading the unmoved part of the above original program code, the above connection instruction and the moved above section program code into the above memory.

A memory processing system for processing a memory comprising a plurality of storage units, comprising:

A microprocessor, coupled to the above-mentioned memory, is used to load an original program code. When the storage units to which the above-mentioned original program code is loaded are all non-defective storage units, then load the above-mentioned original program code into the above-mentioned memory. When the above-mentioned original program code When the storage unit where the program code is loaded includes at least one defective storage unit, the original program code is scanned, and the first breakpoint and the second breakpoint are determined before and after a defective address corresponding to the original program code in the defective storage unit , and move the segment program code between the first breakpoint and the second breakpoint to between the first address and the second address, and when the segment program code contains at least one executable instruction, provide a A connection instruction, used to connect the execution order of the above-mentioned section program code and the unmoved part of the above-mentioned original program code, and load the unmoved part of the above-mentioned original program code, the above-mentioned connection instruction and the above-mentioned section program code after moving to the above-mentioned memory , wherein the memory address corresponding to the program code between the above-mentioned first address and the above-mentioned second address does not include the above-mentioned defective address.

A memory processing method for preventing local weakening, suitable for a memory loaded with an original program code, comprising the following steps:

Examining the above-mentioned memory to find defective storage units with weakened functions in the above-mentioned memory;

When the above-mentioned memory contains at least one storage unit with weakened function, the following steps are performed:

Scanning the original program code, determining a first breakpoint and a second breakpoint before and after a defect address of the defective storage unit corresponding to the original program code;

Move the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first storage unit and the second storage unit in the above-mentioned internal memory, between the above-mentioned first storage unit and the above-mentioned second storage unit does not contain the defective memory cells described above; and

When the segment program code includes at least one executable instruction, link the execution sequence of the moved segment program code and the unmoved portion of the original program code.

A memory processing system for processing a memory comprising a plurality of storage units and storing an original program code, comprising:

A microprocessor, coupled to the above-mentioned memory, is used to check whether the storage unit of the above-mentioned memory has a weakened storage unit, and when the weakened storage unit exists and has stored the above-mentioned original program code, then scan the above-mentioned original program code, Before and after the weakened storage unit corresponds to a weakened address of the original program code, determine a first breakpoint and a second breakpoint, and move the section program code between the first breakpoint and the second breakpoint to Between the first storage unit and the second storage unit in the above-mentioned internal memory, and when the above-mentioned section program code contains at least one executable instruction, connect the moved section of the above-mentioned program code and the unmoved part of the above-mentioned original program code The execution sequence of , wherein the defective storage unit is not included between the first storage unit and the second storage unit.

A memory processing method is applicable to a memory comprising a plurality of storage units and an original program code to be loaded in the memory, comprising the following steps:

determining whether said memory contains defective memory cells;

When the above-mentioned memory does not contain a defective storage unit or the above-mentioned original program code is not loaded in the defective address corresponding to the defective storage unit in the above-mentioned memory, then load the above-mentioned original program code into the above-mentioned memory;

When the above-mentioned original program code is loaded into the defective address corresponding to at least one defective storage unit in the above-mentioned memory, the following steps are performed:

Scanning the above-mentioned original program code, before and after a defect address corresponding to the above-mentioned original program code in the above-mentioned defective storage unit, determine a first breaking point and a second breaking point;

loading the above original program code into the above memory;

Load the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first storage unit and the second storage unit, and the above-mentioned defect is not included between the above-mentioned first storage unit and the above-mentioned second storage unit storage unit; and

When the segment program code includes at least one executable instruction, link the execution sequence of the segment program code located between the first storage unit and the second storage unit with other parts of the original program code.

A memory processing system for processing a memory comprising a plurality of storage units, comprising:

A microprocessor, coupled to the above-mentioned memory, is used to load an original program code. When the storage unit where the above-mentioned original program code is loaded contains at least one defective storage unit, the system can scan the above-mentioned original program code, and in the above-mentioned Determining a first breakpoint and a second breakpoint before and after a defective address corresponding to the original program code in the defective storage unit, and loading the original program code into the memory and loading the first breakpoint and the second breakpoint The segment program code between the first storage unit and the second storage unit, and when the segment program code contains at least one executable instruction, the connection is between the first storage unit and the second storage unit The execution order of the above segment program code and other parts of the above original program code, wherein the defective storage unit is not included between the first storage unit and the second storage unit.

A program code scanning processing method for determining a separable breaking point of an original program code, the above-mentioned program code scanning processing method includes the following steps:

Provide a first data table and a second data table, the first data table is used to record the address to be scanned related to the conditional branch instruction in the original program code, and the second data table is used to record the read address range ;

Read the above original program code in sequence;

When the read instruction is a conditional branch instruction, record the address to be scanned related to the conditional branch instruction in the above-mentioned first data table, and continue scanning according to the next address or branch destination address of the above-mentioned conditional branch instruction;

updating the address range of the second data table as the instruction is read, and outputting a detachable breakpoint when at least one complete instruction is read; and

When the read command is an end command or its address is within the address range of the second data table, continue reading according to an address to be scanned in the first data table, and transfer the address to be scanned from the first Datasheet removed.

Compared with the prior art, the present invention has the following advantages:

According to the above purpose, the present invention proposes a method for processing locally defective memory, which can be applied between a memory containing multiple storage units and the original program code to be loaded into the memory. Assume that there is at least one defective memory cell in the memory. Firstly, the original program code is scanned, and the first breakpoint and the second breakpoint are determined before and after the defect address corresponding to the defective memory unit in the original program code. Then move the section program code between the first breakpoint and the second breakpoint to between the first address and the second address, wherein the defect address is not included between the first address and the second address. When the moved segment program code contains at least one executable instruction (ie, includes an instruction part), it is necessary to connect the execution sequence of the moved segment program code and the unmoved part of the original program code. And when there is a reference address between the moved section program code and the unmoved part of the original program code or there is a reference address inside the section program code itself, adjustment is made according to the situation. Finally, the unmoved part of the original program code, the connection instruction and the moved segment program code can be sequentially loaded into the memory. Since the program code loaded by the above method is in an executable state and will not be stored in a known defective storage unit, even if there is a defective storage unit in the memory, the memory can still be used normally. In addition, the above processing does not involve modification or change of hardware circuits, so the implementation cost is quite low.

In addition, if the original program code to be loaded has been modularized, the required breaking point can be directly determined when the program code is scanned. However, if the original program code is not pre-modularized, the original program code is read in sequence, and then multiple breakpoints are output according to the composition of the instructions in the original program code, and finally the defect address and the connection to be inserted can be used. The command length determines the required first breakpoint and second breakpoint. To confirm that the complete original program code has been scanned, the present invention provides the following methods. First, a first data table and a second data table are provided, wherein the first data table is used to record the branch destination address of the conditional branch instruction in the original program code, and the second data table is used to record the read address range. When the read instruction is a conditional branch instruction, the branch destination address of the conditional branch instruction is recorded in the first data table; when an instruction is read, the address range of the second data table is updated. When the read instruction is an end instruction or its address is within the address range of the second data table, as long as the branch destination address of the first data table does not belong to the address range of the second data table, the The branch destination address of the data table continues to be read. Through the above method of processing branches and loops, it is possible to ensure that all instructions are scanned.

In addition, two unconditional branch instructions can be inserted to connect the moved section program code with the unmoved part of the original program code. The first unconditional branch instruction is inserted at the address of the first breakpoint, and its destination address is the first address after the section program code moves; the second unconditional branch instruction is inserted at the second address after the section program code moves, Its destination address is the second breakpoint.

The above processing method can also be changed slightly in practice. For this reason, the present invention additionally proposes a local defect memory processing method, the procedure of which is slightly different from the above method. Firstly, the original program code is scanned and a first breaking point and a second breaking point are determined before and after the defective address corresponding to the defective memory unit. Next, load the entire original program code into the memory first, and in addition, between the first storage unit and the second storage unit that does not contain the defective storage unit, load the area between the first breakpoint and the second breakpoint again segment program code. Then, it is the same as the aforementioned method: connect the execution sequence of the reloaded segment program code and other parts of the original program code, and correct the reference addresses between them. In this way, in addition to achieving the purpose of the previous way, because the program code is first loaded into the memory, the speed of the subsequent processing steps, such as the processing of modifying the reference address, can also be accelerated.

In addition, the present invention also provides a method for processing partially defective memory, which is applicable to the situation where the original program code already exists in the memory. Firstly, the memory is checked and at least one defective storage unit with weakened function is found in the memory. Then scan the original program code so as to determine the first breaking point and the second breaking point before and after the defective address corresponding to the defective memory unit. Then move the section program code between the first breaking point and the second breaking point to between the first storage unit and the second storage unit which do not contain the defective storage unit in the internal memory. Then, it is the same as the aforementioned method: connect the execution sequence of the moved segment program code and the unmoved part of the original program code, and correct the reference addresses between them. Since this method can be applied to the memory in use, it is more convenient in application.

Based on the above, the local defect memory processing method and system of the present invention have the following advantages:

1. In the present invention, the method for solving the local defect storage unit does not need to change the design on the hardware (memory configuration) or increase the hardware circuit, but avoids using the defective storage unit by modifying the program code; and the program code The increased burden during execution is not serious, and only two unconditional branch commands (ie JMP) need to be added in the best case. Therefore, in terms of implementation complexity and cost, the present invention does have excellent industrial application value.

2. The present invention is applicable not only to known defective memory, but also to memory in use, as described in the third embodiment. The hardware correction method in the prior art usually needs to extract the memory and modify it separately during execution, but the present invention can adjust the program code in the memory in use, so the application is more convenient.

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

Figure 1 shows a system configuration diagram of a general single chip computer (single chip computer) or a single chip system (system-on-a-chip).

Fig. 2 shows a flow chart of general machine program code during execution (execution).

Fig. 3 shows a configuration diagram of a local defect memory processing system according to the first embodiment of the present invention.

FIG. 4 shows a flow chart of the local defect memory processing method according to the first embodiment of the present invention.

Fig. 5 shows a flow chart of the program code scanning method in the present invention.

FIG. 6 shows a schematic diagram of processing a program code example by the program code scanning method of the present invention.

Fig. 7 shows a schematic diagram of connecting the moved section program code and the unmoved part of the original program code in the present invention.

Fig. 8 shows a schematic diagram of modifying reference addresses in the present invention.

FIG. 9 shows a flow chart of the local defect memory processing method according to the second embodiment of the present invention.

Fig. 10 shows a configuration diagram of a local defect memory processing system according to a third embodiment of the present invention.

FIG. 11 shows a flow chart of a local defect memory processing method according to the third embodiment of the present invention.

Symbol Description 1~CPU; 3~RAM (memory); 5~ROM; 7~I/O interface; 9~external storage device; 10~data/address bus; 20~original program code; 30~first data table; 40~second data table; C1-C7~command segment part; D1-D3~data/stack part; 21~defect address; 51, 52~connection instruction; 50~program code after moving segment program code; 60~ Complete program code for reference address correction; R1-R3, R1'-R3'~reference address.

Detailed ways

The local defect memory processing method and system of the present invention mainly corrects the original program code to be loaded or existing to avoid the defective storage unit, so that the memory IC with the partial defective storage unit can still operate normally. Modifying the processing method of the original program code is mainly achieved by identifying the break point of the machine program code and moving the segment program code. That is to say, first identify the separable breakpoints in the original program code, and then determine the section of program code that can be moved according to the program position corresponding to the actual defective storage unit; move the section of program code to the normal After the working memory unit is used, the connection instruction is used to maintain the execution sequence between the moved segment program code and the original program code, so that the defective memory unit can be avoided. Because the present invention does not need to change or redesign the hardware circuit, and the additional burden added on software execution is also very limited (only connection instructions are added), so the purpose of the present invention can be achieved. The technical content of each embodiment of the present invention will be described in detail below with reference to the drawings.

First embodiment:

Fig. 3 shows a configuration diagram of the local defect memory processing system of the first embodiment. In FIG. 3 , the memory 3 includes at least one defective storage unit. In the following descriptions, unless otherwise specified, a single defective storage unit or a group of adjacent defective storage units is used as a preset condition. The CPU 1 is preparing to load the original program code 20 into the memory 3 through the data/address bus 10 , and the storage units to be loaded by the original program code 20 include the defective storage units mentioned above. Therefore, the loader (loader) executed in CPU1 must perform some pre-processing actions to ensure that the loaded original program code 20 will not occupy the defective storage unit, and the original program code 20 itself can still be normal. implement. In this embodiment, CPU1 and memory 3 can coexist in the same integrated circuit, such as the application of a single chip system (system on a chip), in addition, it can also be an individual independent integrated circuit. At this time, CPU1 and memory 3 pass a specific The IC pins are connected to perform the defect inspection, processing and other steps described later.

FIG. 4 shows a flow chart of the local defect memory processing method of the first embodiment, which details various steps that the CPU 1 must perform before loading the original program code 20 . First, the CPU 1 has to decide the location of the defective memory cell in the memory 3 (S10). That is, it is necessary to perform a defect test on the memory 3 in order to check whether there is a defective memory unit and its physical location. An example of checking whether a memory cell is a defect is to write data "1" and "0" into each memory cell, and then read whether the data is correct. If the written data and the read data do not match, it means the The storage unit is defective. The device for actually executing the test may be the CPU 1 itself, or may be executed by an external tester or computer.

According to the physical address of the defective storage unit obtained through testing and the loading information of the original program code 20 (such as the address of the loading start point), the corresponding defective address of the defective storage unit in the original program code 20 can be determined (S11), That is, the absolute reference address represented by the defective storage unit in the original program code 20 . Since the defective storage unit cannot operate normally, the loader executed by the CPU 1 must change and load the program code originally scheduled to be stored in the defective storage unit to other storage units to avoid data loss. However, according to the foregoing description of general machine program codes, it can be seen that machine program codes cannot be divided arbitrarily, and a certain byte may only be a part of a certain instruction and cannot be moved separately to avoid confusion of instructions and data. Therefore, the CPU 1 must find an appropriate breaking point in the original program code 20, so as to correctly move the byte originally occupying the defective storage unit.

Next, scan the original program code 20 ( S12 ), so as to find out all the breakable points in the original program code 20 . In general machine program codes, the individual instructions in the instruction part are separable breakpoints, this is because even if the individual instructions are cut off, CPU1 can still correctly decode the correct instruction message during execution; relatively, the data part and The stack part is inseparable because there may be dependencies between the data and the stack that can only be checked at execution time, such as array data. On the other hand, the CPU 1 cannot directly distinguish the instruction part from other parts in the machine program code. Therefore, the CPU1 must scan the entire instruction part in the original program code 20 to determine all the separable breakpoints.

Fig. 5 shows a flowchart of the scanning method of the original program code 20 in this embodiment. The so-called "scanning" here includes operations such as fetching opcodes, decoding, and fetching operands, but does not need to be executed. In order to scan the entire instruction portion of the original program code 20, two special types commonly seen in general machine program codes, namely branch and loop, must be specially handled.

The branch type will generate two different instruction execution sequences in the original program code 20, generally caused by conditional branch instructions, such as JNE, JE, JG and so on. In the scanning process, in order to ensure that all instructions are processed, both instruction execution sequences need to be scanned. In this embodiment, the first data table 30 (as shown in FIG. 5 ) will be established during the scanning process. When any conditional branch instruction is encountered, the next address of the branch instruction or the branch purpose of the branch instruction will be displayed. The address (branch-toaddress) is stored in the first data table 30 . In this way, after the main instruction execution sequence is scanned, other execution sequences can be scanned according to the first data table 30 . In addition, it should be noted that general branch instructions also include an unconditional branch instruction (unconditional branch instruction), such as JMP, but since this instruction does not cause two different instruction execution sequences, the scanning in this embodiment can be based on Its destination address (branch-to address) continues to scan. On the other hand, the loop type will cause the scan to not be terminated. In this embodiment, the second data table 40 is created during the scanning process to record the scanned address range, and the second data table 40 is updated every time an instruction is scanned. When repeated scanning reaches the inside of the loop, it can be judged according to the second data table 40 that this part has been scanned, thus preventing further scanning of subsequent instructions.

The operation of each step in Fig. 5 will be described in detail below. First, the program entry point is acquired (S110). Then obtain and designate the address of the next instruction (S111), and read and decode the operation code in the next instruction according to the address (S112). If the instruction requires an operand, the operand is read from the subsequent address (S113). What is read at this time is a complete instruction, so it can be recorded as a separable breakpoint. Then judge whether this instruction is a conditional branch instruction (S114), if so, then can: (i) add the branch destination address of this conditional branch instruction in the first data table 30 (S115), and according to the conditional branch instruction Continue scanning at the next address; or (ii) add the next address of the conditional branch instruction into the first data table, and continue scanning according to the branch destination address of the conditional branch instruction. Then determine the next address to be scanned (S116), and judge whether the instruction at this address is a return instruction (such as RET) or a program end instruction (such as END) (S117). If the instruction at the next address is not a return instruction or a program end instruction, it is judged according to the second data table 40 whether the address is within the scanned address range ( S121 ). If the next address is not in the scanned address range, modify the second data table 40 to update the scanned address range ( S122 ), and continue to process the next instruction. If in step S117 the instruction of the next address is indeed a return instruction or a program end instruction, or in step S121 the next address is the scanned address range, then it is judged whether there is still an address to be scanned in the first data table 30 (S118). If there are still, then obtain an address to be scanned from the first data table 30 and remove it from the first data table 30 (S119), then modify the scanned address range in the second data table 40 (S122), Continue to process subsequent instructions of the address to be scanned. If there is no address to be scanned in the first data table 30, it means that all instructions have been scanned (S120). At this point, all the separable breakpoints have been obtained, and the instruction part and data/stack part in the original program code 20 can be judged. In FIG. 5 , the dotted box P1 represents the relevant steps for processing the branch type, and the dotted line box P2 represents the relevant steps for processing the loop type.

The processing actions in the above-mentioned scanning process can be briefly described as follows: (1) when the read instruction is a conditional branch instruction (such as JNE, JE, JG, etc.), the branch destination address or the next address of the conditional branch instruction Recorded in the first data table 30; (2) when finishing reading an instruction, just update the address range of the second data table 40 and output the break point; (3) if the read instruction is an end instruction or Return instruction or its address is in the address range of the second data table 40, as long as a certain address to be scanned of the first data table 30 does not belong to the address range of the second data table 40, just from this waiting address range of the first data table 30 The scan address continues to read.

According to the scanning procedure described in FIG. 5 , an example is used below to illustrate its scanning operation. FIG. 6 is a schematic diagram of processing a program code example according to the scanning method of FIG. 5 . Among them, the program entry point is Q1. When scanning from Q1 to Q2, a conditional branch instruction JNE is read, and the branch destination address Q6 of the conditional branch instruction JNE is recorded in the first data table 30 at this time. When continuing to scan to Q3, an unconditional branch instruction JMP is read. The unconditional branch instruction JMP does not need to store its branch destination address Q10, but directly goes to its branch destination address to continue scanning. Then scan from Q10 to Q11, then read two conditional branch instructions JG and JE in sequence. Similarly, after the first data table 30 records the branch destination addresses Q4 and Q8 of the two instructions, the scan continues. When Q12 is scanned, the program end instruction END is read, so the scanning of the main program segment ends. At this time, the scanned areas include C1, C2, C6, and C7, and the addresses to be scanned of Q6, Q4, and Q8 are recorded in the first data table 30 . Next, continue scanning from the first address to be scanned Q6 until Q7 reads the return instruction RET. Then continue to scan from the second address Q4 to be scanned until Q5 is scanned. Although no end command or return command is read, the next address Q6 belongs to the scanned area, so the scan still ends. Then continue scanning from the third to-be-scanned address Q8 until Q9 is scanned. Similarly, although no end command or return command has been read, the next address Q10 belongs to the scanned area, so the scan still ends. So far, there are no other addresses to be scanned in the first data table 30, so the entire scanning work is completed. During the scanning process, it can be judged that all separable breakpoints (that is, every complete instruction is a separable breakpoint before and after), and it is judged that C1-C7 belong to the instruction part, while D1-D3 belong to data or stack, etc. The non-instruction part, and a continuous program code segment that has not been scanned after the scanning is completed, can be regarded as a non-instruction segment such as data or stack.

Returning to Fig. 4, when the scanning action of the original program code 20 is completed, the first breaking point and the second breaking point can be respectively determined before and after the defective address corresponding to the defective memory unit according to the obtained separable breaking point (S13) . Between or before and after each complete instruction are separable breakpoints. The instruction part (may also include data/stack part) between the first breakpoint and the second breakpoint is called the segment program code, and the segment program code needs to be moved to other addresses to avoid the defect address. In this embodiment, the way to determine the first break point and the second break point is to select the break point closest to the defect address but still have several bytes between the defect address, that is, the first/second break point There are still several good storage units between the binary breakpoint and the defect address, which can be used to store connection instructions (this point will be described in detail later). In the following descriptions, this case is taken as an example for illustration. However, the above method of selecting the breaking point is not intended to limit the present invention. For example, the first/second breaking point can also be selected according to the distance between the defect address and the defect address by at least several breakable points. In addition, if the subsequent moving method is to shift all the program codes after the defect address down by a certain length of bytes, the first breakpoint can be based on the fact that there are still several words before the defect address and between the defect address. section, and the second breakpoint is set at the end of the program code, that is, after the last byte of the program code, and the program code near and behind the defect address is set as the segment program code that needs to be moved, and After moving the segment program code to the defect address, the object of the present invention can still be achieved.

After determining the program code segment between the first breakpoint and the second breakpoint, the program code segment can be moved between the first address and the second address (S14). It must be noted that the defective address should not be located between the first address and the second address, that is, the segment program code does not contain defective memory cells in the loaded memory cells. After completing the re-addressing of the segment program code, if the moved segment program code contains instruction parts, then a link instruction must be inserted so that the original program code still maintains its program execution sequence. In this embodiment, two unconditional branch instructions (JMP) are mainly inserted to achieve the purpose of connection. The first unconditional branch instruction is inserted at the address of the first breakpoint, and its branch destination address points to the segment program code after the move; the second unconditional branch instruction is inserted behind the segment program code after the move, and Its branch destination address is the address pointing to the second breakpoint, but if the address of the second breakpoint is set at the end of the program code, then the second unconditional branch instruction is not needed. Therefore, when the program code is executed to the instruction on the first breakpoint address (which is the beginning part of the segment program code), it will jump to the moved segment program code to continue execution by the first unconditional branch instruction; After completing the instruction of the section program code after moving, then jump back to the instruction on the second breakpoint address by the second unconditional branch instruction. In addition, if the segment program code is only a simple data/stack part, there is no need to add connection instructions, only need to modify the reference address related to it.

Fig. 7 shows a schematic diagram of connecting the moved section program code and the unmoved part of the original program code in this embodiment. As shown in the figure, the original program code 20 includes program codes A-G, and the defect address 21 is located in the program code E, and the first breakpoint and the second breakpoint are respectively determined before and after the program code E. When the program code E is moved to a new address range, the moved program code E' appears. Symbols 51 and 52 represent the inserted first/second unconditional branch instructions, respectively. After the program code D is executed, it jumps to the program code E' through the first unconditional branch instruction; after the program code E' is executed, it jumps back to the program code F through the second unconditional branch instruction. Therefore, the program execution sequence of the original program code can be maintained, and only two more unconditional branch instructions need to be executed.

After the connection action of step S15 is completed, the pre-loading action of the CPU1 has been roughly completed, leaving only the common reference address (reference address) in the general machine program code unprocessed. If the reference address in the original program code 20 is related to the moved section program code, it must be checked and corrected. Therefore, the CPU 1 must correct the relevant reference address (S16). Fig. 8 shows a schematic diagram of correcting reference addresses in this embodiment. As shown in the figure, there are three kinds of reference addresses in the original program code 20 that are related to the program code E including the defect address 21, which are respectively marked as R1, R2, and R3. R1 indicates that the reference address of the instruction in the program code E points to the address in the program code E; R2 indicates that the reference address of the instruction in other program codes (such as program code B) points to the address in the program code E; R3 indicates that in the program code E The reference address of the instruction points to other program codes (such as program code B). These reference addresses must be modified into the program code E' after the program code E is moved, and its reference addresses (such as R1', R2', R3') must be corrected so as to produce the machine program code 60 that can actually be loaded into the internal memory 3.

To correct the reference address, the CPU 1 can scan the entire original program code 20 again to find the reference address related to the program code section containing the defective address. In addition, the general reference address can be subdivided into two addressing modes, which are relative addressing mode and absolute addressing mode. If considered together with the above three reference address situations, there are six types in total. Among the reference addresses of R1, only the reference addresses of the absolute address addressing mode need to be corrected. Among the reference addresses of R3, only the reference addresses of the relative address addressing mode need to be corrected. In the reference address of R2, both relative and absolute addresses need to be corrected. When correcting the reference address of the above-mentioned absolute address addressing mode (both pointing to the segment program code E), then add the relative displacement between the program code E and the moved program code E' to the reference address. To modify the reference address of the above-mentioned relative address addressing mode, it can also be achieved by using the relative displacement between the program code E and the moved program code E'. However, the relative address addressing mode generally has its limitations in use, that is, the relative address is usually limited to a certain range, so it is more complicated to deal with the relative address addressing mode. For example, in this embodiment, a considerable number of usable storage units are reserved before and after the defective address 21, and this part can be used to insert connected instructions to indirectly achieve the same effect; The program code is shifted to the rear (ie, the direction of the higher address) by several bytes in order to avoid the defective storage unit, which can also avoid the trouble that a segment of the program code moves too far beyond the range of the relative address addressing mode; One solution is to adjust the encoding format of the editor, such as using absolute addresses as much as possible to avoid using relative addresses for encoding, or changing the addressing codes of relative addresses affected by the movement of a section of program code to absolute Address addressing code.

When the above-mentioned pre-processing is completed, the loader of the CPU 1 can load the original program code, the connection instruction and the moved section program code into the memory 3 to complete all the steps (S17). Because the segment program code that would have occupied the defective storage unit has been moved, the program code can be executed and operated normally.

In addition, although the above description takes a single defective memory cell as an example, for those skilled in the art, it can be extended to the case of multiple defective memory cells, and the basic processing mode is still the same. In addition, although the detachable breakpoint is determined by byte scanning in this embodiment, for those skilled in the art, the original program code can also be modularized to conveniently determine the detachable breakpoint. At this time, there is no need to perform the scanning action described in this embodiment, and a relatively simple scanning procedure can be used to determine the first breakpoint and the second breakpoint before and after the defect address.

Although the processing method and system of the local defect memory disclosed above are taken as an example of a general computer system, its best application example should be in a single-chip system (system-on-a-chip) or a single-chip computer (single chip computer). chip computer). In such systems, the memory modules are generally embedded and cannot be replaced arbitrarily. In the case that some memory cells are found to be defective, the method disclosed in this embodiment can be used, and the entire chip can still execute program codes normally after processing. In addition, the local defect memory disclosed in this embodiment can also be applied to the application of programming programs, such as program programming of flash memory (flash memory) or electronically erasable programmable read-only memory (PROM). Recorded, even if the local storage unit is defective, it can still be used. Most importantly, the implementation of this embodiment does not increase the cost and complexity of hardware design, and the burden on software execution is lighter than that of the prior art. It can be seen that the present invention has extremely high industrial application value.

Second embodiment:

Although the processing method of a certain program has been disclosed in the first embodiment, which can solve the problem of partially defective memory, there are still some programs that can be changed. For example, this embodiment is produced by changing the scanning processing method of the original program code and the order of loading the memory from the first embodiment.

FIG. 9 shows a flow chart of the local defect memory processing method of the second embodiment. As shown in Figure 9, on the one hand, CPU1 determines the physical location of the defective storage unit (S20) and determines the corresponding defect address (S21) of the defective storage unit in the original program code 20; 20 performs scanning (S22). The defect address of the defective storage unit can be determined by step S20 and step S21, and the divisible break point in the original program code 20 can be determined by step S22. This synchronization processing can be applied to a CPU with multi-tasking function or a system with multiple CPUs. Then, according to the address of the defect and the address of the breakable point, the first breakpoint and the second breakpoint can be further determined ( S23 ), that is, the code range of the segment to be moved.

The sequence of the next steps is different from that of the first embodiment. First load the entire original program code 20 into the internal memory 3 (S24). At this time, the segment program code including the defective address will also be loaded into the storage unit adjacent to the defective storage unit, but because it contains the defective storage unit, this Some section codes are not actually used. Next, load the section program code again between the first storage unit and the second storage unit in the memory 3 (S25), and there is no defective storage unit between the first storage unit and the second storage unit. Then, as in the first embodiment, a connection instruction is inserted to connect the segment program code with other parts in the original program code 20 (S26), and the reference address therein is corrected (S27). Like the first embodiment, the program code in the memory 3 can be executed normally at this time, and the actually executed program code will not be stored in the defective storage unit.

In the second embodiment, the original program code 20 and the moved section program code are firstly loaded, and then the connection and reference address correction are performed. In addition to achieving the same effect as the first embodiment, such a processing method can also obtain better processing efficiency. Generally, the source of the original program code is mostly an external storage medium, such as a hard disk drive, a floppy disk drive, and the like. When performing connection actions and modifying reference addresses, the processing speed is slower than that of the memory 3, especially when modifying the reference addresses, the entire original program code 3 must be scanned again. However, in this embodiment, all the program codes to be processed have been loaded in the memory 3, so the above processing steps can be completed more quickly. In addition, the original program code can also be stored in a known non-defective memory, such as ROM, RAM or PROM, which can speed up the scanning speed of the above program code, but this method needs to temporarily or permanently store the original program code in another Good memory, or a portion of a memory that has been determined to be free of defective memory cells.

Third embodiment:

The first and second embodiments are applicable to the situation that the original program code has not been loaded into the internal memory. At this time, the CPU (microprocessor) can perform pre-processing before the original program code is loaded into the internal memory, so as to adjust the program code to Avoid defective memory cells. However, the situation to be dealt with in this embodiment is the phenomenon that the original program code has been successfully loaded into the memory, but some storage units show weakened functions after a period of time. These degraded memory cells can be read normally at present, but after a certain period of time, the logic value read from them will become increasingly illegible. At this time, the original program code content in the memory must be adjusted to avoid these defective storage units with weakened functions.

Fig. 10 shows a configuration diagram of a local defect memory processing system of the third embodiment. As shown in FIG. 10, the original program code 20 has been loaded in the memory 3 at this moment. During system operation, the CPU 1 itself or other external processors or testers can periodically test each storage unit in the memory 3 . If the data read out by a certain storage unit during the test has become more and more difficult to identify, then CPU1 sets this storage unit as a defective storage unit, and executes the processing method disclosed below in order to stop using the weakened function. defective memory cells.

FIG. 11 shows a flow chart of the local defect memory processing method of the third embodiment. As shown in Fig. 11, the original program code 20 already exists in the memory 3 (S30). At this time, on the one hand, CPU1 can scan (S31) the original program code 20 to obtain all divisible breakpoints in the original program code 20; unit (S32). Since the original program code 20 has been loaded into the memory 3, the corresponding defective address can be quickly determined according to the defective storage unit. Then, according to the address of the defect and the addresses of all the breakpoints, the first breakpoint and the second breakpoint can be further determined ( S33 ), that is, the range of the segment program code that needs to be moved.

First find out a section of memory block with normal function (that is, between the first storage unit and the second storage unit) in the memory 3, so as to accommodate the section program code that needs to be moved. Then copy the section program code between the first storage unit and the second storage unit (S34). Next, as in the first embodiment, a link instruction is inserted to link the segment program code with other parts of the original program code 20 (S35), and the reference address therein is corrected (S36). At this time, the program code in the memory 3 can be executed normally, and the actually executed program code will not be stored in the defective storage unit with weakened functions.

In addition, if the above-mentioned internal memory contains a plurality of non-adjacent defective storage units, the present invention can also be applied to generate an array of separable breakpoint groups corresponding to these defective memory units, and several programs between these separable breakpoint groups The code segment is moved to several different new addresses, and the associated reference address corrections are made to produce a modified program code that avoids these defective memory locations when executed.

Although the present invention is disclosed above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art can make a small amount of changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be determined by the claims in combination with the specification and drawings.

Claims (52)

1. A method for loading program code into memory for execution, applicable to a memory comprising a plurality of storage units and an original program code to be loaded in said memory, characterized in that: it comprises the following steps: determining whether said memory contains defective memory cells; When the above-mentioned memory does not contain defective storage units, then load the above-mentioned original program code into the above-mentioned memory; When the memory includes at least one defective storage unit, the following steps are performed: Scanning the above-mentioned original program code, before and after a defect address corresponding to the above-mentioned original program code in the above-mentioned defective storage unit, determine a first breaking point and a second breaking point; Move the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first address and the second address, and the addresses between the above-mentioned first address and the above-mentioned second address do not correspond to the above-mentioned memory The above defect address of ; When the segment program code includes at least one executable instruction, a connection instruction is provided to connect the execution sequence of the moved segment program code and the unmoved part of the original program code; and Loading the unmoved part of the above original program code, the above connection instruction and the moved above section program code into the above memory. 2. The method for loading program code into memory for execution as claimed in claim 1, characterized in that: it also includes a step: Correct the reference address between the above section program code and the unmoved portion of the above original program code. 3. The method for loading program code into memory for execution as claimed in claim 2, characterized in that: said correcting step is used to correct the relative difference between the moved section program code and the unmoved part in the above-mentioned original program code The addressing mode reference address, and the relative addressing mode reference address and the absolute addressing mode reference address of the unmoved portion of the above-mentioned original program code relative to the moved above-mentioned segment program code. 4. The method for loading program code into memory for execution as claimed in claim 2, characterized in that: it also includes a step: Correct the absolute addressing mode reference address in the program code of the above segment after moving. 5. The method for loading program code into memory for execution as claimed in claim 1, wherein the step of scanning the above-mentioned original program code also includes the following steps: Read the above original program code in sequence; According to the composition of each instruction in the above original program code, output a plurality of separable breakpoints; and The first breaking point and the second breaking point are determined based on the defect address and the inserted connection command. 6. The method for loading program codes into memory for execution as claimed in claim 5, wherein the step of reading the original program codes in sequence also includes the following steps: Provide a first data table and a second data table, the above-mentioned first data table is used to record the branch destination address of the conditional branch instruction in the above-mentioned original program code, and the above-mentioned second data table is used to record the read address range; When the read instruction is a conditional branch instruction, recording the branch destination address of the conditional branch instruction in the first data table; When finishing reading an instruction, update the address range of the above-mentioned second data table; and When the read instruction is an end instruction or its address is within the address range of the above-mentioned second data table, and when the branch destination address of the above-mentioned first data table does not belong to the address range of the above-mentioned second data table, then according to the above The branch destination address of the first data table continues to be read. 7. The method for loading program code into memory for execution as claimed in claim 1, characterized in that: in the above-mentioned connecting step, the first unconditional branch instruction is inserted at the address of the first breakpoint, and the first unconditional The destination address of the branch instruction is the first address after the section program code is moved, and a second unconditional branch instruction is inserted into the second address after the section program code is moved, and the destination address of the second unconditional branch instruction is the above-mentioned first address. Bipartite breakpoint. 8. The method for loading program code into memory for execution as claimed in claim 1, wherein the second breaking point is after the last byte of the original program code. 9. A memory processing system for processing a memory comprising a plurality of storage units, characterized in that: it comprises: A microprocessor, coupled to the above-mentioned memory, is used to load an original program code. When the storage units to which the above-mentioned original program code is loaded are all non-defective storage units, then load the above-mentioned original program code into the above-mentioned memory. When the above-mentioned original program code When the storage unit where the program code is loaded includes at least one defective storage unit, the original program code is scanned, and the first breakpoint and the second breakpoint are determined before and after a defective address corresponding to the original program code in the defective storage unit , and move the segment program code between the first breakpoint and the second breakpoint to between the first address and the second address, and when the segment program code contains at least one executable instruction, provide a A connection instruction, used to connect the execution order of the above-mentioned section program code and the unmoved part of the above-mentioned original program code, and load the unmoved part of the above-mentioned original program code, the above-mentioned connection instruction and the above-mentioned section program code after moving to the above-mentioned memory , wherein the memory address corresponding to the program code between the above-mentioned first address and the above-mentioned second address does not include the above-mentioned defective address. 10. The memory processing system according to claim 9, wherein the second breaking point is after the last byte of the original program code. 11. The memory processing system as claimed in claim 9, characterized in that: said microprocessor also revises the reference address between the moved portion of the program code and the unmoved portion of the original program code, and the moved The reference address within the program code of the above section. 12. The memory processing system as claimed in claim 9, characterized in that: in the connection action of the above-mentioned microprocessor, the first unconditional branch instruction is inserted on the address of the first breakpoint, and the first unconditional branch instruction The destination address is the first address after the section program code is moved, and a second unconditional branch instruction is inserted into the second address after the section program code is moved, and the destination address of the second unconditional branch instruction is the second breakpoint . 13. The memory processing system according to claim 9, wherein said memory and said microprocessor are placed in the same chip. 14. The memory processing system as claimed in claim 9, characterized in that: the above-mentioned memory and the above-mentioned microprocessor are placed in different independent chips. 15. A method for preventing and treating local weakened memory, suitable for a memory loaded with an original program code, characterized in that it comprises the following steps: Examining the above-mentioned memory to find defective storage units with weakened functions in the above-mentioned memory; When the above-mentioned memory contains at least one storage unit with weakened function, the following steps are performed: Scanning the original program code, determining a first breakpoint and a second breakpoint before and after a defect address of the defective storage unit corresponding to the original program code; Move the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first storage unit and the second storage unit in the above-mentioned internal memory, between the above-mentioned first storage unit and the above-mentioned second storage unit does not contain the defective memory cells described above; and When the segment program code includes at least one executable instruction, link the execution sequence of the moved segment program code and the unmoved portion of the original program code. 16. The memory processing method for preventing local weakening as claimed in claim 15, characterized in that: the second breaking point is after the last byte of the original program code. 17. The method for preventing and treating local weakened memory as claimed in claim 15, characterized in that: it also includes a step: Correct the reference address between the above-mentioned section program code after moving and the unmoved part of the above-mentioned original program code. 18. The memory processing method for preventing local weakening as claimed in claim 17, characterized in that: the above-mentioned correction step is used to correct the relative addressing mode reference of the moved portion of the program code to the unmoved part of the above-mentioned original program code The address, and the relative addressing mode reference address and the absolute addressing mode reference address of the unmoved portion of the above original program code relative to the moved above segment program code are corrected. 19. The method for preventing and treating local weakened memory as claimed in claim 18, characterized in that: it also includes a step: Correct the absolute addressing mode reference address in the program code of the above segment after moving. 20. The memory processing method for preventing local weakening as claimed in claim 15, characterized in that: the step of scanning the above-mentioned original program code also includes the following steps: Read the above original program code in sequence; According to the composition of each instruction in the above original program code, output a plurality of separable breakpoints; and The first breaking point and the second breaking point are determined based on the defect address and the inserted connection command. 21. The memory processing method for preventing local weakening as claimed in claim 20, characterized in that: the step of reading the above-mentioned original program code in order also includes the following steps: Provide a first data table and a second data table, the above-mentioned first data table is used to record the branch destination address of the conditional branch instruction in the above-mentioned original program code, and the above-mentioned second data table is used to record the read address range; When the read instruction is a conditional branch instruction, recording the branch destination address of the conditional branch instruction in the first data table; When finishing reading an instruction, update the address range of the above-mentioned second data table; and When the read instruction is an end instruction or its address is within the address range of the above-mentioned second data table, and when the branch destination address of the above-mentioned first data table does not belong to the address range of the above-mentioned second data table, then according to the above The branch destination address of the first data table continues to be read. 22. The memory processing method for preventing local weakening as claimed in claim 15, characterized in that: in the above-mentioned connecting step, the first unconditional branch instruction is inserted at the address of the first breakpoint, and the purpose of the first unconditional branch instruction The address is the first storage unit after the section program code is moved, and a second unconditional branch instruction is inserted after the second storage unit after the section program code is moved, and the destination address of the second unconditional branch instruction is the second breaking point. 23. A memory processing system for processing a memory comprising a plurality of storage units and having stored an original program code, characterized in that it comprises: A microprocessor, coupled to the above-mentioned memory, is used to check whether the storage unit of the above-mentioned memory has a weakened storage unit, and when the weakened storage unit exists and has stored the above-mentioned original program code, then scan the above-mentioned original program code, Before and after the weakened storage unit corresponds to a weakened address of the original program code, determine a first breakpoint and a second breakpoint, and move the section program code between the first breakpoint and the second breakpoint to Between the first storage unit and the second storage unit in the above-mentioned internal memory, and when the above-mentioned section program code contains at least one executable instruction, connect the moved section of the above-mentioned program code and the unmoved part of the above-mentioned original program code The execution sequence of , wherein the defective storage unit is not included between the first storage unit and the second storage unit. 24. The memory processing system as claimed in claim 23, wherein the second breaking point is after the last byte of the original program code. 25. The memory processing system as claimed in claim 23, wherein the microprocessor is directly coupled to the memory. 26. The memory processing system as claimed in claim 23, characterized in that: said microprocessor also revises the reference address between the moved portion of the program code and the unmoved portion of the original program code, and the moved The reference address within the program code of the above section. 27. The memory processing system as claimed in claim 23, characterized in that: in the connection action of the above-mentioned microprocessor, the first unconditional branch instruction is inserted on the address of the first breakpoint, and the first unconditional branch instruction The destination address is the first storage unit after the section program code is moved, and a second unconditional branch instruction is inserted into the second storage unit after the section program code is moved, and the destination address of the second unconditional branch instruction is the above-mentioned second breaking point. 28. The memory processing system as claimed in claim 23, wherein the memory and the microprocessor are placed in the same chip. 29. The memory processing system as claimed in claim 23, characterized in that: said memory and said microprocessor are placed in different independent chips. 30. A memory processing method, applicable to a memory comprising a plurality of storage units and an original program code to be loaded into the memory, characterized in that it comprises the following steps: determining whether said memory contains defective memory cells; When the above-mentioned memory does not contain a defective storage unit or the above-mentioned original program code is not loaded in the defective address corresponding to the defective storage unit in the above-mentioned memory, then load the above-mentioned original program code into the above-mentioned memory; When the above-mentioned original program code is loaded into the defective address corresponding to at least one defective storage unit in the above-mentioned memory, the following steps are performed: Scanning the above-mentioned original program code, before and after a defect address corresponding to the above-mentioned original program code in the above-mentioned defective storage unit, determine a first breaking point and a second breaking point; loading the above original program code into the above memory; Load the section program code between the above-mentioned first breakpoint and the above-mentioned second breakpoint to between the first storage unit and the second storage unit, and the above-mentioned defect is not included between the above-mentioned first storage unit and the above-mentioned second storage unit storage unit; and When the segment program code includes at least one executable instruction, link the execution sequence of the segment program code located between the first storage unit and the second storage unit with other parts of the original program code. 31. The memory processing method according to claim 30, further comprising a step of: Correcting the reference address between the section program code located between the first storage unit and the second storage unit and other parts of the original program code. 32. The memory processing method as claimed in claim 31, characterized in that: said modifying step is used to correct the above-mentioned section program code between the above-mentioned first storage unit and the second storage unit for other parts of the above-mentioned original program code. Part of the relative addressing mode reference address, and modify the relative addressing mode reference address and absolute addressing mode of other parts of the above original program code for the above-mentioned segment program code located between the above-mentioned first storage unit and the second storage unit Reference address. 33. The memory processing method according to claim 32, further comprising a step of: Modifying the absolute addressing mode reference address in the segment program code located between the first storage unit and the second storage unit. 34. The memory processing method as claimed in claim 30, characterized in that: the step of scanning the above-mentioned original program code also includes the following steps: Read the above original program code in sequence; According to the composition of each instruction in the above original program code, output a plurality of separable breakpoints; and The first breaking point and the second breaking point are determined based on the defect address and the inserted connection command. 35. The memory processing method as claimed in claim 34, characterized in that: the step of reading the above-mentioned original program code in order also includes the following steps: Provide a first data table and a second data table, the above-mentioned first data table is used to record the branch destination address of the conditional branch instruction in the above-mentioned original program code, and the above-mentioned second data table is used to record the read address range; When the read instruction is a conditional branch instruction, recording the branch destination address of the conditional branch instruction in the first data table; When finishing reading an instruction, update the address range of the above-mentioned second data table; and When the read instruction is an end instruction or its address is within the address range of the above-mentioned second data table, and when the branch destination address of the above-mentioned first data table does not belong to the address range of the above-mentioned second data table, then according to the above The branch destination address of the first data table continues to be read. 36. The memory processing method according to claim 30, characterized in that: in the connecting step, the first unconditional branch instruction is inserted at the address of the first breaking point, and the destination address of the first unconditional branch instruction is the above-mentioned The first storage unit of the segment program code, and inserting a second unconditional branch instruction into the second storage unit of the segment program code, the destination address of the second unconditional branch instruction is the second breakpoint. 37. A memory processing system for processing a memory comprising a plurality of storage units, characterized in that it comprises: A microprocessor, coupled to the above-mentioned memory, is used to load an original program code. When the storage unit where the above-mentioned original program code is loaded contains at least one defective storage unit, the system can scan the above-mentioned original program code, and in the above-mentioned Determining a first breakpoint and a second breakpoint before and after a defective address corresponding to the original program code in the defective storage unit, and loading the original program code into the memory and loading the first breakpoint and the second breakpoint The segment program code between the first storage unit and the second storage unit, and when the segment program code contains at least one executable instruction, the connection is between the first storage unit and the second storage unit The execution order of the above segment program code and other parts of the above original program code, wherein the defective storage unit is not included between the first storage unit and the second storage unit. 38. The memory processing system as claimed in claim 37, wherein the second breaking point is after the last byte of the original program code. 39. The memory processing system as claimed in claim 37, characterized in that: said microprocessor also revises said section program code and other parts in said original program code between said first storage unit and second storage unit The reference address between, and the reference address in the section program code located between the first storage unit and the second storage unit. 40. The memory processing system as claimed in claim 37, characterized in that: in the above-mentioned connection operation of the above-mentioned microprocessor, a first unconditional branch instruction is inserted on the address of the first breakpoint, and the first unconditional branch instruction The destination address of the above-mentioned segment program code is the first storage unit, and a second unconditional branch instruction is inserted into the second storage unit of the above-mentioned segment program code. The destination address of the second unconditional branch instruction is the second break point. 41. The memory processing system according to claim 37, characterized in that: said memory and said microprocessor are placed in the same chip. 42. The memory processing system as claimed in claim 37, characterized in that: said memory and said microprocessor are placed in different independent chips. 43. A program code scanning processing method for determining a separable breaking point of an original program code, characterized in that: the above program code scanning processing method includes the following steps: Provide a first data table and a second data table, the first data table is used to record the address to be scanned related to the conditional branch instruction in the original program code, and the second data table is used to record the read address range ; Read the above original program code in sequence; When the read instruction is a conditional branch instruction, record the address to be scanned related to the conditional branch instruction in the above-mentioned first data table, and continue scanning according to the next address or branch destination address of the above-mentioned conditional branch instruction; updating the address range of the second data table as the instruction is read, and outputting a detachable breakpoint when at least one complete instruction is read; and When the read command is an end command or its address is within the address range of the second data table, continue reading according to an address to be scanned in the first data table, and transfer the address to be scanned from the first Datasheet removed. 44. The program code scanning processing method according to claim 43, characterized in that: the program code scanning processing method is to determine the movable segment program code when an original program code is loaded into a memory. 45. The program code scanning processing method according to claim 44, wherein the memory includes at least one defective storage unit. 46. The program code scanning processing method according to claim 43, wherein the address to be scanned related to the conditional branch instruction is the branch destination address of the conditional branch instruction. 47. The program code scanning processing method according to claim 43, wherein the address to be scanned related to the conditional branch instruction is the next address of the conditional branch instruction. 48. The program code scanning processing method as claimed in claim 43, further comprising a step of: When the read instruction is an unconditional branch instruction, continue scanning from the branch destination address of the above unconditional branch instruction. 49. The program code scanning processing method according to claim 43, characterized in that: when the read command is an end command or its address is within the address range of the second data table, and the first data table When there is no address to be scanned, the scan ends. 50. The program code scanning processing method according to claim 43, characterized in that: when the scanning ends, a continuous program code address that has not been scanned is determined as a data program code segment. 51. The program code scanning processing method according to claim 43, characterized in that: when the scanning ends, a continuous program code address that has not been scanned is determined as a data or stack program code segment. 52. The program code scanning processing method according to claim 43, characterized in that: when the scanning ends, a continuous program code address that has not been scanned is determined as a non-command segment.

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