CN116719728B - Multi-node regression testing method and device, medium and electronic equipment - Google Patents
Multi-node regression testing method and device, medium and electronic equipment Download PDFInfo
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- CN116719728B CN116719728B CN202310691641.5A CN202310691641A CN116719728B CN 116719728 B CN116719728 B CN 116719728B CN 202310691641 A CN202310691641 A CN 202310691641A CN 116719728 B CN116719728 B CN 116719728B
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Abstract
The application provides a multi-node regression testing method, a multi-node regression testing device, a medium and electronic equipment. The multi-node regression testing method comprises the following steps: acquiring a simulation test case set of a chip to be verified; based on a node verification mode and the simulation test case sets of the chip to be verified, obtaining the simulation test case sets on a plurality of machine nodes, wherein the node verification mode is a working mode of the machine nodes for verifying the simulation test case sets of the chip to be verified, and the node verification modes are at least two; and verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, wherein the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes. Compared with the traditional verification method, the multi-node regression testing method is high in verification efficiency.
Description
Technical Field
The application belongs to the field of chip verification, and relates to a testing method, in particular to a multi-node regression testing method, a multi-node regression testing device, a medium and electronic equipment.
Background
In the process of chip research and development, a large number of simulation tasks exist in the digital verification link, the number of regression simulation test cases can reach hundreds or even thousands, the personalized difference of different simulation test cases is obvious, the time consumption of some simulation test cases is short, the time consumption of some simulation test cases is long, and the known bug is confirmed to be clearly repaired through multiple iterations. In order to rapidly push out products, the related verification requirements are difficult to meet in a traditional serial verification mode, and the existing regression test method for chip verification has the problem of low verification efficiency.
Disclosure of Invention
The purpose of the application is to provide a multi-node regression testing method, a multi-node regression testing device, a multi-node regression testing medium and an electronic device, which are used for solving the problem of low verification efficiency in the existing verification method.
In a first aspect, the present application provides a multi-node regression testing method for chip verification, the multi-node regression testing method including: acquiring a simulation test case set of a chip to be verified; based on a node verification mode and the simulation test case sets of the chip to be verified, obtaining the simulation test case sets on a plurality of machine nodes, wherein the node verification mode is a working mode of the machine nodes for verifying the simulation test case sets of the chip to be verified, and the node verification modes are at least two; and verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, wherein the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes.
The multi-node regression testing method completes the verification work of the simulation test case set of the chip to be verified through a plurality of machine nodes together, so that the verification efficiency can be improved. And because the verification report and the simulation test case set on the machine node are both stored in the shared area between the machine nodes, the data related to verification in the machine node has the characteristic of easy management, and no additional labor cost is added. In addition, the multi-node regression testing method has multiple node verification modes, and different node verification modes can be flexibly selected according to actual requirements, so that the flexibility and the practicability of the multi-node regression testing method are improved.
In an embodiment of the present application, when the node verification mode is a first node verification mode, the implementation method for obtaining the simulation test case set on the plurality of machine nodes includes: copying the simulation test case sets of the chip to be verified to obtain a plurality of simulation test case sets of the chip to be verified, wherein the number of the simulation test case sets of the chip to be verified is the same as the number of the machine nodes; and distributing the simulation test case sets of the chips to be verified to obtain the simulation test case sets on the machine nodes, wherein the simulation test case sets on the machine nodes are the simulation test case sets of the chips to be verified.
In an embodiment of the present application, the multi-node regression testing method further includes: and merging the verification logs of the machine nodes to obtain merged reports, wherein the merged reports and the verification reports comprise coverage rate simulation test results of the simulation test case set on the machine nodes, and the simulation test results in the merged reports are more complete than the simulation test results in the verification reports.
In an embodiment of the present application, when the node verification mode is a second node verification mode, the implementation method for obtaining the simulation test case set on the plurality of machine nodes includes: the simulation test case set of the chip to be verified is subjected to blocking processing to obtain a plurality of simulation test case subsets of the simulation test case set of the chip to be verified, wherein the number of the simulation test case subsets is the same as the number of the machine nodes; and distributing the plurality of simulation test case subsets to obtain simulation test case sets on the machine nodes, wherein the simulation test case sets on each machine node are one simulation test case subset, and the simulation test case sets on each machine node are different.
In an embodiment of the present application, the machine node includes an operation state feedback control switch, and when a verification result of the simulation test case set on the machine node is a verification failure, the multi-node regression testing method further includes: generating a waveform generation command based on the opened running state feedback control switch and a verification log of the machine node, wherein the verification log of the machine node comprises a case name and configuration information of a simulation test case which fails to be verified.
In an embodiment of the present application, the machine node includes a coverage control switch, and the multi-node regression testing method further includes: and acquiring the coverage rate of the simulation test case set on the machine node based on the opened coverage rate control switch and the simulation test case set on the machine node.
In an embodiment of the present application, a method for implementing verification of a simulation test case set on a machine node by a plurality of threads of the machine node includes: generating a shared directory in the shared area, wherein the shared directory stores a project version library required by the machine node verification; based on the shared directory, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node.
In a second aspect, the present application provides a multi-node regression testing apparatus for chip verification, the multi-node regression testing apparatus comprising: the first simulation test case set acquisition module is used for acquiring a simulation test case set of a chip to be verified; the second simulation test case set acquisition module is used for acquiring simulation test case sets on a plurality of machine nodes based on a node verification mode and the simulation test case sets of the chip to be verified, wherein the node verification mode is a working mode of the machine nodes for verifying the simulation test case sets of the chip to be verified, and the node verification mode is at least two; the simulation test case set verification module is used for verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, and the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes.
In a third aspect, the present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the multi-node regression testing method of any of the first aspects of the present application.
In a fourth aspect, the present application provides an electronic device, including: a memory storing a computer program; and the processor is in communication connection with the memory and executes the multi-node regression testing method according to any one of the first aspect of the application when the computer program is called.
As described above, the multi-node regression testing method, device, medium and electronic equipment have the following beneficial effects:
the multi-node regression testing method completes the verification work of the simulation test case set of the chip to be verified through a plurality of machine nodes together, so that the verification efficiency can be improved. And because the verification report and the simulation test case set on the machine node are both stored in the shared area between the machine nodes, the data related to verification in the machine node has the characteristic of easy management, and no additional labor cost is added. In addition, the multi-node regression testing method has multiple node working modes, and different node verification modes can be flexibly selected according to actual requirements, so that the flexibility and the practicability of the multi-node regression testing method are improved.
Drawings
FIG. 1 is a schematic diagram of a multi-node verification system according to an embodiment of the present application.
FIG. 2 is a flow chart of a multi-node regression testing method according to an embodiment of the present application.
FIG. 3 shows a flowchart of an implementation method for obtaining a set of simulation test cases on multiple machine nodes according to an embodiment of the present application.
FIG. 4 shows a flowchart of an implementation method for obtaining a set of simulation test cases on multiple machine nodes according to an embodiment of the present application.
FIG. 5 is a flowchart of an implementation method for verifying a simulation test case set on a machine node through multiple threads of the machine node according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a multi-node regression testing apparatus according to an embodiment of the present application.
Description of element reference numerals
10. Multi-node verification system
110. Main machine node
120. Auxiliary machine node
600. Multi-node regression testing device
610. First simulation test case set acquisition module
620. Second simulation test case set acquisition module
630. Simulation test case set verification module
S11-S13 step
S21-S22 step
S31-S32 step
S41-S42 step
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that, the illustrations provided in the following embodiments merely illustrate the basic concepts of the application by way of illustration, and only the components related to the application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The following describes the technical solutions in the embodiments of the present application in detail with reference to the drawings in the embodiments of the present application.
As shown in fig. 1, the embodiment of the present application provides a multi-node verification system 10 on which the multi-node regression testing method may be performed, the multi-node verification system 10 including: the system comprises a main machine node 110 and a plurality of auxiliary machine nodes 120, wherein the main machine node 110 is in communication connection with the auxiliary machine nodes 120, the main machine node 110 and the auxiliary machine nodes 120 can be computer equipment, the main machine node 110 can be used for a user to check verification progress information of simulation test case sets on the auxiliary machine nodes 120, and the main machine node 110 can be also used for distributing the simulation test case sets on the auxiliary machine nodes 120 for verification of the auxiliary machine nodes 120.
As shown in fig. 2, the present embodiment provides a multi-node regression testing method for chip verification, which may be implemented by a processor of a computer device, and includes:
s11, acquiring a simulation test case set of the chip to be verified.
Alternatively, the chip to be verified may be a software-level chip design that needs to be verified. The simulation test case set of the chip to be verified is a regression simulation test case set of the chip to be verified, and the regression test can be used for ensuring that the chip to be verified which can normally work does not fade under the condition of change, for example, one function is newly added to the chip to be verified, the chip to be verified can not fade through performing the regression test, and the fading of the chip to be verified can refer to that the part of the chip to be verified which normally works is destroyed.
S12, based on a node verification mode and the simulation test case sets of the chip to be verified, the simulation test case sets on a plurality of machine nodes are obtained, wherein the node verification mode is a working mode of verifying the simulation test case sets of the chip to be verified by the machine nodes, and the node verification mode is at least two.
Optionally, the simulation test case set on the machine node may be a complete simulation test case set of the chip to be verified or a part of simulation test case set of the chip to be verified, the obtaining of the simulation test case set on the machine node may be related to the node verification mode, the node verification mode is a working mode in which the machine node verifies the simulation test case set of the chip to be verified, the node verification mode relates to an allocation process of the simulation test case set of the chip to be verified on the machine node, for example, the simulation test case set of the chip to be verified is a simulation test case set 1, a simulation test case set 2, a simulation test case set 3, a simulation test case set 4, the machine node includes a machine node 1 and a machine node 2, the node verification mode may be two, and when the node verification mode is a mode a, the simulation test case set 1 of the machine node 1 may include a simulation test case set 1 and a simulation test case set 2, the simulation test case set 2 relates to an allocation process of the simulation test case set of the chip to be verified, for example 1, the simulation test case set 2, and when the machine node verification mode is a mode 4, the machine node 1 and the machine node 2 may include a simulation test case set 4. In addition, the plurality of machine nodes may be a plurality of computers communicatively coupled to each other.
S13, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node. The validation report and the set of simulation test cases on the machine nodes are both stored in an area shared between a block of the machine nodes.
Optionally, the thread number of the machine node can be flexibly set according to the configuration condition of an actual single machine, and the use thread number of the machine node can be set by specifying the occupied processor core number.
Optionally, the verification report includes the number of simulation test cases currently passed, the number of simulation test cases not passed, the number of simulation test cases running, statistics of abnormal simulation test cases, test passing rate and progress completion rate, and the like.
Optionally, the verification report is stored in the storage area, and the multi-node regression testing method further includes: the verification report is automatically refreshed based on an update period of the verification report. For example, the update cycle interval of the verification report may be configured, defaulting to 1 hour, the host node may run a monitoring process, scan and count engineering directories in the storage area, and refresh and generate the verification report every other hour.
Optionally, the machine node includes an operation state feedback control switch, and when the verification result of the simulation test case set on the machine node is verification failure, the multi-node regression testing method further includes: generating a waveform generation command based on the opened running state feedback control switch and a verification log of the machine node, wherein the verification log of the machine node comprises a case name and configuration information of a simulation test case which fails to be verified. The configuration information may include the number of seeds, etc. The running state feedback control switch can be a code block on the machine node, and the running of the code block can be controlled through corresponding computer instructions, namely, the running state feedback control switch is started. When the running state feedback control switch is not started, a certain disk space can be saved, a certain verification speed can be improved, and the running state feedback control switch can be flexibly selected according to actual requirements. The waveform generation command may be, for example, a dump command to facilitate waveform generation.
Optionally, the machine node includes a coverage control switch, and the multi-node regression testing method further includes: and acquiring the coverage rate of the simulation test case set on the machine node based on the opened coverage rate control switch and the simulation test case set on the machine node. The coverage rate control switch can be a code block on the machine node, and the operation of the code block can be controlled through corresponding computer instructions, namely the coverage rate control switch is turned on. When the coverage rate control switch is not started, a certain disk space can be saved, a certain verification speed can be improved, and the coverage rate control switch can be flexibly selected according to actual requirements.
Optionally, the machine node further includes a failed re-running control switch, and the failed re-running control switch is used for automatically re-verifying and outputting waveforms when the failed re-running control switch is turned on and verification fails, so as to facilitate verification engineer checking. The failed re-running control switch can be a code block on the machine node, and the running of the code block can be controlled through corresponding computer instructions, namely, the failed re-running control switch is started. When the failed re-running control switch is not started, a certain disk space can be saved, a certain verification speed can be improved, and the failed re-running control switch can be flexibly selected according to actual requirements.
As can be seen from the above description, the multi-node regression testing method according to the present embodiment includes: the multi-node regression testing method is used for chip verification and comprises the following steps: acquiring a simulation test case set of a chip to be verified; based on a node verification mode and the simulation test case sets of the chip to be verified, obtaining the simulation test case sets on a plurality of machine nodes, wherein the node verification mode is a working mode of the machine nodes for verifying the simulation test case sets of the chip to be verified, and the node verification modes are at least two; and verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, wherein the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes.
The multi-node regression testing method completes the verification work of the simulation test case set of the chip to be verified through a plurality of machine nodes together, so that the verification efficiency can be improved. And because the verification report and the simulation test case set on the machine node are both stored in the shared area between the machine nodes, the data related to verification in the machine node has the characteristic of easy management, and no additional labor cost is added. In addition, the multi-node regression testing method has multiple node verification modes, and different node verification modes can be flexibly selected according to actual requirements, so that the flexibility and the practicability of the multi-node regression testing method are improved.
As shown in fig. 3, when the node verification mode is a first node verification mode, the embodiment provides an implementation method for obtaining simulation test case sets on a plurality of machine nodes, including:
s21, copying the simulation test case sets of the chip to be verified to obtain a plurality of simulation test case sets of the chip to be verified, wherein the number of the simulation test case sets of the chip to be verified is the same as the number of the machine nodes.
For example, when there are 4 machine nodes, 4 simulation test case sets of the chip to be verified can be obtained by performing copy processing on the simulation test case sets of the chip to be verified.
S22, distributing the simulation test case sets of the chips to be verified to obtain the simulation test case sets on the machine nodes, wherein the simulation test case sets on the machine nodes are the simulation test case sets of the chips to be verified. For example, 4 machine nodes are respectively allocated with a simulation test case set of the chip to be verified.
Optionally, when the node verification mode is a first node verification mode, verifying the simulation test case set on the machine node through multiple threads of the machine node to obtain a verification report of the simulation test case set on the machine node, where the implementation method includes: based on the random seed number on the machine node, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, wherein the verification report comprises coverage rate of the simulation test case set on the machine node.
Because the random seed numbers on the machine nodes are different, the coverage rates of the simulation test case sets on different machine nodes are also different, and therefore, under the first node verification mode, the different coverage rates of the simulation test case sets of the chip to be verified can be collected.
Optionally, when the node verification mode is a first node verification mode, the multi-node regression testing method further includes: and merging the verification reports of the simulation test case sets on the machine nodes to obtain merged reports, wherein the verification reports and the merged reports both comprise coverage rate simulation test results of the simulation test case sets on the machine nodes, and the simulation test results in the merged reports are more complete than the simulation test results in the verification reports. The more complete simulation test results may mean that the coverage rate of the simulation test case set is higher.
Optionally, the implementation method for merging the verification reports of the simulation test case set on the machine node may be: and combining the verification reports of the simulation test case set on the machine node through scripts to obtain combined reports, wherein detailed details of the embodiment of the scripts are not repeated.
As shown in fig. 4, when the node verification mode is the second node verification mode, the embodiment provides an implementation method for obtaining simulation test case sets on a plurality of machine nodes, including:
s31, blocking the simulation test case set of the chip to be verified to obtain a plurality of simulation test case subsets of the simulation test case set of the chip to be verified, wherein the number of the simulation test case subsets is the same as the number of the machine nodes.
For example, when the simulation test case set of the chip to be verified includes a simulation test case subset 1, a simulation test case subset 2, a simulation test case subset 3, and a simulation test case subset 4, when there are 4 machine nodes, the simulation test case set of the chip to be verified may be divided into 4 blocks, where the first block includes the simulation test case subset 1, the second block includes the simulation test case subset 2, the third block includes the simulation test case subset 3, and the fourth block includes the simulation test case subset 4.
S32, distributing the simulation test case subsets to obtain simulation test case sets on the machine nodes, wherein the simulation test case sets on the machine nodes are one simulation test case subset, and the simulation test case sets on the machine nodes are different.
For example, when there are four subsets of simulation test cases and four machine nodes, each machine node is assigned a subset of the simulation test cases.
As can be seen from the above description, the implementation method for obtaining the simulation test case set on the plurality of machine nodes according to the present embodiment includes: the simulation test case set of the chip to be verified is subjected to blocking processing to obtain a plurality of simulation test case subsets of the simulation test case set of the chip to be verified, wherein the number of the simulation test case subsets is the same as the number of the machine nodes; and distributing the plurality of simulation test case subsets to obtain simulation test case sets on the machine nodes, wherein the simulation test case sets on each machine node are one simulation test case subset, and the simulation test case sets on each machine node are different. By performing blocking processing on the simulation test case set of the chip to be verified and performing distribution processing on the sub-simulation test case subsets, the simulation test case set on the machine node is only a part of the simulation test case set of the chip to be verified, and each machine node only needs to complete the distributed simulation test case, so that the overall efficiency of the machine node for processing the simulation test case of the chip to be verified can be further improved.
In an embodiment of the present invention, when the node verification mode is the third node verification mode, the simulation test case set of the chip to be verified may be simulation test case sets of different versions of the chip to be verified, and the simulation test case set on the machine node may be simulation test case sets of corresponding versions of the chip to be verified. For example, when the simulation test case set of the chip to be verified with three versions is ver1, ver2 and ver3, respectively, the simulation test case set with three machine nodes is machine node 1, machine node 2 and machine node 3, respectively, the simulation test case set on machine node 1 may be ver1, the simulation test case set on machine node 2 may be ver2, and the simulation test case set on machine node 3 may be ver3.
As shown in fig. 5, the implementation method for verifying the simulation test case set on the machine node through multiple threads of the machine node includes:
s41, generating a shared directory in the shared area, wherein the shared directory stores an item version library required by the machine node verification.
Optionally, the implementation method for generating the shared directory in the shared area includes: and generating a shared directory in the shared area through script. Directory switch instructions may be encapsulated in the script to cause the item version library to be stored in the shared directory. The shared directory refers to a directory in which the machine nodes all have read-write permission. In addition, the project version library may include environment files required for the machine node verification, which are not described in detail herein.
S42, based on the shared directory, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node.
According to the above description, the implementation method for verifying the simulation test case set on the machine node through the multiple threads of the machine node includes: generating a shared directory in the shared area, wherein the shared directory stores a project version library required by the machine node verification; based on the shared directory, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node. By generating the shared directory in the shared area, the machine node can directly execute the verification task in the shared directory, and the condition that the machine node can execute the verification work only by switching the directory in the verification process is avoided.
The protection scope of the multi-node regression testing method according to the embodiment of the present application is not limited to the execution sequence of the steps listed in the embodiment, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art made by the principles of the present application are included in the protection scope of the present application.
As shown in fig. 6, the present embodiment provides a multi-node regression testing apparatus 600, the multi-node regression testing apparatus 600 being used for chip verification, the multi-node regression testing apparatus 600 comprising:
the first simulation test case set obtaining module 610 is configured to obtain a simulation test case set of a chip to be verified.
The second simulation test case set obtaining module 620 is configured to obtain simulation test case sets on a plurality of machine nodes based on a node verification mode and a simulation test case set of the chip to be verified, where the node verification mode is a working mode in which the machine node verifies the simulation test case set of the chip to be verified, and the node verification mode has at least two modes.
The simulation test case set verification module 630 is configured to verify, by using multiple threads of the machine node, the simulation test case set on the machine node to obtain a verification report of the simulation test case set on the machine node, where the verification report and the simulation test case set on the machine node are both stored in a region shared between one piece of machine nodes.
In the multi-node regression testing apparatus 600 provided in this embodiment, the first simulation test case set obtaining module 610, the second simulation test case set obtaining module 620, and the simulation test case set verification module 630 are in one-to-one correspondence with steps S11-S13 of the multi-node regression testing method shown in fig. 2, and are not described in detail herein.
As can be seen from the above description, the multi-node regression testing apparatus 600 of the present embodiment completes the verification of the simulation test case set of the chip to be verified together through a plurality of machine nodes, so that the verification efficiency can be improved. And because the verification report and the simulation test case set on the machine node are both stored in the shared area between the machine nodes, the data related to verification in the machine node has the characteristic of easy management, and no additional labor cost is added. In addition, the multi-node regression testing device is provided with a plurality of node verification modes, and different node verification modes can be flexibly selected according to actual requirements, so that the flexibility and the practicability of the multi-node regression testing device are improved.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.
The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the purposes of the embodiments of the present application. For example, functional modules/units in various embodiments of the present application may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.
Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The embodiment provides an electronic device, which comprises a memory, wherein a computer program is stored in the memory; and the processor is in communication connection with the memory and executes the multi-node regression testing method shown in FIG. 2 when the computer program is called. And the display is in communication connection with the processor and the memory and is used for displaying a related GUI interactive interface of the multi-node regression testing method shown in FIG. 2.
Embodiments of the present application also provide a computer-readable storage medium. Those of ordinary skill in the art will appreciate that all or part of the steps in the method implementing the above embodiments may be implemented by a program to instruct a processor, where the program may be stored in a computer readable storage medium, where the storage medium is a non-transitory (non-transitory) medium, such as a random access memory, a read only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape (magnetic tape), a floppy disk (floppy disk), an optical disk (optical disk), and any combination thereof. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
Embodiments of the present application may also provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions described in accordance with the embodiments of the present application are produced in whole or in part. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.).
The computer program product is executed by a computer, which performs the method according to the preceding method embodiment. The computer program product may be a software installation package, which may be downloaded and executed on a computer in case the aforementioned method is required.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.
Claims (10)
1. The multi-node regression testing method is characterized in that the multi-node regression testing method is used for chip verification and comprises the following steps:
acquiring a simulation test case set of a chip to be verified;
based on a node verification mode and simulation test case sets of the chips to be verified, obtaining simulation test case sets on a plurality of machine nodes, wherein the node verification mode is a working mode that the machine nodes verify the simulation test case sets of the chips to be verified, the node verification mode is at least two, the node verification mode is a first node verification mode or a second node verification mode, the simulation test case sets of the chips to be verified are subjected to copying processing in the first node verification mode, the simulation test case sets on the machine nodes are the simulation test case sets of the chips to be verified, the simulation test case sets of the chips to be verified are subjected to blocking processing in the second node verification mode, the simulation test case sets on the machine nodes are simulation test case subsets of the simulation test case sets of the chips to be verified, and the simulation test case sets on the machine nodes are different;
and verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, wherein the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes.
2. The multi-node regression testing method of claim 1, wherein when the node verification mode is a first node verification mode, the method for obtaining the simulation test case sets on the plurality of machine nodes comprises:
copying the simulation test case sets of the chip to be verified to obtain a plurality of simulation test case sets of the chip to be verified, wherein the number of the simulation test case sets of the chip to be verified is the same as the number of the machine nodes;
and distributing the simulation test case sets of the chips to be verified to obtain the simulation test case sets on the machine nodes, wherein the simulation test case sets on the machine nodes are the simulation test case sets of the chips to be verified.
3. The multi-node regression testing method of claim 2, further comprising: and merging the verification reports of the simulation test case sets on the machine nodes to obtain merged reports, wherein the verification reports and the merged reports both comprise coverage rate simulation test results of the simulation test case sets on the machine nodes, and the simulation test results in the merged reports are more complete than the simulation test results in the verification reports.
4. The multi-node regression testing method of claim 1, wherein when the node verification mode is a second node verification mode, the method for obtaining the simulation test case sets on the plurality of machine nodes comprises:
the simulation test case set of the chip to be verified is subjected to blocking processing to obtain a plurality of simulation test case subsets of the simulation test case set of the chip to be verified, wherein the number of the simulation test case subsets is the same as the number of the machine nodes;
and distributing the plurality of simulation test case subsets to obtain simulation test case sets on the machine nodes, wherein the simulation test case sets on each machine node are one simulation test case subset, and the simulation test case sets on each machine node are different.
5. The multi-node regression testing method of claim 1, wherein the machine node includes a run state feedback control switch, and wherein when the verification result of the simulation test case set on the machine node is a verification failure, the multi-node regression testing method further comprises: generating a waveform generation command based on the opened running state feedback control switch and a verification log of the machine node, wherein the verification log of the machine node comprises a case name and configuration information of a simulation test case which fails to be verified.
6. The multi-node regression testing method of claim 1 wherein the machine node includes a coverage control switch, the multi-node regression testing method further comprising: and acquiring the coverage rate of the simulation test case set on the machine node based on the opened coverage rate control switch and the simulation test case set on the machine node.
7. The multi-node regression testing method of claim 1, wherein the method for validating the set of simulation test cases on the machine node by the plurality of threads of the machine node comprises:
generating a shared directory in the shared area, wherein the shared directory stores a project version library required by the machine node verification;
based on the shared directory, verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node.
8. A multi-node regression testing apparatus, wherein the multi-node regression testing apparatus is for chip verification, the multi-node regression testing apparatus comprising:
the first simulation test case set acquisition module is used for acquiring a simulation test case set of a chip to be verified;
the second simulation test case acquisition module is used for acquiring simulation test case sets on a plurality of machine nodes based on a node verification mode and the simulation test case sets of the chips to be verified, wherein the node verification mode is a working mode of verifying the simulation test case sets of the chips to be verified by the machine nodes, the node verification mode is at least two, the node verification mode is a first node verification mode or a second node verification mode, the simulation test case sets of the chips to be verified are subjected to replication processing in the first node verification mode, the simulation test case sets on the machine nodes are the simulation test case sets of the chips to be verified, the simulation test case sets of the chips to be verified are subjected to blocking processing in the second node verification mode, the simulation test case sets on the machine nodes are simulation test case subsets of the simulation test case sets of the chips to be verified, and the simulation test case sets on the machine nodes are different;
the simulation test case set verification module is used for verifying the simulation test case set on the machine node through a plurality of threads of the machine node to obtain a verification report of the simulation test case set on the machine node, and the verification report and the simulation test case set on the machine node are both stored in a region shared among the machine nodes.
9. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the multi-node regression testing method of any of claims 1-7.
10. An electronic device, the electronic device comprising:
a memory storing a computer program;
a processor communicatively coupled to said memory for executing the multi-node regression testing method of any one of claims 1-7 when said computer program is invoked;
and the display is in communication connection with the processor and the memory and is used for displaying a related GUI interactive interface of the multi-node regression testing method.
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