CN116719685A - Functional safety testing methods, devices and equipment under chip transient faults - Google Patents

Abstract

Embodiments of this specification relate to the technical field of transient fault safety testing of chips, and in particular to a functional safety testing method, device and equipment for a chip under transient faults. The method includes: obtaining a hit of a chip under a transient fault simulation test. The functional unit set and the corresponding test vector set when hit; sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set; control the irradiation source to continuously irradiate the chip ; Input each test vector in the test vector sequence into the chip in stages, and detect the fault detection results of each functional unit under each input; according to the fault detection of each functional unit under each input As a result, the functional test results of the chip under each input are determined. The embodiments of this specification can improve the testing efficiency of functional safety testing of chips under transient faults.

Description

Functional safety testing methods, devices and equipment under chip transient faults

Technical field

This specification relates to the technical field of functional safety testing of chips, and in particular to a method, device and equipment for functional safety testing of chips under transient faults.

Background technique

Electromagnetic interference or crosstalk can easily cause transient failures of the chip. The functional safety test of a chip under transient fault is an important means to check the correctness of its functional safety design and process manufacturing. However, the current test efficiency of functional safety testing of chips under transient faults needs to be improved urgently.

Contents of the invention

The purpose of the embodiments of this specification is to provide a method, device and equipment for functional safety testing of chips under transient faults, so as to improve the testing efficiency of functional safety testing of chips under transient faults.

In order to achieve the above objectives, on the one hand, embodiments of this specification provide a functional safety testing method under transient faults of a chip, including:

Obtain the set of functional units that were hit under the transient fault simulation test of the chip and the corresponding set of test vectors when they were hit;

Sorting the test vector set into a test vector sequence based on the contribution and coverage to the functional unit set;

Control the irradiation source to continuously irradiate the chip;

Input each test vector in the test vector sequence into the chip in batches in order, and detect the fault detection result of each functional unit under each input;

According to the fault detection results of each functional unit under each input, the functional test result of the chip under each input is determined.

In the functional safety testing method under chip transient fault in the embodiment of this specification, the test vector set is sorted into a test vector sequence based on the contribution and coverage of the functional unit set, including:

Determine the contribution of each test vector in the test vector set to the functional unit set;

Arrange the test vector set into an initial sequence according to the degree of contribution;

Determine the coverage of the functional unit set by the subsequence consisting of each remaining test vector in the initial sequence and the one with the largest contribution respectively;

Determine the coverage of the subsequence with the largest coverage and the subsequence composed of each remaining test vector in the initial sequence to the functional unit set;

Recurse in sequence until the length of the currently obtained subsequence with the largest coverage meets the preset conditions;

The subsequence with the largest coverage currently obtained is used as the test vector sequence.

In the functional safety testing method for chip transient faults in the embodiment of this specification, the preset conditions include:

The subsequence with the largest coverage currently obtained achieves full coverage.

In the functional safety testing method under chip transient fault in the embodiment of this specification, determining the contribution of each test vector in the test vector set to the functional unit set includes:

According to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set;

Among them, C _i is the contribution of the i-th test vector in the test vector set to the functional unit set, N _ik is the probability that the i-th test vector hits the k-th functional unit in the functional unit set, and M is the Describe the size of the functional unit collection.

In the functional safety testing method of the chip under transient fault in the embodiment of this specification, each test vector in the test vector sequence is input into the chip in stages, and the fault of each functional unit under each input is detected. Test results include:

Sequentially select an unselected test vector from the test vector sequence as the target test vector;

Input the target test vector to the chip;

Detect the fault detection results of each of the functional units under the input of the target test vector;

When the conditions for continued test execution are met, the above steps are repeated until all test vectors in the test vector sequence have been selected.

In the functional safety testing method of a chip under transient fault in the embodiment of this specification, the functional test results of the chip under each input are determined based on the fault detection results of each functional unit under each input, including:

Accumulate the number of faulty functional units detected in the functional unit set under the current input;

Determine whether the accumulated value reaches the preset threshold;

When the accumulated value reaches the threshold, the accumulated value is output.

In the functional safety test method of the chip under transient fault in the embodiment of this specification, the functional test result of the chip under each input is determined based on the fault detection result of each functional unit under each input, and also includes:

When the accumulated value does not reach the threshold, determine whether there is an unselected test vector in the target test vector;

If there is an unselected test vector in the target test vector, continue to perform the test.

In the functional safety testing method of a chip under transient fault in the embodiment of this specification, the chip includes an automotive grade chip.

On the other hand, embodiments of this specification also provide a functional safety testing device under transient chip faults, including:

The acquisition module is used to obtain the set of functional units that are hit under the transient fault simulation test of the chip and the corresponding test vector set when it is hit;

A sorting module, configured to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set;

An irradiation module, used to control the irradiation source to continuously irradiate the chip;

A detection module, configured to input each test vector in the test vector sequence into the chip in batches in order, and detect the fault detection result of each functional unit under each input;

A determining module, configured to determine the functional test result of the chip under each input based on the fault detection result of each functional unit under each input.

On the other hand, embodiments of this specification also provide a computer device, including a memory, a processor, and a computer program stored on the memory. When the computer program is run by the processor, the instructions of the above method are executed. .

On the other hand, embodiments of this specification also provide a computer storage medium on which a computer program is stored. When the computer program is run by the processor of the computer device, the instructions for the above method are executed.

On the other hand, embodiments of this specification also provide a computer program product. The computer program product includes a computer program. When the computer program is run by a processor of a computer device, it executes instructions for the above method.

It can be seen from the technical solutions provided by the above embodiments of this specification that the embodiments of this specification can perform a transient fault simulation test on the chip in advance to obtain each functional unit that is hit under the transient fault simulation test and the functions used when it is hit. Each test vector corresponds to a set of functional units and a set of test vectors, thereby screening out functional units with weak security as test objects, and streamlining the number of test vectors used, thus improving the function of the chip under transient faults. Security testing efficiency. Moreover, by sorting the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set, and testing in batches according to the order of the test vector sequence, it is beneficial to hit the transient state that has a great impact on the expected safety target earlier. fault, which can further improve the efficiency of functional safety testing of chips under transient faults.

Description of the drawings

In order to more clearly explain the embodiments of this specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some of the embodiments recorded in this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting any creative effort. In the attached picture:

Figure 1 shows a schematic diagram of the application scenario of the functional safety testing device in some embodiments of this specification;

Figure 2 shows a flow chart of the functional safety testing method under chip transient fault in some embodiments of this specification;

Figure 3 shows a flow chart of sorting the test vector set in the method shown in Figure 2;

Figure 4 shows a flow chart of divided testing according to the ordering of the test vector sequence in the method shown in Figure 2;

Figure 5 shows a flow chart for determining the corresponding functional test results according to the fault detection results under each input in the method shown in Figure 2;

Figure 6 shows a schematic diagram of the functional safety test under transient fault of the chip in an exemplary embodiment of this specification;

Figure 7 shows a schematic diagram of a functional unit (see the cross mark in the figure) detected under one input in an exemplary embodiment of this specification;

Figure 8 shows a structural block diagram of a functional safety test device under chip transient fault in some embodiments of this specification;

Figure 9 shows a structural block diagram of a computer device in some embodiments of this specification.

[Explanation of reference symbols]

11. Irradiation source;

12. Functional safety testing device;

81. Get module

82. Sorting module;

83. Irradiation module;

84. Detection module;

85. Determine the module;

902. Computer equipment;

904. Processor;

906. Memory;

908. Driving mechanism;

910. Input/output interface;

912. Input device;

914. Output device;

916. Presentation equipment;

918. Graphical user interface;

920. Network interface;

922. Communication link;

924. Communication bus.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described The embodiments are only some of the embodiments of this specification, but not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of this specification.

The embodiments of this specification relate to the transient fail-safe test technology of chips, which can be adapted to the transient fail-safe test of automobile-grade chips, and can also be applied to the transient fail-safe test of non-auto-grade chips. Among them, the car-grade chip can be, for example, a car-grade safety MCU chip, a car-grade gateway control MCU chip, an engine powertrain control chip, etc.

Figure 1 shows the application scenario of the functional safety test device in some embodiments of this specification; in this application scenario, the irradiation source 11 can also be called a radiation source, which means that it can emit laser or heavy ions, etc. Electromagnetic radiation device is used to irradiate chips to facilitate functional safety testing of simulated chips under electromagnetic interference. In an exemplary embodiment, the irradiation source 11 may be a laser, a radiation generator, or the like. The functional safety testing device 12 is an integrated circuit testing equipment that can be used to detect the functional integrity of the integrated circuit. Specifically, the functional safety test device 12 can obtain the set of hit functional units of the chip under the transient fault simulation test and the set of test vectors corresponding to the hits; based on the contribution and coverage of the set of functional units, The test vector set is sorted into a test vector sequence; the irradiation source 11 is controlled to continuously irradiate the chip; each test vector in the test vector sequence is input into the chip in sequence, and each test vector under each input is detected. The fault detection results of the functional units; and then determine the functional test results of the chip under each input based on the fault detection results of each functional unit under each input.

In an exemplary embodiment, the functional safety testing device may be, for example, a combination of a test machine and a host computer, or a test machine integrated with the data analysis and processing function of the host computer.

The embodiment of this specification provides a functional safety testing method under chip transient fault, which can be applied to the above-mentioned functional safety testing device side. Refer to Figure 2. In some embodiments, the functional safety testing device may include the following steps: :

Step 201: Obtain the set of hit functional units of the chip under the transient fault simulation test and the set of corresponding test vectors when the chip is hit.

Step 202: Sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set.

Step 203: Control the irradiation source to continuously irradiate the chip.

Step 204: Input each test vector in the test vector sequence into the chip in batches in sequence, and detect the fault detection results of each functional unit for each input.

Step 205: Determine the functional test results of the chip under each input based on the fault detection results of each functional unit under each input.

In the embodiment of this specification, a transient fault simulation test can be performed on the chip in advance to obtain each functional unit that is hit under the transient fault simulation test and each test vector used when it is hit, and correspondingly serve as a functional unit Collection and test vector collection, thereby screening out functional units with weak security as test objects, and streamlining the number of test vectors used, thus improving the efficiency of functional safety testing of chips under transient faults. Moreover, by sorting the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set, and testing in batches according to the order of the test vector sequence, it is beneficial to hit the transient state that has a great impact on the expected safety target earlier. fault, which can further improve the efficiency of functional safety testing of chips under transient faults.

Transient fault simulation testing refers to simulating the integrated circuit test environment through programming (for example, using simulation tools such as VCS), injecting transient faults into each functional unit of the chip for fault simulation, and using each of the full test vectors in turn. The test vector is used for simulation testing, and the hit functional units and the test vectors used when they are hit are counted. Among them, the hit functional unit refers to the functional unit that is identified as having a transient fault or has a high probability of having a transient fault in the transient fault simulation test. For example, in an exemplary embodiment, during the transient fault simulation test, if the functional unit A of the chip finds a fault after inputting the test vector R, then the functional unit A is one of the hit functional units, and the test vector R is then is the corresponding test vector when functional unit A is hit.

In this way, by conducting transient fault simulation tests in advance to screen functional units and test vectors, it is possible to ensure that functional units with weak functional safety in the chip can participate in the actual functional test, which is beneficial to ensuring the functional safety of the chip under transient faults. Test accuracy.

It should be noted that the test pattern (test pattern) is a test input signal. In the functional safety test scenario under chip transient fault, the test pattern can be used to detect the functional safety of the chip. In some embodiments, a test vector generation tool (such as TetraMax, etc.) may be used to generate the test vector.

In the embodiments of this specification, functional units refer to various modules or units in the chip that are divided according to functional roles. Each module or unit can implement a specific function. For example, taking a CPU chip as an example, a CPU chip can include arithmetic units, controllers, registers, etc. Then the arithmetic unit, controller, and register can all be used as a functional unit. In actual application scenarios, the functional units in the chip can adjust the division granularity according to actual needs (for example, the division can be more detailed).

Referring to Figure 3, in some embodiments, sorting the test vector set into a test vector sequence based on the contribution and coverage to the functional unit set may include the following steps:

Step 301: Determine the contribution of each test vector in the test vector set to the functional unit set.

The contribution of a test vector to a set of functional units refers to the contribution of a single test vector hitting a functional unit in a transient fault simulation test; the more functional units a single test vector hits, the greater the contribution of the test vector. The greater the contribution, the higher the importance of the test vector in functional safety testing.

In some embodiments, according to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set. Among them, C _i is the contribution of the i-th test vector in the test vector set to the functional unit set, N _ik is the probability that the i-th test vector hits the k-th functional unit in the functional unit set, and M is the Describe the size of the functional unit set (i.e. the number of elements in the functional unit set).

Step 302: Arrange the test vector set into an initial sequence according to the degree of contribution.

Arranging the test vector set into an initial sequence according to the contribution degree means: arranging the test vector set into the initial sequence according to the descending order of the contribution degree.

Step 303: Determine the coverage of the functional unit set by the subsequence consisting of the one with the largest contribution and each of the remaining test vectors in the initial sequence.

Coverage refers to: in the transient fault simulation test, the proportion of functional units hit by a single test vector subsequence relative to the test vector set. The greater the coverage, the higher the importance of the test vector in functional safety testing.

For example, in an exemplary embodiment, assume that the order of contribution degrees corresponding to each test vector is C ₁ > C ₂ > K > K > C _i > K > C _n , and the corresponding initial test vector sequence (i.e., initial sequence) is {V ₁ ,V ₂ ,K,V _i ,K,V _n }; Since C ₁ is the maximum contribution, the test vector V ₁ corresponding to C ₁ is the one with the maximum contribution. At this time, in V ₁ , Among V ₂ ,K,V _i ,K,V _n , the remaining test vectors include {V ₂ ,K,V _i ,K,V _n }, then the test vector V ₁ can be the same as {V ₂ ,K,V _i , Each test vector in K,V _n } forms a subsequence; for example, {V ₁ ,V ₂ }, {V ₁ ,V ₃ },…,{V ₁ ,V _i },…,{V ₁ ,V _n }.

Based on the transient fault simulation test of the chip, the coverage rate of each subsequence can be calculated. For example, in the above exemplary embodiment, assume that the chip has 10 functional units F ₁ to F ₁₀ ; if the functional units hit by V ₁ , V ₂ , and V ₃ are respectively:

V ₁ : F ₁ , F ₂ , F ₅ , F ₈ , F ₁₀ ;

V ₂ : F ₁ , F ₂ , F ₆ , F ₈ ;

V ₃ : F ₁ , F ₄ , F ₇ ;

Then the total hit functional units of the subsequence {V ₁ , V ₂ } are: F ₁ , F ₂ , F ₅ , F ₆ , F ₈ , F ₁₀ ;

Then the total hit functional units of the subsequence {V ₁ , V ₃ } are: F ₁ , F ₂ , F ₄ , F ₅ , F ₇ , F ₈ , F ₁₀ ;

Therefore, the coverage of subsequence {V ₁ , V ₃ } is greater than the coverage of subsequence {V ₁ , V ₂ }.

Step 304: Determine the coverage of the subsequence with the largest coverage and the subsequence composed of each remaining test vector in the initial sequence to the functional unit set.

Taking the exemplary embodiment in step 303 as an example, if the subsequence {V ₁ , V ₃ } is {V ₁ , V ₂ }, {V ₁ , V ₃ }, ..., {V ₁ , V _i }, ..., The subsequence with the largest coverage in {V ₁ ,V _n }; then in {V ₁ ,V ₂ ,K,V _i ,K,V _n }, the remaining test vectors include {V ₂ ,V ₄ , K,V _i ,K,V _n }, then the subsequence {V ₁ ,V ₃ } can form a new subsequence with each test vector in {V ₂ ,V ₄ ,K,V _i ,K,V _n } Sequence; for example {V ₁ ,V ₃ ,V ₂ }, {V ₁ ,V ₃ ,V ₄ },…, {V ₁ ,V ₃ ,V _i },…, {V ₁ ,V ₃ ,V _n } , and on this basis, calculate the coverage of each new subsequence on the set of functional units;

If the subsequence {V ₁ ,V ₃ ,V ₂ } is {V ₁ ,V ₃ ,V ₂ },{V ₁ ,V ₃ ,V ₄ },…,{V ₁ ,V ₃ ,V _i },…, The subsequence with the largest coverage in {V ₁ , V ₃ , V _n }, then in {V ₁ , V ₂ , K, _Vi , K, V _n }, the remaining test vectors include {V ₄ , K,V _i ,K,V _n }, then the subsequence {V ₁ ,V ₃ ,V ₂ } can form a new subsequence with each test vector in {V ₄ ,K,V _i ,K,V _n } Sequence; for example {V ₁ ,V ₃ ,V ₂ ,V ₅ },{V ₁ ,V ₃ ,V ₂ ,V ₆ },…,{V ₁ ,V ₃ ,V ₂ ,V _i },…,{ V ₁ , V ₃ , V ₂ , V _n }, and on this basis, the coverage rate of each new subsequence on the set of functional units is calculated, and the sequence is repeated.

Step 305: Determine whether the length of the currently obtained subsequence with the largest coverage meets the preset condition. If satisfied, execute step 306; otherwise, execute step 304 to continue sorting.

Preset conditions can be customized as needed. For example, in some embodiments, the preset condition may be to achieve full coverage of the currently obtained subsequence with the largest coverage (that is, the coverage is 100%). In this way, it is conducive to further streamlining the test vector, thereby conducive to further testing efficiency; if the length of the currently obtained subsequence with the maximum coverage is R=S-1 (R is the length of the currently obtained subsequence with the maximum coverage, S is the length of the initial sequence), the last remaining test vector in the initial sequence needs to participate in the test to ensure test accuracy.

Step 306: Use the currently obtained subsequence with the largest coverage as the test vector sequence.

For example, taking the exemplary embodiments in steps 303 and 304, if the currently obtained subsequence with the largest coverage {V ₁ , V ₃ , V ₂ , V ₅ , K, _Vi , K, V _{n- 1} } has a length of n-1, then the remaining test vector V _n in the initial sequence can be added to {V ₁ ,V ₃ ,V ₂ ,V ₅ ,K,V _i ,K,V _n-1 }, thus forming the test vector sequence {V ₁ ,V ₃ ,V ₂ ,V ₅ ,K,V _i ,K,V _n-1 ,V _n }.

Therefore, when the test vector set is sorted into a test vector sequence based on the contribution and coverage of the functional unit set, and the tests are performed in the order of the test vector sequence, not only can the test vectors that have a greater impact on chip security be hit earlier, Transient faults can end the test early, thereby saving test time and improving test efficiency. It can also avoid missing functional units with weak safety performance, thus ensuring test accuracy.

Referring to Figure 4, in some embodiments, inputting each test vector in the test vector sequence into the chip in stages, and detecting the fault detection results of each functional unit under each input, may include Following steps:

Step 401: Sequentially select an unselected test vector from the test vector sequence as a target test vector.

For example, in an exemplary embodiment, if all test vectors in the test vector sequence {V ₁ , V ₂ , K, _Vi , K, V _n } have not been selected, then the test vector V can be selected this time ₁ ; If in the test vector sequence {V ₁ , V ₂ , K, V _i , K, V _n }, except the test vector V ₁ , no test vector has been selected, then the test vector V ₂ can be selected this time; if the test vector In the sequence {V ₁ , V ₂ , K, _Vi , K, V _n }, except for the test vector V ₁ , V ₂ , no test vector has been selected. Then the test vector V ₃ can be selected this time; the sequence is repeated.

Step 402: Input the target test vector to the chip.

Obviously, inputting the target test vector to the chip is performed under the background or premise that the irradiation source is continuously irradiating the chip.

Step 403: Detect the fault detection results of each functional unit under the input of the target test vector.

The functional safety test device itself is equipped with a fault detection device, which can detect whether the output of each functional unit of the chip is the expected output after inputting the target test vector. If the output of a functional unit is the expected output, it means that the functional unit is in the target test vector. There is no fault under the input, otherwise it means that the functional unit has a fault under the input of the target test vector, and the functional unit with the fault can be marked (for example, the functional unit with the fault is marked with a cross in Figure 6 or Figure 7).

Step 404: Determine whether the conditions for continued test execution are met. If satisfied, execute step 401 to continue testing; otherwise, end the test.

Among them, the test continuation execution conditions can be customized. For example, in one embodiment, the test continuation execution condition may be: the total number of functional units with detected faults under the current target test vector is lower than a set threshold, and there are unselected targets in the test vector sequence. test vector. If the total number of functional units with detected faults under the current target test vector is lower than the set threshold, it indicates that the expected safety objectives of the chip will not be affected in this scenario, and the test can continue.

Referring to Figure 5, in some embodiments, determining the functional test results of the chip under each input based on the fault detection results of each functional unit under each input may include the following steps:

Step 501: Accumulate the number of faulty functional units detected in the functional unit set under the current input.

Step 502: Determine whether the accumulated value reaches a preset threshold. If the accumulated value reaches the preset threshold, step 503 is executed; otherwise, step 504 is executed.

Step 503: Output the accumulated value.

By outputting the accumulated value, relevant personnel can be reminded of the severity of the chip failure in a quantitative manner, so that relevant personnel can deal with it.

Step 504: Determine whether there is an unselected test vector in the target test vector. If there is an unselected test vector in the target test vector, step 505 is executed; otherwise, the test ends.

Step 505: Continue to execute the test.

Corresponding to the above-mentioned functional safety testing method under chip transient fault, as shown in Figure 8, in some embodiments, the functional safety testing device of the embodiment of this specification may include:

The acquisition module 81 is used to obtain the set of hit functional units of the chip under the transient fault simulation test and the set of corresponding test vectors when the chip is hit;

A sorting module 82, configured to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set;

Irradiation module 83, used to control the irradiation source to continuously irradiate the chip;

The detection module 84 is used to input each test vector in the test vector sequence into the chip in stages, and detect the fault detection result of each functional unit under each input;

The determination module 85 is configured to determine the functional test result of the chip under each input based on the fault detection result of each functional unit under each input.

For the convenience of description, when describing the above device, the functions are divided into various units and described separately. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and/or hardware.

It should be noted that in the embodiments of this specification, the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) are involved. data, etc.), are all information and data that have been authorized by the user and fully authorized by all parties.

An embodiment of this specification also provides a computer device. As shown in Figure 9, in some embodiments of the present description, the computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each A processing unit can implement one or more hardware threads. Computer device 902 may also include any memory 906 for storing any kind of information such as code, settings, data, etc., in one embodiment, a computer program on memory 906 and executable on processor 904. When the computer program is run by the processor 904, it can execute the instructions of the functional safety testing method under chip transient fault described in any of the above embodiments. Without limitation, for example, the memory 906 may include any one or more combinations of the following: any type of RAM, any type of ROM, flash memory device, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of computer device 902. In one instance, when processor 904 executes associated instructions stored in any memory or combination of memories, computer device 902 may perform any operation of the associated instructions. Computer device 902 also includes one or more drive mechanisms 908 for interacting with any memory, such as a hard disk drive, an optical disk drive, and the like.

Computer device 902 may also include an input/output interface 910 (I/O) for receiving various inputs (via input device 912) and for providing various outputs (via output device 914). One particular output mechanism may include a presentation device 916 and an associated graphical user interface 918 (GUI). In other embodiments, the input/output interface 910 (I/O), the input device 912 and the output device 914 may not be included, and may only be used as a computer device in the network. Computer device 902 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922 . One or more communication buses 924 couple together the components described above.

Communication link 922 may be implemented in any manner, such as through a local area network, a wide area network (eg, the Internet), a point-to-point connection, etc., or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc. governed by any protocol or combination of protocols.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products of some embodiments of the specification. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processor to produce a machine such that the instructions executed by the processor of the computer or other programmable data processor produce a use A device for realizing the functions specified in one process or multiple processes of the flowchart and/or one block or multiple blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processor to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operating steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

In a typical configuration, a computer device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-permanent storage in computer-readable media, random access memory (RAM), and/or non-volatile memory in the form of read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer-readable media includes both persistent and non-volatile, removable and non-removable media that can be implemented by any method or technology for storage of information. Information may be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), and read-only memory. (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, Magnetic tape cassettes, disk storage or other magnetic storage devices or any other non-transmission medium can be used to store information that can be accessed by computer equipment. According to the definition in this specification, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

Those skilled in the art will appreciate that embodiments of the present specification may be provided as methods, systems, or computer program products. Accordingly, embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Furthermore, embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of this specification may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Embodiments of the present description may also be practiced in distributed computing environments where tasks are performed by remote processors connected through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including storage devices.

It should also be understood that in the embodiment of this specification, the term "and/or" is only an association relationship describing associated objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship.

Each embodiment in this specification is described in a progressive manner. The same and similar parts between the various embodiments can be referred to each other. Each embodiment focuses on its differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For relevant details, please refer to the partial description of the method embodiment.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the embodiments of this specification. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine different embodiments or examples and features of different embodiments or examples described in this specification unless they are inconsistent with each other.

The above descriptions are only examples of the present application and are not intended to limit the present application. To those skilled in the art, various modifications and variations may be made to this application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application shall be included in the scope of the claims of this application.

Claims (12)

1. A functional safety testing method under transient fault of a chip, which is characterized by including: Obtain the set of functional units that were hit under the transient fault simulation test of the chip and the corresponding set of test vectors when they were hit; Sorting the test vector set into a test vector sequence based on the contribution and coverage to the functional unit set; Control the irradiation source to continuously irradiate the chip; Input each test vector in the test vector sequence into the chip in batches in order, and detect the fault detection result of each functional unit under each input; According to the fault detection results of each functional unit under each input, the functional test result of the chip under each input is determined. 2. The functional safety testing method under chip transient fault according to claim 1, wherein the test vector set is sorted into a test vector sequence based on the contribution and coverage of the functional unit set. ,include: Determine the contribution of each test vector in the test vector set to the functional unit set; Arrange the test vector set into an initial sequence according to the degree of contribution; Determine the coverage of the functional unit set by the subsequence consisting of each remaining test vector in the initial sequence and the one with the largest contribution respectively; Determine the coverage of the subsequence with the largest coverage and the subsequence composed of each remaining test vector in the initial sequence to the functional unit set; Recurse in sequence until the length of the currently obtained subsequence with the largest coverage meets the preset conditions; The subsequence with the largest coverage currently obtained is used as the test vector sequence. 3. The functional safety testing method under chip transient fault according to claim 2, characterized in that the preset conditions include: The subsequence with the largest coverage currently obtained achieves full coverage. 4. The functional safety testing method under chip transient fault according to claim 2, wherein determining the contribution of each test vector in the test vector set to the functional unit set includes: According to the formula Calculate the contribution of each test vector in the test vector set to the functional unit set; Among them, C _i is the contribution of the i-th test vector in the test vector set to the functional unit set, N _ik is the probability that the i-th test vector hits the k-th functional unit in the functional unit set, and M is the Describe the size of the functional unit collection. 5. The functional safety testing method under transient fault of the chip according to claim 1, characterized in that each test vector in the test vector sequence is input into the chip in sequence, and each test vector is detected. The fault detection results of each functional unit include: Sequentially select an unselected test vector from the test vector sequence as the target test vector; Input the target test vector to the chip; Detect the fault detection results of each of the functional units under the input of the target test vector; When the conditions for continued test execution are met, the above steps are repeated until all test vectors in the test vector sequence have been selected. 6. The functional safety testing method of a chip under transient fault according to claim 5, characterized in that the function of the chip under each input is determined based on the fault detection results of each functional unit under each input. Test results include: Accumulate the number of faulty functional units detected in the functional unit set under the current input; Determine whether the accumulated value reaches the preset threshold; When the accumulated value reaches the threshold, the accumulated value is output. 7. The functional safety testing method of a chip under transient fault according to claim 6, characterized in that the function of the chip under each input is determined based on the fault detection results of each functional unit under each input. Test results also include: When the accumulated value does not reach the threshold, determine whether there is an unselected test vector in the target test vector; If there is an unselected test vector in the target test vector, continue to perform the test. 8. The functional safety testing method under transient fault of a chip according to claim 1, wherein the chip includes an automotive grade chip. 9. A functional safety testing device for chip transient faults, characterized by including: The acquisition module is used to obtain the set of functional units that are hit under the transient fault simulation test of the chip and the corresponding test vector set when it is hit; A sorting module, configured to sort the test vector set into a test vector sequence based on the contribution and coverage of the functional unit set; An irradiation module, used to control the irradiation source to continuously irradiate the chip; A detection module, configured to input each test vector in the test vector sequence into the chip in batches in order, and detect the fault detection result of each functional unit under each input; A determining module, configured to determine the functional test result of the chip under each input based on the fault detection result of each functional unit under each input. 10. A computer device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that when the computer program is run by the processor, it executes any one of claims 1-8 instructions for the method. 11. A computer storage medium with a computer program stored thereon, characterized in that when the computer program is run by a processor of a computer device, the instructions of the method according to any one of claims 1-8 are executed. 12. A computer program product, characterized in that the computer program product includes a computer program, and when the computer program is run by a processor, the instructions of the method according to any one of claims 1-8 are executed.