CN116701290A

CN116701290A - Data processing device, method, electronic device, and storage medium

Info

Publication number: CN116701290A
Application number: CN202310589796.8A
Authority: CN
Inventors: 卢垚松; 张钊; 吴曾
Original assignee: Kunlun Core Beijing Technology Co ltd
Current assignee: Kunlun Core Beijing Technology Co ltd
Priority date: 2023-05-23
Filing date: 2023-05-23
Publication date: 2023-09-05

Abstract

The present disclosure provides a data processing apparatus, relates to the technical field of artificial intelligence, and in particular relates to the technical field of chips. The device comprises: a first storage unit; a first processor configured to execute at least one instruction corresponding to the first code data to: setting a target cache region on a second storage unit by using a preset driver interface; transmitting second code data corresponding to the second processor, wherein the second code data includes print function code segment data; in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit. The disclosure also provides a data processing method, electronic equipment and a storage medium.

Description

Data processing device, method, electronic device, and storage medium

Technical Field

The present disclosure relates to the field of artificial intelligence, and in particular, to the field of chip technology. More particularly, the present disclosure provides a data processing apparatus, method, electronic device, and storage medium.

Background

With the development of artificial intelligence technology, heterogeneous electronic devices with a central processor (central Processing Unit, CPU) and a graphics processor (Graphics Processing Unit, GPU) may be used to process data.

Disclosure of Invention

The present disclosure provides a data processing apparatus, method, device, and storage medium.

According to an aspect of the present disclosure, there is provided a data processing apparatus comprising: a first storage unit; a first processor configured to execute at least one instruction corresponding to the first code data to: setting a target cache region on a second storage unit by using a preset driver interface; transmitting second code data corresponding to the second processor, wherein the second code data includes print function code segment data; in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit.

According to another aspect of the present disclosure, there is provided a data processing apparatus comprising: a second storage unit; a second processor configured to execute at least one instruction corresponding to the second code data to: acquiring the position of a target cache region positioned in a second storage unit; executing the printing function code segment data to obtain an initial output result corresponding to the printing function code segment data; adjusting the data format of the initial output result to obtain a target output result; and writing the target output result into the target cache area.

According to another aspect of the present disclosure, there is provided an electronic device including at least one of: the first data processing device is provided by the disclosure; and a second data processing device, wherein the second data processing device is another data processing device provided by the present disclosure.

According to another aspect of the present disclosure, there is provided a data processing method, the method comprising: setting a target cache region on a second storage unit by using a preset driver interface; transmitting second code data corresponding to the second processor, wherein the second code data includes print function code segment data; in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit.

According to another aspect of the present disclosure, there is provided a data processing method, the method comprising: acquiring the position of a target cache region positioned in a second storage unit; executing the printing function code segment data to obtain an initial output result corresponding to the printing function code segment data; adjusting the data format of the initial output result to obtain a target output result; and writing the target output result into the target cache area.

According to another aspect of the present disclosure, there is provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method provided in accordance with the present disclosure.

According to another aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a method provided according to the present disclosure.

According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements a method provided according to the present disclosure.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic block diagram of a data processing apparatus according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of obtaining code data according to one embodiment of the present disclosure;

FIG. 3 is a schematic block diagram of a data processing apparatus according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a heterogeneous electronic device according to one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an electronic device according to one embodiment of the present disclosure;

FIG. 6 is a schematic flow chart diagram of a data processing method according to one embodiment of the present disclosure;

FIG. 7 is a schematic flow chart diagram of a data processing method according to one embodiment of the present disclosure; and

fig. 8 is a block diagram of an electronic device to which a data processing method may be applied according to one embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In the software development process, developers may use some auxiliary functions for debugging the software code. The auxiliary functions can help developers find out abnormality generated during software running, help correct logic errors of codes, and provide richer testing means for the developers.

These auxiliary functions may include, for example, formatting string printing, breakpoint debugging, etc. In order to achieve debugging accuracy, input data, output results and various intermediate results in the running process of the software program can be obtained. Under the condition of accurately acquiring related data or results, the efficiency of software program development and testing can be effectively improved.

However, the heterogeneous electronic device may include a host side (host) and a device side (device). The host side may include, for example, a central processor, and may send the data to be processed and the associated code to the device side. The device side may include, for example, a graphics processor or a neural network processor, and may use the data to be processed and the related code to perform data processing, or may output a processing result. The host side can acquire the processing result. The device side may have a storage unit that is accessible by the host side and the device side. It is difficult to directly perform large-scale data transmission between the processor on the host side and the processor on the device side.

In some embodiments, the device side does not have the ability to directly expose information to the developer, making it difficult for the developer to efficiently optimize the code of the device side. The debugging information generated in the code execution process of the equipment end can be displayed to the developer through the host end. The processor on the device side and the processor on the host side may use dedicated interrupt functions and interrupt handling functions to transfer debug information. However, if the processor on the device side does not have these functions, it is difficult for a developer to efficiently debug.

For some heterogeneous electronic devices with simpler functions or results, adding an interrupt function or a debug function may increase design difficulty and cost.

In order to efficiently optimize the respective processors at the host side and at the device side, the present disclosure provides a data processing apparatus, which will be described in detail below.

Fig. 1 is a schematic block diagram of a data processing apparatus according to one embodiment of the present disclosure.

As shown in fig. 1, the apparatus 10 may include a first storage unit 101 and a first processor 102.

The first storage unit 101 may be a Main Memory (Main Memory).

The first processor 102 is configured to execute at least one instruction corresponding to the first code data to: and setting a target buffer area on the second storage unit by using a preset driver interface. And transmitting second code data corresponding to the second processor. In response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit.

In an embodiment of the disclosure, the first processor may be a central processor, and the second processor may be a graphics processor, a neural network processor, or a kunlun core (XPU) or the like.

In an embodiment of the disclosure, if the second processor is a graphics processor, the second storage unit may be a video memory (GDDR).

In an embodiment of the present disclosure, the second code data may include print function code segment data. The print function code segment data may correspond to print function printf (). For example, after the code of the device side is initially written, a developer may empirically add at least one print function to the code to obtain various data or results during the execution of the code of the device side.

According to the embodiment of the invention, in the process of executing the first code data, the interrupt is not required to be triggered, and the stable and efficient operation of the processor can be maintained. The software program development process of the heterogeneous electronic device is expedited without relying on the debugging functions or interrupt functions of hardware (e.g., a processor).

In addition, through the embodiment of the disclosure, the first processor can acquire the output result related to the printing function from the second processor in various forms, the architecture of the processor does not need to be iterated, and related codes can be optimized efficiently under the condition that the hardware design cost is not increased.

In addition, through the embodiment of the disclosure, the first processor can load the output result of any data type to the first storage unit, so that the requirements of developers can be fully met, and the optimization and development flow of codes are quickened.

It will be appreciated that the apparatus of the present disclosure is described above and the code data will be further described below.

Fig. 2 is a schematic diagram of obtaining code data according to one embodiment of the present disclosure.

In the embodiment of the disclosure, according to the original code written by the developer, the first initial code data corresponding to the first processor and the second initial code data corresponding to the second processor can be obtained.

In an embodiment of the present disclosure, the first processor may be further configured to: first initial code data corresponding to the first processor and second initial code data corresponding to the second processor are traversed. The first initial code data may include initial call code segment data.

As shown in fig. 2, the first processor may run a compiler 203. Compiler 203 may be a program. The compiler 203 may traverse the first initial code data 2020 and the second initial code data 2120. Compiler 203 may determine the location of the initial call code segment data in first initial code data 2020. The compiler 203 may also determine if there is initial print function code segment data in the second initial code data 2120. It will be appreciated that various programs having scanned or modified code data may also be used to traverse the first initial code data and the second initial code data, which is not limiting of the present disclosure.

In an embodiment of the present disclosure, the first processor may be further configured to: and in response to determining that the initial print function code segment data exists in the second initial code data, adding the initial buffer setting code segment data and the initial result acquisition code segment data to the first initial code data to obtain the first code data. The initial buffer area sets the code segment data before the initial calling code segment data, the initial result obtaining code segment data after the initial calling code segment data, and the initial printing function code segment data corresponds to the printing function code segment data.

As shown in fig. 2, in the case where the compiler 203 determines that the initial print function code segment data exists in the second initial code data, the initial buffer setting code segment data may be added before the initial call code segment data, or the initial result acquisition code segment data may be added after the initial call function code segment. Next, the compiler 203 may compile the first initial code data to which the code segment data is added, resulting in first code data 2021. The first code data 2021 may include call code segment data. The first code data 2021 may also include cache region setting code section data and result acquisition code section data. The cache region setting code segment data may be located before the calling code segment data and the result acquisition code segment data may be located after the calling code segment data.

In an embodiment of the present disclosure, the first processor may be further configured to: and adding the code segment data acquired by the initial buffer area to second initial code data to obtain second code data. The initial buffer area obtains code segment data before the initial print function code segment data.

As shown in fig. 2, in the case where the compiler 203 determines that the initial print function code segment data exists in the second initial code data, the initial buffer acquisition code segment data may be added before the initial print function code segment data. Next, the compiler 203 may compile the second initial code data to which the code segment data is added, resulting in second code data 2121. The second code data 2121 may include cache area acquisition code segment data and print function code segment data. The buffer acquisition code segment data may precede the print function code segment data.

In an embodiment of the present disclosure, the first processor may be further configured to execute at least one instruction corresponding to the cache region setting code segment data, so as to set the target cache region in the second storage unit using the preset driver interface.

In an embodiment of the present disclosure, the first processor may be further configured to execute at least one instruction corresponding to the calling code segment data in order to send second code data corresponding to the second processor.

In an embodiment of the present disclosure, the first processor may be further configured to execute at least one instruction corresponding to the result acquisition code segment data so as to load the target output result corresponding to the print function code segment data from the target buffer to the first storage unit.

According to the embodiment of the disclosure, a developer can obtain the output result corresponding to the printing function under the condition that the first processor or the second processor does not have a debugging function or an interrupt function without adjusting the written code, so that the learning cost and the labor cost of the developer are reduced, and the software development efficiency of the heterogeneous electronic device is greatly improved.

It will be appreciated that the above description has been given taking the initial code data as uncompiled data as an example. The present disclosure is not limited thereto and the initial code data may be compiled data.

It will be appreciated that the manner in which the code data is obtained is described above and that the target output results will be further described below.

In an embodiment of the present disclosure, the first processor may be further configured to: visual information corresponding to the target output result is generated. For example, the visual information may be presented on a display device to enable a developer to obtain a target output.

It will be appreciated that the above has described a data processing apparatus comprising a first processor and that a data processing apparatus comprising a second processor will be described below.

Fig. 3 is a schematic block diagram of a data processing apparatus according to another embodiment of the present disclosure.

As shown in fig. 3, the apparatus 31 may include a second storage unit 311 and a second processor 312.

The second storage unit 311 may be a video memory.

The second processor 312 may be configured to execute at least one instruction corresponding to the second code data to: and acquiring the position of the target cache region in the second storage unit. Executing the printing function code segment data to obtain an initial output result corresponding to the printing function code segment data. And adjusting the data format of the initial output result to obtain a target output result. And writing the target output result into the target cache area.

In embodiments of the present disclosure, the second processor may be a graphics processor, a neural network processor, or various processors such as a Kunlun core.

The second code data may be, for example, the second code data 2121 described above. The second code data may include print function code segment data and buffer acquisition code segment data.

In an embodiment of the disclosure, the second processor may receive the second code data sent by the first processor.

In an embodiment of the disclosure, the second processor may be further configured to execute at least one instruction corresponding to the second code data, so as to process the input data to obtain the output data.

In the embodiment of the present disclosure, the print function code segment data may correspond to, for example, a print function printf ().

By the embodiment of the disclosure, the stable and efficient operation of the processor can be kept in the process of executing the second code data. The second processor may not have a debug function or an interrupt function to accelerate the software program development process of the heterogeneous electronic device.

It will be appreciated that the second processor of the present disclosure is described above, and that the second processor of the present disclosure will be further described below in connection with the first processor.

Fig. 4 is a schematic diagram of a heterogeneous electronic device according to one embodiment of the present disclosure.

As shown in fig. 4, heterogeneous electronic device 400 may include, for example, means 40 and means 41. Device 40 may be the host side and device 41 may be the device side. The apparatus 40 may comprise a first processor and the apparatus 41 may comprise a second processor.

In an embodiment of the present disclosure, the first processor may be configured to execute at least one instruction corresponding to the above-described cache region setting code section to implement operation S4010. In operation S4010, a target buffer is set on the second storage unit using a preset driving degree interface. For example, the first processor may determine a continuous address space on the second storage unit as the target buffer area using the preset driving level interface.

In an embodiment of the present disclosure, the first processor may be configured to execute at least one instruction corresponding to the above-described calling code segment data to implement operation S4020. In operation S4020, second code data corresponding to the second processor is transmitted. For example, the second code data includes print function code segment data. As described above, the second code data includes the cache area acquisition code data. After the second code data is obtained, the second processor may execute associated instructions, as further described below.

In an embodiment of the present disclosure, the second processor may be configured to execute at least one instruction corresponding to the cache area acquisition code data to implement operation S4110. In operation S4110, the location of the target buffer area located in the second storage unit is acquired. For example, the starting address offset of the consecutive address space in the second memory location may be obtained to determine the location of the target buffer.

In an embodiment of the present disclosure, the second processor may be configured to execute at least one instruction corresponding to the print function code segment data in order to implement operation S4120. In operation S4120, the print function is executed, resulting in an initial output result corresponding to the print function code segment data. For example, the print function printf () can take as an initial output result the intermediate result currently being computed by the second processor. The intermediate result may be a formatted string.

In an embodiment of the present disclosure, the second processor may be configured to execute at least one instruction to implement operation S4130. In operation S4130, the data format of the initial output result is adjusted to obtain the target output result. For example, the data format of the initial output result may be consistent with the data format of the second processor. The data format of the initial output result may be adjusted to be consistent with the first processor.

In an embodiment of the present disclosure, the second processor may be configured to execute at least one instruction to implement operation S4140. In operation S4140, the target output result is written into the target buffer. For example, the target output result may be written into the above-described consecutive address section.

In an embodiment of the present disclosure, the second processor may be configured to execute at least one instruction to implement operation S4150. In response to determining that the execution of the second code data is completed, a message indicating that the second processor has executed the second code data is transmitted in operation S4150. For example, after the second processor has executed all instructions corresponding to the second code data, a message may be sent indicating that the second processor has executed the second code data.

The first processor may then execute associated instructions in response to receiving the message, as will be further described below.

In an embodiment of the present disclosure, the first processor may be configured to execute at least one instruction corresponding to the result acquisition code segment data to implement operation S4030. In operation S4030, the target output result corresponding to the print function code segment data is loaded from the target buffer to the first storage unit. For example, the target output results may be loaded from a continuous address space of the video memory to the main memory.

In an embodiment of the present disclosure, the first processor may be further configured to execute at least one instruction to implement operation S4040. In operation S4040, visual information corresponding to the target output result is generated. For example, the visual information may be presented on a display device to enable a developer to obtain a target output.

It is understood that the print function code segment data may be at least one. In the case where the print function code segment data is plural, the target buffer may store plural target output results.

It will be appreciated that the data processing apparatus of the present disclosure has been described above and that an electronic device comprising the data processing apparatus will be described below.

Fig. 5 is a schematic diagram of an electronic device according to one embodiment of the present disclosure.

As shown in fig. 5, the apparatus 500 may include a first data processing device 50 and a second data processing device 51.

In the disclosed embodiment, the first data processing device 50 may be the device 10 described above.

In the disclosed embodiment, the second data processing device 51 may be the device 31 described above.

It will be appreciated that the present disclosure has been described above with the example of apparatus 500 comprising two data processing devices. The present disclosure is not limited thereto and the electronic device may also include the apparatus 10 described above. Alternatively, the electronic device may comprise the above-mentioned means 31.

It will be appreciated that the data processing apparatus of the present disclosure is described above and the data processing method of the present disclosure will be described below.

Fig. 6 is a schematic flow chart diagram of a data processing method according to one embodiment of the present disclosure.

As shown in fig. 6, the method 600 may include operations S6010 to S6030.

In operation S6010, a target buffer is set on the second storage unit using a preset driver interface.

In operation S6020, second code data corresponding to the second processor is transmitted. In an embodiment of the disclosure, the second code data includes print function code segment data;

in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit in operation S6030.

It will be appreciated that at least one instruction corresponding to the method 600 may be executed using the first processor 102 described above.

In some embodiments, the method 600 may further comprise: first initial code data corresponding to the first processor and second initial code data corresponding to the second processor are traversed. For example, the first initial code data includes initial call code segment data, which corresponds to the call code segment data. And in response to determining that the initial print function code segment data exists in the second initial code data, adding the initial buffer setting code segment data and the initial result acquisition code segment data to the first initial code data to obtain the first code data. For example, the initial buffer setting code segment data is located before the initial call code segment data, the initial result acquisition code segment data is located after the initial call code segment data, and the initial print function code segment data corresponds to the print function code segment data. And adding the code segment data acquired by the initial buffer area to second initial code data to obtain second code data. For example, the initial buffer acquisition code segment data precedes the initial print function code segment data.

In some embodiments, the method 600 may further comprise: visual information corresponding to the target output result is generated.

It will be appreciated that the method that the first processor may implement is described above and that the method that the second processor implements will be described below.

Fig. 7 is a schematic flow chart diagram of a data processing method according to one embodiment of the present disclosure.

As shown in fig. 7, the method 700 may include operations S7110 to S7140.

In operation S7110, a location of the target buffer located in the second storage unit is acquired.

In operation S7120, print function code segment data is executed, resulting in an initial output result corresponding to the print function code segment data.

In operation S7130, the data format of the initial output result is adjusted to obtain the target output result.

In operation S7140, the target output result is written into the target buffer.

It will be appreciated that at least one instruction corresponding to the method 700 may be executed using the second processor 312 described above.

In some embodiments, the method 700 may further comprise: in response to determining that the second code data is executed, a message is sent indicating that the second code data has been executed.

In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

Fig. 8 illustrates a schematic block diagram of an example electronic device 700 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 8, the apparatus 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to the bus 804.

Various components in device 800 are connected to I/O interface 805, including: an input unit 806 such as a keyboard, mouse, etc.; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, or the like. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The computing unit 801 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the respective methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 800 via ROM 802 and/or communication unit 809. When a computer program is loaded into RAM 803 and executed by computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display)) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A data processing apparatus comprising:

a first storage unit;

a first processor configured to execute at least one instruction corresponding to the first code data to:

setting a target cache region on a second storage unit by using a preset driver interface;

transmitting second code data corresponding to a second processor, wherein the second code data comprises print function code segment data;

in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to the first storage unit.

2. The apparatus of claim 1, wherein the first code data comprises calling code segment data,

the first processor is further configured to execute at least one instruction corresponding to the call code segment data to send the second code data corresponding to the second processor.

3. The apparatus of claim 2, the first processor further configured to:

traversing first initial code data corresponding to the first processor and second initial code data corresponding to the second processor, wherein the first initial code data comprises initial calling code segment data, and the initial calling code segment data corresponds to the calling code segment data;

in response to determining that initial print function code segment data exists in the second initial code data, adding initial buffer setting code segment data and initial result acquisition code segment data to the first initial code segment data to obtain the first code data, wherein the initial buffer setting code segment data is located before the initial call code segment data, the initial result acquisition code segment data is located after the initial call code segment data, and the initial print function code segment data corresponds to the print function code segment data;

and adding the initial buffer area acquisition code segment data to the second initial code segment data to obtain the second code data, wherein the initial buffer area acquisition code segment data is positioned before the initial printing function code segment data.

4. The apparatus of claim 1, wherein the first processor is further configured to:

and generating visual information corresponding to the target output result.

5. A data processing apparatus comprising:

a second storage unit;

a second processor configured to execute at least one instruction corresponding to the second code data to:

acquiring the position of a target cache region positioned in the second storage unit;

executing the printing function code segment data to obtain an initial output result corresponding to the printing function code segment data;

adjusting the data format of the initial output result to obtain a target output result;

and writing the target output result into the target cache region.

6. The apparatus of claim 5, wherein the second processor is further configured to:

in response to determining that the second code data is executed, a message is sent indicating that the second processor has executed the second code data.

7. An electronic device comprising at least one of:

a first data processing apparatus, wherein the first data processing apparatus is a data processing apparatus as claimed in any one of claims 1 to 4;

a second data processing apparatus, wherein the second data processing apparatus is a data processing apparatus as claimed in any one of claims 5 to 6.

8. A data processing method, comprising:

in response to receiving a message indicating that the second processor has executed the second code data, a target output result corresponding to the print function code segment data is loaded from the target cache area to a first storage unit.

9. The method of claim 8, further comprising

Traversing first initial code data corresponding to a first processor and second initial code data corresponding to a second processor, wherein the first initial code data comprises initial calling code segment data, and the initial calling code segment data corresponds to the calling code segment data;

10. The method of claim 8, further comprising:

and generating visual information corresponding to the target output result.

11. A data processing method, comprising:

acquiring the position of a target cache region positioned in a second storage unit;

and writing the target output result into the target cache region.

12. The method of claim 11, further comprising:

in response to determining that the second code data is executed, a message is sent indicating that the second code data has been executed.

13. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 8 to 12.

14. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 8 to 12.

15. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 8 to 12.