CN116560936A - Anomaly monitoring method, coprocessor and computing device - Google Patents

Abstract

A method for anomaly monitoring, the method is applied to a mainboard including a main processor and a coprocessor, the main processor and the coprocessor are coupled through a bus, and during the abnormality monitoring process, the coprocessor carries out chip monitoring on the mainboard Level abnormal monitoring, the chip-level abnormal monitoring includes at least one of the main processor in the motherboard or the bus coupled to the main processor and the coprocessor for abnormal monitoring, and when it is detected that the motherboard has a chip-level abnormal , the coprocessor generates a chip-level exception on the motherboard. In this way, not only abnormality monitoring can be realized, but also because the coprocessor performs chip-level abnormality monitoring on the motherboard, this can make the coprocessor usually not affected by the network transmission delay or the operating load of the motherboard during the abnormality monitoring process, so as to This can improve the accuracy and reliability of anomaly monitoring.

Description

Anomaly monitoring method, coprocessor and computing device

technical field

The present application relates to the field of computer technology, in particular to an abnormality monitoring method, a coprocessor and a computing device.

Background technique

Computing devices such as servers may run abnormally after running for a long time. For example, after some hardware devices in the computing device have been running for a long time, due to aging or electromagnetic interference, etc., the operating data of the computing device may be erroneous, causing the computing device to go down.

At present, a dedicated monitoring device is usually configured for the computing device, and the monitoring device can periodically send a connection request to the computing device based on the Secure Shell (SSH) protocol, and when the connection is successful, the monitoring device determines that the computing device does not go down machine, and when a connection failure occurs, the monitoring device determines that the computing device is down. However, when the computing device is running normally, if the connection request fails to respond in time due to a large transmission delay or a heavy load on the computing device during network transmission, the monitoring device may misjudge that the computing device is down. machine, reducing the accuracy of monitoring.

Therefore, how to improve the accuracy and reliability of abnormality monitoring of computing devices has become an important problem that needs to be solved urgently.

Contents of the invention

The present application provides an abnormality monitoring method, a coprocessor, computing equipment, an abnormality monitoring device, a computer-readable storage medium and a computer program product, which are used to improve the accuracy and reliability of abnormality monitoring for computing equipment.

In the first aspect, the present application provides an abnormality monitoring method, which is applied to a main board including a main processor and a coprocessor, the main processor and the coprocessor are coupled through a bus, and during the abnormality monitoring process, The coprocessor performs chip-level anomaly monitoring on the mainboard. The chip-level anomaly monitoring includes anomaly monitoring on the main processor in the mainboard, or anomalous monitoring on the bus coupling the main processor and the coprocessor, or simultaneously The processor and the bus perform abnormality monitoring; when a chip-level abnormality occurs on the mainboard, the coprocessor generates a chip-level abnormality on the mainboard.

In this way, not only abnormality monitoring can be realized, but also because the coprocessor performs chip-level abnormality monitoring on the motherboard, this can make the coprocessor usually not affected by the network transmission delay or the operating load of the motherboard during the abnormality monitoring process, so as to This can improve the accuracy and reliability of abnormality monitoring. In addition, the coprocessor can realize the monitoring of the abnormal source at the chip level, which makes it possible to quickly locate the abnormality of the main processor, the abnormality of the bus between the main processor and the coprocessor, or the abnormality of the main processor. The processor and the bus are abnormal at the same time, so that the source of the abnormality can be accurately identified, and the ability to locate the root cause of the abnormality can be effectively enhanced, which in turn helps to reduce the fault recovery delay.

In a possible implementation manner, the coprocessor may perform chip-level abnormality monitoring on the motherboard in a real-time monitoring manner. In this way, the coprocessor can monitor in real time whether the main processor or the bus on the main board is abnormal, so as to report and alarm in time when at least one of the main processor or the bus is abnormal, and reduce the fault recovery delay.

In a possible implementation manner, when the coprocessor uses a real-time monitoring method to monitor the motherboard for chip-level abnormalities, it may specifically monitor in real time whether it receives a no-instruction timeout interrupt from the main processor, and the no-instruction timeout interrupt uses It is used to indicate that one or more processor cores in the main processor have not received instructions within a preset time period, and when receiving a no-instruction timeout interrupt, the coprocessor can determine that a chip-level exception occurs on the main board, specifically the main processing An exception occurred in the device. In this way, whether the main processor is abnormal can be judged in real time by monitoring whether the no-instruction timeout interrupt is received, so as to realize fast positioning when the main processor is abnormal.

In a possible implementation manner, when the coprocessor uses a real-time monitoring method to monitor the chip-level abnormality of the motherboard, it may specifically monitor in real time whether an interrupt signal of the internal bus in the main processor is received, and the interrupt signal is used for It is used to indicate the operation failure of the internal bus in the main processor, such as data transmission blockage in the internal bus or interruption of the data transmission link, etc., so that when receiving the interrupt signal of the internal bus, the coprocessor can determine that a chip-level exception occurs on the main board, Specifically, the internal bus in the host processor is abnormal. In this way, whether the internal bus is abnormal can be judged in real time by monitoring whether the interrupt signal of the internal bus is received, so as to realize rapid positioning when the internal bus is abnormal.

In a possible implementation manner, when the coprocessor performs chip-level abnormality monitoring on the motherboard in a real-time monitoring manner, it may specifically monitor in real time whether it receives an interrupt signal from the bus coupled between the coprocessor and the main processor. The interrupt signal is used to indicate the operation failure of the bus coupled between the coprocessor and the main processor, such as data transmission blocking on the bus or interruption of the data transmission link, etc., so that when receiving the interrupt signal of the bus, the coprocessor can determine the main board A chip-level exception occurs, specifically, an exception occurs on the bus coupling the coprocessor to the main processor. In this way, it is possible to judge whether the bus is abnormal in real time by monitoring whether the interrupt signal of the bus coupled to the coprocessor and the main processor is received, so as to realize fast processing when the bus coupled to the coprocessor and the main processor is abnormal. position.

In a possible implementation manner, the coprocessor may perform chip-level abnormality monitoring on the motherboard in a periodic monitoring manner. In this way, the coprocessor can not only detect whether the main processor or the bus on the main board is abnormal by periodic monitoring, but also reduce the cost of abnormal monitoring.

In a possible implementation manner, when the coprocessor performs chip-level abnormality monitoring on the motherboard in a periodic monitoring manner, it may specifically monitor whether it receives the first processor core of the main processor in the first monitoring cycle. A heartbeat message is sent, the heartbeat message is used to indicate that the first processor core is running normally, and when the heartbeat message is not received within the first monitoring period, the coprocessor determines that a chip-level abnormality occurs on the motherboard, specifically the first An exception occurred in a processor core. In this way, it can be determined whether the first processor core in the main processor is abnormal by means of periodical monitoring, so as to accurately locate the source of the abnormality when the first processor core is abnormal.

In a possible implementation manner, after determining that the first processor core is abnormal, the coprocessor may monitor whether it receives a heartbeat message sent by the second processor core within the second monitoring period, and the second processor core The heartbeat message sent is used to indicate that the second processor core is running normally, the second processor is a processor core in the main processor other than the first processor core, and, when the second processing core is not received When receiving the heartbeat message sent by the processor core, the coprocessor may determine that an exception occurs in the second processor core. In this way, after the first processor core is abnormal, it can be detected whether other processor cores on the main processor also have abnormalities, and other processor cores with abnormalities can be precisely located through the heartbeat message.

In a possible implementation manner, when the coprocessor performs chip-level abnormality monitoring on the motherboard in a periodic monitoring manner, specifically, it may periodically monitor all processor cores in the main processor, and, when no When the heartbeat message is sent by the third processor core among all the processor cores in the main processor, it is determined that the third processor core is abnormal, and the third processor core is any processor core in the main processor. In this way, when any processor core in the main processor is abnormal, the coprocessor can accurately locate the abnormal processor core through periodic monitoring.

In a possible implementation manner, the motherboard may include a baseboard management controller in addition to the main processor and the coprocessor, and the coprocessor may report to the baseboard management controller after generating a chip-level exception on the motherboard. A chip-level abnormality occurs on the motherboard to trigger the baseboard management controller to issue an abnormal alarm. In this way, the baseboard management controller can prompt the operation and maintenance personnel to restore the source of the abnormality in time through the abnormality alarm, thereby reducing the time delay of abnormality recovery.

In a possible implementation, the bus coupled between the coprocessor and the main processor may include an Advanced Extensible Interface AXI bus, a HyperTransport HT bus, a QuickPath Interconnect QPI bus, a unified bus UB, and a computing fast link CXL 1. At least one of the shortcut peripheral components interconnecting PCIe bus, or other signal lines that can be used for data communication, which is not limited in this embodiment.

In the second aspect, the present application also provides a method for abnormality monitoring, which is applied to a baseboard management controller (BMC), and the BMC is located on the main board. In addition to the BMC, the main board also includes a main processor coupled through a bus and an auxiliary Processor, the method includes: BMC receives a chip-level abnormality on the main board reported by the coprocessor, and the chip-level abnormality on the main board means that the main processor has an abnormality or the bus has an abnormality, and then, the BMC analyzes the chip-level abnormality, An abnormal monitoring result is generated, and an abnormal alarm is issued according to the abnormal monitoring result. In this way, the baseboard management controller can prompt the operation and maintenance personnel to restore the source of the abnormality in time through the abnormality alarm, thereby reducing the time delay of abnormality recovery.

In a possible implementation manner, the main board further includes a memory, and the BMC can also generate a monitoring log, which includes abnormal monitoring results, and then, the BMC can write the monitoring log into the memory. In this way, when the operation and maintenance personnel perform abnormal recovery, they can obtain the specific information of the abnormal source by viewing the monitoring log in the storage, so that the operation and maintenance personnel can accurately locate the abnormal source and recover quickly.

In a third aspect, the present application further provides an abnormality monitoring device, the abnormality monitoring device including various modules for executing the first aspect or the abnormality monitoring method in any possible implementation manner of the first aspect.

In a fourth aspect, the present application further provides an abnormality monitoring device, which includes various modules for executing the abnormality monitoring method in the second aspect or any possible implementation manner of the second aspect.

In the fifth aspect, the present application also provides a coprocessor, the coprocessor is composed of logic circuits, and the coprocessor is used to execute the abnormality monitoring method in the first aspect or in any possible implementation manner of the first aspect Steps.

In a sixth aspect, the present application also provides a computing device, including a mainboard, the mainboard includes a main processor and a coprocessor, and the coprocessor is used to execute the first aspect or any one of the possibilities of the first aspect according to computer instructions. Operation steps of the abnormality monitoring method in the implementation manner.

In the seventh aspect, the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on the coprocessor, the coprocessor is made to perform the above-mentioned first aspect and the first aspect The operation steps of the method described in any one of the implementation modes.

In an eighth aspect, the present application provides a computer program product containing instructions, which, when run on a coprocessor, causes the coprocessor to execute the first aspect and the method described in any one of the implementation modes of the first aspect Steps.

On the basis of the implementation manners provided in the foregoing aspects, the present application may further be combined to provide more implementation manners.

Description of drawings

FIG. 1 is a schematic structural diagram of an example computing device provided by the present application;

FIG. 2 is a schematic flow diagram of an abnormality monitoring method provided by the present application;

FIG. 3 is a schematic diagram of an exemplary display interface provided by the present application;

FIG. 4 is a schematic structural diagram of an abnormality monitoring device provided by the present application;

FIG. 5 is a schematic structural diagram of another abnormality monitoring device provided by the present application;

FIG. 6 is a schematic diagram of a hardware structure of a computing device provided in the present application.

Detailed ways

The technical solutions in the present application will be described below in conjunction with the drawings in the embodiments of the present application.

Referring to FIG. 1 , it is a schematic diagram of a hardware structure of a computing device provided in this application. As shown in FIG. 1 , a computing device 100 includes a main processor 101 and a coprocessor 102. The main processor 101 and the coprocessor 102 may be coupled through a bus (not shown in FIG. 1 ), so that the coprocessor 102 Data interaction with the main processor 101 can be performed through the bus. Moreover, the main processor 101 and the coprocessor 102 can be deployed on the main board 201 in the computing device 100 .

Wherein, the main processor 101 is used to run an operating system, and, for services running on the computing device 100, the main processor 101 can also perform corresponding data operations and resource scheduling for the services. The coprocessor 102 is used to assist the main processor 101 to perform corresponding management and control, and some coprocessors 102 can also perform tasks that the main processor 101 cannot perform.

As some examples, the main processor 101 may be, for example, a central processing unit (central processing unit, CPU), including a processor based on an advanced reduced instruction set machine (Advanced Reduced Instruction Set Computer Machine, ARM) architecture (such as ARMv8, ARMv9, etc.), An X86 processor based on a complex instruction set architecture (such as Skylake, etc.), or the main processor 101 can be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (programmable logic device, PLD). The PLD may be a complex programmable logic device (complex programmable logical device, CPLD), a field programmable logic gate array (field programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.

The coprocessor 102 can be, for example, an auxiliary processor on a system on chip (SOC), a graphics processing unit (graphics processing unit, GPU), an intelligent management unit (Intelligent management unit, IMU), a management engine (management engine) , ME), any one of single-chip microcomputers, or other co-processors, etc. In this embodiment, specific implementation manners of the main processor 101 and the coprocessor are not limited.

Moreover, the bus between the main processor 101 and the coprocessor 102 may be, for example, an advanced extensible interface (advanced extensible interface, AXI) bus, a hyper transport (hyper transport, HT) bus, a quick path interconnect (quick path interconnect, QPI) bus, unified bus (Unified bus, UB), computing express link (compute express link, CXL), shortcut peripheral component interconnect express (PCIe) bus, or other information available Interacting signal lines, such as shared address lines, data lines, etc., are not limited in this embodiment.

In actual application scenarios, due to hardware aging or electromagnetic interference, etc., the bus between the main processor 101 and the coprocessor 102 or the main processor 101 may be abnormal, which further causes failures such as downtime of the computing device 100 . To this end, the embodiment of the present application provides an abnormality monitoring method, in which the coprocessor 102 performs chip-level abnormality monitoring on the motherboard, that is, monitors at least one of the processor 101 or the bus in the motherboard. Moreover, when detecting that at least one of the main processor 101 and the bus is abnormal, the coprocessor 101 may generate a chip-level abnormality on the motherboard 201 . In this way, not only can the abnormal monitoring of the computing device 100 be realized, but also, since the coprocessor 102 executes the monitoring process inside the computing device 100, this can make the coprocessor 102 usually not be affected by the network during the process of obtaining the abnormal monitoring result. The transmission delay or the influence of the operating load of the computing device 100 can improve the accuracy and reliability of anomaly monitoring.

In addition, the coprocessor 102 can realize the monitoring of the abnormal source at the chip level, which makes it possible to quickly locate the main processor 101 and the connection between the main processor 101 and the coprocessor 102 after the computing device 100 has a fault such as a downtime. At least one of the buses is abnormal, so that the source of the abnormality can be accurately identified, the ability to locate the root cause of the abnormality of the computing device 100 is effectively enhanced, and the failure recovery delay of the computing device 100 can be reduced.

It should be noted that, in FIG. 1 , the integrated deployment of the main processor 101 and the coprocessor 102 on one chip is used as an example for illustration (that is, the coprocessor 102 is located on the chip where the main processor 101 is located), and in other possible In an implementation manner, the main processor 101 and the coprocessor 102 may also be respectively deployed on different chips.

Further, the computing device 100 not only includes a main processor 101 and a coprocessor 102, but also includes a baseboard management controller (baseboard management controller, BMC) 103 and a memory 104, and the BMC 103 and the memory 104 can be deployed on the motherboard 201. Wherein, BMC103 is used for receiving the information that coprocessor 102 provides, and is responsible for analyzing this information and information storage; For data communication, for example, the BMC 103 can receive a chip-level abnormality reported by the coprocessor 102 through the IPMI interface. The memory 104 is used to be responsible for data storage, such as an embedded multi media card (embedded multi media card, EMMC) etc.; the memory 104 can receive the data sent by the BMC103 through a secure digital input and output (secure digital input and output, SDIO) interface or other interfaces data, and store the data, for example, the memory 104 receives the monitoring log through the SDIO interface and stores the monitoring log, etc.

In addition, the computing device 100 can also be equipped with peripherals 105 (in FIG. Information is presented externally or data is entered into computing device 100 . Moreover, the peripheral device 105 can perform data interaction with the BMC 103 through a video graphics array (videographics array, VGA) interface or other interfaces. As some examples, the peripheral device 105 may be a monitor, or may be a keyboard video mouse (keyboard video mouse, KVM) or the like.

In practical applications, the computing device 100 may specifically be a computing server, such as a server in a high performance computing (highperformance computing, HPC) cluster. Alternatively, the computing device 100 may be a storage server capable of storing data. In this case, the computing device 100 may also be integrated with a storage element such as a solid state disk (solid state disk, SSD). Alternatively, the computing device 100 may be a terminal device, such as a portable terminal device such as a mobile phone or a notebook computer. In this embodiment, specific application scenarios of the computing device 100 are not limited.

It should be noted that the computing device 100 shown in FIG. 1 is only used as an example, and in actual application, the computing device 100 may also adopt other applicable architectures. For example, in other possible computing devices 100, a power supply may also be integrated on the motherboard 201, and the power supplies are respectively connected to the main processor 101, the coprocessor 102, the BMC 103, and the memory 104 to provide power for them; or, the computing device 100 can be configured with a greater number of main processors or co-processors, etc.

Next, the abnormality monitoring process for the computing device 100 provided by the present application will be further introduced with reference to the accompanying drawings.

Referring to FIG. 2, FIG. 2 is a schematic flowchart of an abnormality monitoring method provided by an embodiment of the present application, wherein the method can be applied to the computing device 100 shown in FIG. 1, and specifically can be executed by the coprocessor 102 in FIG. 1 this method.

As shown in Figure 2, the method may specifically include:

S201: The coprocessor 102 performs chip-level abnormality monitoring on the motherboard 201. The chip-level abnormality monitoring includes at least one of the main processor 101 in the motherboard 201 or the bus between the main processor 101 and the coprocessor 102. Anomaly monitoring.

Since abnormality monitoring is performed outside the computing device 100, it may be affected by the network transmission delay and the load of the computing device 100 itself. Therefore, in this embodiment, the coprocessor 102 can cause the computing device 100 to Monitor the fault sources that cause downtime and other faults. During specific implementation, the coprocessor 102 may perform chip-level abnormality monitoring on the main board 201 . As some examples, the chip-level abnormality monitoring performed by the coprocessor 102 on the motherboard 201 mainly includes any of the following methods:

Mode 1, the coprocessor 102 can monitor the abnormality of the main processor 101 .

In the first implementation example of monitoring the main processor 101, the coprocessor 102 can monitor in real time whether it receives a no-instruction timeout interrupt from the main processor 101, and the no-instruction timeout interrupt is used to indicate that one of the main processors 102 or Multiple processor cores do not receive instructions within a preset time period, and when receiving a no-instruction timeout interrupt, the coprocessor 102 may determine that the main processor 101 is abnormal. Wherein, the main processor 101 may include one or more processor cores, and when the main processor 101 determines that there is one or more processor cores that have not received an instruction submitted by the operating system kernel within a preset period of time, This is probably because the processor core is in a no-commit state for a long time due to a failure of the processor core. At this time, the main processor 101 may generate a no-instruction timeout interrupt and send it to the coprocessor 102, so as to notify the coprocessor 102 of an exception through the no-instruction timeout interrupt.

Further, after receiving the no-instruction timeout interrupt, the coprocessor 102 can access the main processor 101 and collect exception information. Wherein, multiple components can be integrated on the main processor 101, for example, in addition to the above-mentioned processor core, it can also include cache (cache), memory (memory), memory controller (memory controller), input and output controller (IO controller), IO expansion controller, and other logic circuits capable of performing computing functions. Wherein, the input-output controller can be, for example, a PCIe controller, a serial attached small computer system interface controller (serial attachedsmall computer system interface controller), a serial advanced technology attachment controller (serialadvanced technology attachment controller), etc.; an IO expansion controller For example, it may be an integrated circuit controller (inter-integrated circuit controller). Therefore, the coprocessor 102 can access multiple elements such as the cache memory, the memory, and the memory controller on the main processor 101 through the bus after receiving the no-instruction timeout interrupt, and determine whether each element is abnormal (such as determining whether the element is storage error/control error, etc.), so that the information of the abnormal component can be collected, such as the name of the abnormal component, the cause of the abnormality and other information. Wherein, by accessing elements such as cache and memory to determine whether the element is abnormal, there are related applications in actual application scenarios, which will not be described in detail in this embodiment.

In the second implementation example of monitoring the main processor 101, the coprocessor 102 can monitor in real time whether an interrupt signal sent by the internal bus from the main processor 101 is received, and the interrupt signal can indicate that the internal bus fails during operation. , such as communication congestion, link disconnection and other faults. Wherein, the internal bus of the main processor 101 refers to a bus used for data exchange between multiple components in the main processor 101, such as a ring bus (ring bus), a mesh bus, and the like. During specific implementation, a system isolation wall (system isolation wall, SIW) may be deployed on the internal bus, and when the two components on the main processor 101 communicate through the internal bus, the The SIW judges whether the data communication process between these two components is legal. Correspondingly, the coprocessor 102 can access the components on the main processor 101 through the internal bus. For example, the coprocessor 102 may send an access instruction to the main processor 101 , and the access instruction may be transmitted to components in the main processor 101 by an internal bus on the main processor 101 . When the internal bus is running normally, the coprocessor 102 can realize the access to the elements in the main processor 101 through the access instruction; and when the internal bus fails, the SIW on the internal bus can return an interrupt signal and the interrupt signal is transmitted to the coprocessor 102. In this way, after receiving the interrupt signal from the internal bus, the coprocessor 102 can determine that the main processor 101 is abnormal, specifically, the internal bus on the main processor 101 is abnormal.

In the third implementation example of monitoring the main processor 101, the coprocessor 102 can periodically determine whether the first processor core in the main processor 101 fails through heartbeat monitoring, and the first processor core is the main processor. The first processor core in the processor 101 is used to uniformly schedule and manage on-chip resources. In some application scenarios, the first processor core may also be called the main core. During specific implementation, the first processor core in the main processor 101 may periodically send a heartbeat message to the coprocessor 102 during operation, and the heartbeat message may be, for example, an interrupt response sent by the first processor core, etc. Used to indicate that the first processor core is running normally. Correspondingly, the coprocessor 102 may monitor whether a heartbeat message from the first processor core is received within the first monitoring period corresponding to the first processor core, and, when the coprocessor 102 is within the first monitoring period When the heartbeat message is not received, it indicates that the coprocessor 102 does not receive the heartbeat message because the first processor core is likely to fail. At this time, the coprocessor 102 can determine that the main processor 101 is abnormal, specifically An exception occurred for the first processor core.

Wherein, the first processor core may actively send a heartbeat message to the coprocessor 102 periodically during operation, so that the coprocessor 102 may determine whether the first processor core receives the heartbeat message in each monitoring cycle. Whether an exception occurred. Alternatively, the coprocessor 102 can actively send a heartbeat command to the first processor core in the main processor 101 through a system control management interface (System Control and Management Interface, SCMI) in each monitoring cycle, so that the first processor core can An interrupt response (that is, a heartbeat message) is generated based on the heartbeat instruction, and the interrupt response is fed back to the coprocessor 102 . In this way, when the coprocessor 102 does not receive the interrupt response within the monitoring period, it can determine that the first processor core is abnormal.

Further, after the coprocessor 102 determines that the first processor core is abnormal, it can access multiple components on the main processor 101, such as the cache, memory, memory controller, input and output controller, IO on the main processor 101. The extended controller and other logic circuits capable of performing calculation functions can determine whether the components on the main processor 101 are abnormal, and collect abnormal information for the abnormal components.

In the fourth implementation example of monitoring the main processor 101, after determining that the first processor core is abnormal, the coprocessor 102 may start monitoring whether other processor cores on the main processor 101 are abnormal. Taking the monitoring of the second processor core on the main processor 101 as an example, the second processor core in the main processor 101 other than the first processor core, the coprocessor 102 can monitor the Whether a heartbeat message sent by the second processor core is received within the second monitoring period corresponding to the processor core, and the heartbeat message is used to indicate that the second processor core is running normally. And, when a heartbeat message from the second processor core is not received within the second monitoring period, the coprocessor 102 may determine that an abnormality occurs in the second processor core; and when a heartbeat message is received within the second monitoring period When receiving the heartbeat message, the coprocessor 102 may determine that the second processor core is running normally. Wherein, the first monitoring period corresponding to the first processor core may be the same as or different from the second monitoring period corresponding to the second processor core.

In the fifth implementation example of monitoring the main processor 101, the coprocessor 102 can periodically monitor all the processor cores in the main processor 101, taking the monitoring of the third processor core as an example, the third processor core For any processor core in all processor cores in the main processor 101, the coprocessor 102 can monitor whether a heartbeat sent from the third processor core is received in the third monitoring period corresponding to the third processor core message, the heartbeat message is used to indicate that the third processor core is running normally. And, when the heartbeat message from the third processor core is not received within the third monitoring period, the coprocessor 102 may determine that the third processor core is abnormal; When receiving the heartbeat message, the coprocessor 102 may determine that the third processor core is running normally. In this way, the coprocessor 102 can monitor all processor cores in the main processor 101 for abnormalities based on the above method, and can determine all processor cores in the main processor 101 that have abnormalities.

In practical applications, the coprocessor 102 can simultaneously execute any one or more of the above five implementation examples, such as monitoring the internal bus in the main processor 101 and whether there is an abnormality in the processor core, etc. Not limited.

In mode 2, the coprocessor 102 can monitor the abnormality of the bus coupled between the main processor 101 and the coprocessor 102 .

In the implementation example of the first monitoring bus, the coprocessor 102 can monitor in real time whether it receives an interrupt signal sent by the bus coupling the main processor 101 and the coprocessor 102, and the interrupt signal is used to indicate the operation failure of the bus , and, when receiving the interrupt signal sent by the bus, the coprocessor 102 may determine that the bus is abnormal. Wherein, when the main processor 101 is specifically an ARM processor, the bus coupling the main processor 101 and the coprocessor 102 may send an interrupt signal to the coprocessor 102 through the SIW. Specifically, an SIW may be configured in the bus coupling the main processor 101 and the coprocessor 102, and when the coprocessor 102 accesses the main processor 101 through the bus, the access instruction sent by the coprocessor 102 will first pass through the SIW. After the SIW determines that the access instruction is a legal instruction, it transmits the access instruction to the main processor 101 to realize the access of the coprocessor 102 to the main processor 101; The coprocessor 102 feeds back a corresponding message, so as to prevent the coprocessor 102 from hanging due to an access failure. During operation, SIW can sense whether the bus is faulty during operation, such as sensing whether there are faults such as communication blockage and link disconnection on the bus, and when it is determined that the bus is faulty, an interrupt signal indicating the faulty operation of the bus is generated. And send the interrupt signal to the coprocessor 102 .

In the second implementation example of monitoring the main processor 101, the coprocessor 102 uses a real-time monitoring method to perform abnormality monitoring, and the main board 201 is deployed based on the X86 architecture, then the coprocessor 102 can use the host embedded controller interface ( host embedded controller interface (HECI) communicates with the main processor 102 . At this time, the coprocessor 102 may specifically be a management engine, so that the coprocessor 102 may determine whether the main processor 101 fails according to the state of the main processor 101 accessed through the HECI interface. For example, when the coprocessor 102 fails to access the main processor 101 through the HECI interface, it may be determined that the main processor 101 is abnormal.

It is worth noting that the various implementation examples above are only exemplary illustrations for coprocessor 102 to perform abnormality monitoring. In other embodiments, coprocessor 102 may also implement At least one of the abnormality monitoring; and, in actual application, the coprocessor 102 can execute the above-mentioned multiple implementation examples at the same time, such as performing abnormality monitoring on the main processor 101 and the bus at the same time, which is not limited in this embodiment . In addition, the above-mentioned coprocessor 102’s function of abnormality monitoring can be automatically executed during the start-up and operation of the coprocessor 102. For example, the program code for realizing the abnormality monitoring function performed by the above-mentioned coprocessor 102 can be pre-burned into the coprocessor. In the firmware in the processor 102, the coprocessor 102 can begin to perform anomaly monitoring functions when it is up and running. Alternatively, the coprocessor 102 may enable the abnormality monitoring function during any period of time during operation, for example, the coprocessor 102 may be triggered by a user or operation and maintenance personnel to enable the abnormality monitoring function.

It should be noted that the real-time monitoring and periodic monitoring in this embodiment are relative concepts, that is, the abnormality monitoring time delay generated by the real-time monitoring method is much smaller than the abnormality monitoring time delay generated by the periodic monitoring method. For example, when the real-time monitoring method is adopted, the coprocessor 102 can detect that the main processor 101 or the bus is abnormal within a time delay of nanosecond level, achieving or approximately achieving the "real-time" effect; while when the periodic monitoring method is adopted Therefore, the coprocessor 102 can detect that the main processor 101 or the bus is abnormal within a time delay of milliseconds or seconds, and the time delay for abnormality monitoring is relatively long.

S202: When detecting that the main processor 101 or the bus is abnormal, the coprocessor 102 generates a chip-level abnormality on the motherboard 201 .

In this embodiment, when the coprocessor 102 determines that at least one of the main processor 101 or the bus is abnormal, it generates a chip abnormality on the motherboard 201 . Further, the coprocessor 102 may also report the indication information that the motherboard 201 has a chip-level abnormality to the BMC 103 . In this way, not only the abnormal monitoring of the computing device 100 can be realized, but also the chip-level abnormal location can be realized, that is, when the computing device 100 fails, it can be located that it is the main processor on one or more chips in the motherboard 201 At least one of 102 or the bus has failed.

Exemplarily, when the coprocessor 102 reports that the mainboard 201 has a chip-level abnormality, it may report the collected abnormality information and the information indicating that the mainboard 201 has a chip-level abnormality to the BMC 103 . Wherein, the abnormality information may be determined by the coprocessor 102 collecting components on the main processor 101 when determining that there is an abnormality, such as the name of the abnormal component on the main processor 101, the cause of the abnormality, and the like.

Further, after the coprocessor 102 detects that at least one of the main processor 101 or the bus is abnormal, it can also trigger the BMC 103 to give an abnormal alarm. Specifically, this embodiment may also include:

S203: After receiving the report from the coprocessor 102 that the motherboard 201 has a chip-level abnormality, the BMC 103 issues an abnormality alarm.

In a possible implementation manner, after BMC 103 receives information that a chip-level abnormality occurs in the main board 201, it can analyze the information and generate an abnormality monitoring result indicating that at least one of the main processor 101 or the bus is abnormal, thereby BMC103 can issue an abnormal alarm according to the abnormal monitoring result. Exemplarily, BMC 103 can generate alarm information according to the abnormality monitoring result, and send it to peripheral device 105, so that peripheral device 105 can make a corresponding alarm prompt according to the alarm information. For example, when the peripheral device 105 is specifically a display, after receiving the alarm information sent by the BMC 103 , the peripheral device 105 may display an alarm prompt indicating that at least one of the main processor 101 or the bus is abnormal on the display interface. For example, when it is detected that the main processor 101 is abnormal, the peripheral device 105 may display an alarm prompt of "the main processor is currently abnormal, please fix it in time" on the display interface shown in FIG. 3 . In this way, after viewing the alarm content, the user or operation and maintenance personnel can not only determine that the computing device 100 is abnormal, but also quickly locate the location where the computing device 100 is abnormal, which is the main processor 101 on the main board 201 or the main processor 101 on the bus. At least one of them, so that corresponding maintenance operations can be performed on the computing device 100, and the efficiency of abnormal recovery of the computing device 100 is improved, thereby improving the efficiency of service recovery on the computing device 100. Of course, the peripheral device 105 may also issue an abnormal alarm by means of voice, lighting, etc., which is not limited in this embodiment.

In addition, after the BMC 103 determines that there is a chip-level abnormality, it may also generate a monitoring log including abnormality monitoring results, so as to record in the monitoring log that at least one of the main processor 101 or the bus is abnormal. For example, the BMC 103 may first create a monitoring log, and according to the time stamp of the abnormal information collected by the coprocessor 102, organize log entries in chronological order, and record them in the monitoring log. Then, the BMC 103 may send the generated monitoring log to the memory 104 for storage, or store the monitoring log in other ways, which is not limited in this embodiment. In this way, after the user or operation and maintenance personnel determine that there is an abnormality in the computing device 100, they can read the monitoring log stored in the memory 104, and perform an abnormal operation on at least one of the main processor 101 or the bus according to the log entries recorded in the monitoring log. analysis for efficient maintenance of at least one of the main processor 101 or the bus.

In this embodiment, not only abnormality monitoring can be realized, but also, since the coprocessor 102 performs chip-level abnormality monitoring on the motherboard 201, this can make the coprocessor 102 usually not be affected by network transmission delay or the motherboard 201 during the abnormality monitoring process. 201 operating load, so as to improve the accuracy and reliability of abnormal monitoring. In addition, the coprocessor 102 can realize the monitoring of the abnormal source at the chip level, which makes it possible to quickly locate the abnormality in the main processor 101 or the bus between the main processor 101 and the coprocessor 102 after an abnormality occurs. Abnormal, or the main processor 101 and the bus are abnormal at the same time, so that the source of the abnormality can be accurately identified, and the ability to locate the root cause of the abnormality can be effectively enhanced, thereby helping to reduce the fault recovery delay.

It should be noted that other reasonable step combinations conceivable by those skilled in the art based on the above description also fall within the protection scope of the present application. Secondly, those skilled in the art should also be familiar with that the embodiments described in the specification belong to preferred embodiments, and the actions involved are not necessarily required by this application.

The anomaly monitoring method provided by the present application is described in detail above with reference to FIG. 1 to FIG. 3 , and the abnormality monitoring device and computing equipment provided according to the present application will be described below in conjunction with FIG. 4 to FIG. 6 .

FIG. 4 is a schematic structural diagram of an abnormality monitoring device provided by the present application. The abnormality monitoring device 400 is applied to the coprocessor in the motherboard, such as the above-mentioned coprocessor 102, etc., and the motherboard also includes a main processor, and the main processor and the coprocessor are coupled through a bus, as shown in Figure 4 , the abnormality monitoring device 400 may include:

The abnormality monitoring module 401 is configured to perform chip-level abnormality monitoring on the motherboard, and the chip-level abnormality monitoring includes abnormality monitoring on at least one of the main processor or the bus in the motherboard;

The generating module 402 is configured to generate a chip-level abnormality on the motherboard when it is detected that the chip-level abnormality occurs on the motherboard.

In a possible implementation manner, the abnormality monitoring module 401 is specifically configured to perform chip-level abnormality monitoring on the motherboard in a real-time monitoring manner.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

When the no-instruction timeout interrupt of the main processor is received, it is determined that an exception occurs in the main processor, wherein the no-instruction timeout interrupt is used to indicate that one or more processor cores in the main processor are No command received within the preset time period.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

monitoring whether an interrupt signal of the internal bus in the main processor is received, the interrupt signal is used to indicate that the internal bus is faulty;

When the interrupt signal is received, it is determined that the internal bus is abnormal.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

monitoring whether an interrupt signal of the bus is received, the interrupt signal is used to indicate the operation failure of the bus;

When the interrupt signal is received, it is determined that the bus is abnormal.

In a possible implementation manner, the abnormality monitoring module 401 is specifically configured to perform chip-level abnormality monitoring on the motherboard in a periodic monitoring manner.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

During the first monitoring period, it is monitored whether a heartbeat message sent by the first processor core of the main processor is received, and the heartbeat message is used to indicate that the first processor core is running normally;

When the heartbeat message is not received within the first monitoring period, it is determined that the first processor core is abnormal.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

In the second detection period, it is monitored whether a heartbeat message sent by the second processor core is received, the heartbeat message sent by the second processor core is used to indicate that the second processor core is running normally, and the second processing The processor core is a processor core other than the first processor core in the main processor;

When the heartbeat message sent by the second processor core is not received within the second monitoring period, it is determined that the second processor core is abnormal.

In a possible implementation manner, the abnormality monitoring module 401 is specifically used for:

Periodically monitor all processor cores in the main processor;

When the heartbeat message sent by the third processor core among all the processor cores in the main processor is not received, it is determined that an exception occurs in the third processor core, and the third processor core is one of the main processor cores. any processor core.

In a possible implementation manner, the abnormality monitoring device 400 further includes:

The reporting module 403 is configured to report to the BMC that the chip-level abnormality occurs on the motherboard, so as to trigger the BMC to issue an abnormal alarm.

In a possible implementation manner, the bus includes an advanced extensible interface AXI bus, a hypertransport HT bus, a fast channel interconnect QPI bus, a unified bus UB, a computing fast link CXL, and a fast peripheral component interconnect PCIe bus. at least one.

The anomaly monitoring device 400 according to the embodiment of the present application may correspond to the method executed by the coprocessor 102 described in the embodiment of the present application, and the above-mentioned and other operations or functions of the various modules of the anomaly monitoring device 400 are respectively in order to realize the For the sake of brevity, the corresponding processes of each method are not repeated here.

In this embodiment, not only abnormality monitoring can be realized, but also, since the coprocessor performs chip-level abnormality monitoring on the motherboard, this can make the coprocessor usually not be affected by the network transmission delay or the operating load of the motherboard during the abnormality monitoring process. Influence, so as to improve the accuracy and reliability of anomaly monitoring. In addition, the coprocessor can realize the monitoring of the abnormal source at the chip level, which makes it possible to quickly locate the abnormality of the main processor, the abnormality of the bus between the main processor and the coprocessor, or the abnormality of the main processor. The processor and the bus are abnormal at the same time, so that the source of the abnormality can be accurately identified, and the ability to locate the root cause of the abnormality can be effectively enhanced, which in turn helps to reduce the fault recovery delay.

FIG. 5 is a schematic structural diagram of another abnormality monitoring device provided by the present application. The abnormality monitoring device 500 is applied to the BMC in the motherboard, such as the above-mentioned BMC103, etc., and the motherboard also includes a main processor and a coprocessor, and the main processor and the coprocessor are coupled through a bus, as shown in Figure 5, Anomaly monitoring device 500 may include:

The receiving module 501 is used to receive a chip-level abnormality on the main board reported by the coprocessor, and the chip-level abnormality on the main board means that the main processor is abnormal or the bus is abnormal;

The analysis module 502 is used to analyze the chip-level abnormality and generate abnormality monitoring results;

The warning module 503 is configured to give an abnormality warning according to the abnormality monitoring result.

In a possible implementation manner, the motherboard further includes a memory, and the abnormality monitoring device 500 further includes:

A generating module 504, configured to generate a monitoring log, which includes abnormal monitoring results;

A writing module 505, configured to write the monitoring log into the memory.

The abnormality monitoring device 500 according to the embodiment of the present application may correspond to the implementation of the method described in the embodiment of the present application performed by the BMC103, and the above-mentioned and other operations or functions of the various modules of the abnormality monitoring device 500 are respectively in order to realize the various methods in FIG. 2 For the sake of brevity, the corresponding process will not be repeated here.

FIG. 6 is a schematic diagram of a computing device 600 provided by the present application. As shown in the figure, the computing device 600 includes a motherboard 700, the motherboard 700 includes a main processor 601, a coprocessor 602, and the main processor 601 and The coprocessor 602 is coupled through the bus 603 , so that the main processor 601 and the coprocessor 602 perform data communication through the bus 603 . Optionally, the mainboard 700 may further include a memory 604, a baseboard management controller 605, and a communication interface 606, and correspondingly, the main processor 601, the coprocessor 602, the memory 604, the baseboard management controller 605, and the communication interface 606 may The bus 603 communicates.

It should be noted that, besides the data bus, the bus 603 may also include a power bus, a control bus, and a status signal bus. However, for clarity of illustration, the various buses are labeled as bus 603 in the figure.

In this embodiment, the main processor 601 can be a CPU, and can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices , discrete gate or transistor logic devices, discrete device components, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

The coprocessor 602 may be, for example, any one of an auxiliary processor on the SOC, a GPU, an IMU, an ME, a single-chip microcomputer, or a logic circuit, or may be other coprocessors.

As a possible implementation manner, the main processor 601 and the coprocessor 602 may be packaged as one chip, or may be separately packaged as one chip.

The memory 604 may include read-only memory and random-access memory, and provides instructions and data to the main processor 601 and the co-processor 602 . Memory 604 may also include non-volatile random access memory.

Memory 604 can be volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the non-volatile memory can be read-only memory (read-only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erases programmable read-only memory (electrically EPROM, EEPROM) or flash memory. Volatile memory can be random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), Double data rate synchronous dynamic random access memory (double data date SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) and direct Memory bus random access memory (direct rambus RAM, DR RAM).

The communication interface 606 is used for communicating with other devices connected to the computing device 600 .

It should be understood that the computing device 600 according to the embodiment of the present application may correspond to the corresponding processes of the methods in FIG. 2 in the embodiment of the present application, and details are not repeated here for brevity.

The present application also provides a mainboard, the mainboard structure is as shown in the mainboard 700 in Figure 6, the mainboard 700 includes a main processor and a coprocessor, and the coprocessor is used to realize the functions realized by the coprocessor in the above method shown in Figure 2 , for the sake of brevity, it is not repeated here.

The above-mentioned embodiments may be implemented in whole or in part by software, hardware, firmware or other arbitrary combinations. When implemented using software, the above-described embodiments may be implemented in whole or in part in the form of computer program products. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more sets of available media. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media. The semiconductor medium may be a solid state drive (SSD).

The above is only a specific embodiment of the application, but the scope of protection of the application is not limited thereto. Any person familiar with the technical field can easily think of various equivalents within the scope of the technology disclosed in the application. Modifications or replacements, these modifications or replacements shall be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (13)

1. An anomaly monitoring method, the method being applied to a motherboard, the motherboard comprising a main processor and a coprocessor, the main processor and the coprocessor being coupled by a bus, the method being performed by the coprocessor, comprising:

performing chip-level exception monitoring on the main board, wherein the chip-level exception monitoring comprises performing exception monitoring on at least one of the main processor or the bus in the main board;

and when the mainboard is monitored to have the chip-level abnormality, generating that the mainboard has the chip-level abnormality.

2. The method of claim 1, wherein the coprocessor performs on-chip exception monitoring on the motherboard using real-time monitoring.

3. The method of claim 2, wherein the performing on-chip anomaly monitoring on the motherboard using a real-time monitoring method comprises:

and when receiving the non-instruction timeout interrupt of the main processor, determining that the main processor is abnormal, wherein the non-instruction timeout interrupt is used for indicating one or more processor cores in the main processor not to receive instructions within a preset duration.

4. The method of claim 2, wherein the performing on-chip anomaly monitoring on the motherboard using a real-time monitoring method comprises:

monitoring whether an interrupt signal of an internal bus in the main processor is received or not, wherein the interrupt signal is used for indicating the operation fault of the internal bus;

and when the interrupt signal is received, determining that the internal bus is abnormal.

5. The method of claim 2, wherein the performing on-chip anomaly monitoring on the motherboard using a real-time monitoring method comprises:

monitoring whether an interrupt signal of the bus is received or not, wherein the interrupt signal is used for indicating the bus to run out of order;

and when the interrupt signal is received, determining that the bus is abnormal.

6. The method of claim 1, wherein the coprocessor performs on-chip exception monitoring on the motherboard using periodic monitoring.

7. The method of claim 6, wherein the performing on-chip anomaly monitoring on the motherboard using a periodic monitoring method comprises:

in a first monitoring period, monitoring whether a heartbeat message sent by a first processor core of the main processor is received or not, wherein the heartbeat message is used for indicating the first processor core to normally operate;

when the heartbeat message is not received within the first monitoring period, determining that an exception occurs to the first processor core.

8. The method of claim 7, wherein after determining that an exception occurred to the first processor core, the method further comprises:

in a second detection period, monitoring whether heartbeat messages sent by a second processor core are received or not, wherein the heartbeat messages sent by the second processor core are used for indicating the second processor core to normally operate, and the second processor core is a processor core except the first processor core in the main processor;

and determining that the second processor core is abnormal when the heartbeat message sent by the second processor core is not received in the second monitoring period.

9. The method of claim 6, wherein the coprocessor performs chip-level exception monitoring on the motherboard using a periodic monitoring scheme, comprising:

periodically monitoring all processor cores in the main processor;

and when the heartbeat message sent by a third processor core in all the processor cores in the main processor is not received, determining that the third processor core is abnormal, wherein the third processor core is any processor core in the main processor.

10. The method of any of claims 1 to 9, wherein the motherboard further comprises a baseboard management controller, BMC, the method further comprising:

and reporting the chip-level abnormality of the mainboard to the BMC so as to trigger the BMC to carry out abnormality alarm.

11. The method of any of claims 1 to 10, wherein the bus comprises at least one of an advanced extensible interface AXI bus, a hypertransport HT bus, a fast lane interconnect QPI bus, a unified bus UB, a computing express link CXL, a peripheral component interconnect express PCIe bus.

12. Coprocessor, characterized in that it is composed of logic circuits for implementing the functions of the operating steps of the method according to any of claims 1 to 11.

13. A computing device comprising a motherboard, the motherboard comprising a host processor and a co-processor, the host processor and the co-processor coupled by a bus, the co-processor configured to perform the operational steps of the method of any of claims 1-11 in accordance with the computer instructions.