CN116564978A - Novel protection diode structure for stacked image sensor devices - Google Patents

Abstract

The present disclosure relates to novel protective diode structures for stacked image sensor devices. The first side of the sensor wafer is bonded to the first side of the first logic wafer. The sensor wafer includes pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer includes circuitry configured to operate the pixels. The sensor wafer or the first logic wafer includes a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. Through Substrate Vias (TSVs) are formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from damage during TSV formation. The second side of the first logic wafer is bonded to the second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

Description

Novel protection diode structure for stacked image sensor devices

technical field

The present disclosure relates to novel protection diode structures for stacked image sensor devices.

Background technique

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (ie, the number of interconnected devices per chip area) generally increases, while geometry size (ie, the smallest component (or line) that can be created using a fabrication process) decreases. This scaled-down process often provides benefits through increased production efficiency and reduced associated costs.

As semiconductor devices shrink in size and increase in complexity, they can be deployed in a wide variety of applications. These applications may include semiconductor image sensors for sensing radiation such as light. For example, complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are widely used in various applications such as digital cameras, mobile phones, medical devices, automotive sensors, etc. These devices utilize an array of pixels located in a substrate, including photodiodes and transistors, which absorb radiation impinging on the substrate and convert the sensed radiation into electrical signals.

However, conventional image sensor device fabrication processes may expose the device to ambient plasma, which may damage the elements of the image sensor device. In addition, conventional image sensor devices may also be vulnerable to damage during actual operation. Traditional methods of protecting image sensor devices from these types of damage are not entirely satisfactory.

Contents of the invention

According to an embodiment of the present disclosure, there is provided an image sensor device, including: a first substrate including a plurality of pixels and at least one transistor; a second substrate bonded to the first substrate, the second The substrate includes a circuit for interacting with the pixel; and a protection diode is disposed in the first substrate or in the second substrate, and the protection diode includes: a first doped region, disposed in the a second doped region in the first doped region, and a third doped region disposed in the second doped region; wherein: the first doped region and the third doped region have the same conductivity type; the second doped region has a different conductivity type than the first doped region and the third doped region; and the third doped region is electrically coupled to the first substrate bottom transistor.

According to another embodiment of the present disclosure, there is provided an image sensor device including: a sensor substrate including a plurality of pixels and a transfer gate, wherein the pixels are configured to detect radiation entering the sensor substrate from the backside of the substrate; a first non-sensor substrate bonded to the sensor substrate through the front side of the sensor substrate, the first non-sensor substrate comprising circuitry of said pixel; a second non-sensor substrate bonded to said first non-sensor substrate such that said first non-sensor substrate is bonded between said sensor substrate and said second non-sensor substrate , the second non-sensor substrate includes other circuitry configured to operate the pixels; one or more protection diodes, implemented on the sensor substrate, the first non-sensor substrate, or the second In a non-sensor substrate; wherein: each of the one or more protection diodes includes: a first doped well, a second doped well located within the first doped well, and a second doped well located within the A third doped well in the second doped well; the second doped well has a conductivity type different from that of the first doped well and the third doped well; the first doped well is electrically conductive connected to a first reference voltage; the second doped well is electrically connected to a second reference voltage different from the first reference voltage; and the third doped well is electrically connected to the transfer gate.

According to yet another embodiment of the present disclosure, there is provided a method of manufacturing an image sensor device, comprising: bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer includes pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side, wherein the first logic die contains a circuit for a pixel, and wherein the sensor wafer or the first logic wafer includes protection diodes; the first logic wafer is placed from a second side of the first logic wafer opposite the first side thinning; forming through-substrate vias (TSVs) in the first logic wafer, wherein the protection diode protects the sensor wafer or the first logic wafer from damaging; bonding the second side of the first logic wafer to a second logic wafer; and thinning the sensor wafer from the second side of the sensor wafer.

Description of drawings

The present disclosure is best understood from the following Detailed Description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion.

1-4 illustrate a series of cross-sectional side views of an image sensor device at various stages of fabrication corresponding to process flows, according to various aspects of the present disclosure.

5-10 illustrate cross-sectional side views of image sensor devices according to various aspects of the present disclosure.

FIG. 11 shows a flowchart illustrating a method according to various aspects of the present disclosure.

12 shows a block diagram of an integrated circuit fabrication system in accordance with various aspects of the present disclosure.

Detailed ways

The following disclosure provides many different embodiments, or examples, for implementing the different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which the first feature may be formed on the first feature. Embodiments in which an additional feature is formed between and a second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Additionally, the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the following disclosure, the formation of another feature on, connected to, and/or coupled to a feature may include embodiments in which the features are formed in direct contact, and also Embodiments may be included where additional features are formed intervening with features such that the features are not in direct contact. In addition, for convenience in describing the relationship of one feature of the present disclosure with respect to another feature, terms such as "lower", "higher", "horizontal", "vertical", "above", "above", etc. are used herein. Spatial terms such as "below", "under", "upper", "lower", "top", "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc. ). Spatially relative terms are intended to cover different orientations of a device including these features. In addition, when "about" and "approximately" are used to describe numbers or numerical ranges, the term is intended to cover numbers within a reasonable range including the stated number, such as within +/- 10% of the stated number or other values as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5 nm.

The present disclosure relates generally to semiconductor devices, and more particularly to image sensor devices. For example, the present disclosure describes methods and apparatus for protecting a stacked CMOS image sensor (CIS) during its manufacture and operation, which in turn improves the yield and/or performance of the CIS. In more detail, an embodiment of the CIS 10 utilizes a 3-wafer stack implementation. A simplified manufacturing process flow of the CIS 10 is shown with reference to FIGS. 1-4 , which are cross-sectional side views of the CIS 10 at different manufacturing stages. The cross-sectional view is taken along a plane defined by a horizontal X direction (or X axis) and a vertical Y direction (or Y axis).

Referring now to FIG. 1 , CIS 10 includes sensor wafer T1 . The sensor wafer T1 may include a substrate, for example, a silicon substrate doped with P-type dopants or N-type dopants. The P-type dopant can be boron, and the N-type dopant can be phosphorus or arsenic. The substrate of sensor wafer T1 may also include other base semiconductors (eg, germanium), and/or may optionally include compound semiconductors and/or alloy semiconductors. In addition, the substrate of sensor wafer T1 may include an epi layer, may be strained to improve performance, and may include a silicon-on-insulator (SOI) structure.

The substrate of the sensor wafer T1 includes a plurality of radiation sensing elements or light sensing elements (for simplicity, not specifically shown in FIGS. 1-4 ). The radiation sensing elements are portions of pixels operable to sense or detect radiation waves (eg, light) directed toward sensor wafer T1 and entering sensor wafer T1 through backside 20 of sensor wafer T1 . In some embodiments, the radiation sensing element includes a photodiode. In other embodiments, the radiation sensing element may include a pinned photodiode (PPD), a photogate, or other suitable photosensitive elements. Photodiodes or other types of radiation sensing elements may be formed by performing multiple ion implantation processes on the substrate of sensor wafer T1. For example, N+ implants, array N-well implants, and deep array N-well implants can be performed. The ion implantation process may include multiple implantation steps and may use different types of dopants, implantation doses, and implantation energies. The ion implantation process can also use different masks with different patterns and opening sizes. In some embodiments, radiation sensing elements may also be formed in doped wells having a conductivity type opposite to that of the substrate of sensor wafer T1 .

The radiation sensing elements are physically and electrically isolated by isolation structures, such as shallow trench isolation (STI) or deep trench isolation (DTI) structures. STI or DTI structures are formed by etching openings (or trenches) in the substrate and then filling the openings with a suitable material. The isolation structure is used to prevent or substantially reduce crosstalk between adjacent radiation sensing elements. Crosstalk can be electrical, or optical, or both. Crosstalk can degrade CIS 10 performance if not mitigated.

The sensor wafer T1 may also include other types of microelectronic components, such as reset transistors, source follower transistors, transfer transistors, or other suitable devices. As will be discussed in more detail below with reference to FIGS. 1-10 , some of these microelectronic assemblies may be electrically coupled to protection devices, such as protection diodes. For example, the transfer gate of sensor wafer T1 may be electrically coupled to a protection diode, the details of which are discussed below.

With continued reference to FIG. 1 , sensor wafer T1 is bonded to logic wafer T2 . Specifically, the front side 30 (opposite the back side 20 ) of the sensor wafer T1 is bonded to the side 40 of the logic wafer T2 . Logic wafer T2 contains different microelectronic components than sensor wafer T1. For example, logic wafer T2 does not contain radiation sensing elements such as photodiodes. Instead, logic wafer T2 may include circuitry configured to operate the pixels of sensor wafer T1. For example, logic wafer T2 may include decoders, registers, multiplexers/demultiplexers, amplifiers, readout transistors, reference pixels, application specific integrated circuits (ASICs), and the like. These types of circuits are located on or near side 40, which may be referred to as the active side of logic wafer T2.

Each of the sensor wafer T1 and the logic wafer T2 includes interconnect structures, respectively. The interconnect structure includes a plurality of patterned dielectric and conductive layers that provide interconnects (eg, metal wiring) between various doped features, circuits, and inputs/outputs of the CIS 10 . In some embodiments, the interconnect structure may be a multilayer interconnect (MLI) structure that includes multiple metal layers (eg, Metal 0, Metal 1, Metal 2, etc.) formed in a configuration such that the interlayer dielectric (ILD) separates and isolates contacts, vias and metal lines of MLI structures. In one example, the MLI structures may include conductive materials such as aluminum, aluminum/silicon/copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal suicide, or combinations thereof, referred to as aluminum interconnects. Aluminum interconnects may be formed by processes including physical vapor deposition (PVD), chemical vapor deposition (CVD), or combinations thereof. Other fabrication techniques for forming aluminum interconnects may include photolithographic processing and etching for patterning conductive material for vertical connections (vias and contacts) and horizontal connections (wires). Alternatively, copper multilayer interconnects can be used to form metal patterns. The copper interconnect structure may include copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal suicide, or combinations thereof. Copper interconnects may be formed by techniques including CVD, sputtering, electroplating, or other suitable processes. It should be understood that other conductive materials (eg, cobalt, tungsten, or ruthenium) may also be used to form the various components of the MLI structure.

In the embodiment shown in FIG. 1 , the interconnect structures of the sensor wafer T1 are located on the front side 30 of the sensor wafer T1 , and the interconnect structures of the logic wafer T2 are located on the side 40 of the logic wafer T2 . Thus, the interconnect structures of the sensor wafer T1 are bonded to the interconnect structures of the logic wafer T2. In some embodiments, sensor wafer T1 includes a hydrophobic bonding layer (HBL) on front side 30, logic wafer T2 includes a HBL on side 40, and sensor wafer T1 and logic wafer T2 are bonded at least partially by They are carried out by their respective HBL.

Referring now to FIG. 2 , thinning process 50 is performed on logic wafer T2 from a side 60 of logic wafer T2 opposite side 40 . Side 60 may also be referred to as the backside of logic wafer T2, and side 40 may also be referred to as the front side of logic wafer T2. In some embodiments, the thinning process 50 may include a mechanical grinding process and/or a chemical thinning process. For example, during a mechanical grinding process, a substantial amount of material may be removed first from side 60 of logic wafer T2. Thereafter, a chemical thinning process may apply etch chemicals to the logic wafer T2 to further thin the logic wafer T2. In some embodiments, thinning process 50 may reduce logic wafer T2 from an initial thickness of between about 700-800 microns to a thickness of between about 2-3 microns.

After performing the thinning process 50 , through substrate vias (TSVs, also known as through silicon vias) are formed in the logic wafer T2 . The formation of such TSVs involves one or more etching, deposition or ashing processes, which may use plasma. Charges from the plasma may cause inadvertent damage to metallization features (eg, metal lines or vias/contacts) on the logic wafer T2, which is undesirable. To alleviate this problem, the present disclosure implements one or more protection diodes in logic die T2 and/or sensor die T1. As will be discussed in more detail below, the protection diode includes multiple doped regions that help release or otherwise dissipate plasma charges associated with the etch or metal deposition process used to form the TSV, which is One of the benefits provided by the present disclosure. It should also be understood that after performing the thinning process 50, HBLs may be formed on the side 60 of the logic wafer T2. For simplicity, the HBLs, TSVs and protection diodes are not specifically shown in Figure 2, although they will be shown and discussed in more detail in later figures, eg in Figures 5-6.

Referring now to FIG. 3 , another logic wafer T3 is provided. Similar to logic wafer 2 , logic wafer T3 may contain different microelectronic components than sensor wafer T1 . For example, logic wafer T3 does not contain radiation-sensing elements of sensor wafer T1, but rather contains radiation-sensing elements for operating sensor wafer T1 or otherwise electrically interacts with radiation-sensing elements of sensor wafer T1 circuit. Circuitry of logic wafer T3 may be primarily formed at or near side 70 of logic wafer T3 , which may be referred to as the active side of logic wafer T3 . Logic wafer T3 also has a side 80 opposite side 70 .

With continued reference to FIG. 3 , a bonding process 90 is performed on the CIS 10 to bond the side 70 of the logic wafer T3 to the side 60 of the logic wafer T2 . In some embodiments, HBL is formed on side 60 of logic wafer T2 and HBL is formed on side 70 of logic wafer T3 . Splicing can be performed at least in part by splicing the respective HBLs together.

Referring now to FIG. 4 , a thinning process 100 is performed on the CIS 10 to reduce the thickness of the sensor wafer T1 . Again, the thinning process 100 may include a mechanical grinding process and/or a chemical thinning process. For example, during a mechanical grinding process, a substantial amount of material may first be removed from side 20 of sensor wafer T1. Thereafter, a chemical thinning process may apply etch chemicals to the sensor wafer T1 to further thin the sensor wafer T1. After performing the thinning process 100 , openings for sensor elements may be formed on the side 20 of the sensor wafer T1 . These openings can be used for chip pads that are used to probe and/or test the CIS 10 .

5-6 are schematic partial cross-sectional side views of the CIS 10 according to one embodiment of the present disclosure. In more detail, FIG. 5 shows details of CIS 10 as a stack of three wafers bonded together: sensor wafer T1, logic wafer T2, and logic wafer T3, and FIG. 6 shows CIS 10 A magnified view of a portion of . In other words, the CIS 10 of FIGS. 5-6 has undergone the manufacturing steps discussed above in connection with FIGS. 1-4 . For reasons of consistency and clarity, similar components appearing in Figures 1-6 have the same label.

Referring to FIGS. 5-6 , the sensor wafer T1 is bonded to the logic wafer T2 through the bonding interface 140 , and the logic wafer T2 is bonded to the logic wafer T3 through the bonding interface 150 . For example, sensor wafer T1 includes one or more HBLs 160 formed on side 30, logic wafer T2 includes one or more HBLs 170 formed on side 40 and one or more HBLs 180 formed on side 60, and logic Wafer T3 includes one or more HBLs 190 formed on side 70 . One or more HBLs 160 of sensor wafer T1 are bonded to one or more HBLs 170 of logic wafer T2, and one or more HBLs 180 of logic wafer T2 are bonded to one or more HBLs 190 of logic wafer T3.

The sensor wafer T1 includes a substrate 200 , the logic wafer T2 includes a substrate 210 , and the logic wafer T3 includes a substrate 220 . As mentioned above, the substrates 200-220 may each comprise a semiconductor substrate, eg, a silicon substrate doped with a P-type dopant or an N-type dopant. In addition, the substrates 200, 210, or 220 may each include an epi layer, or may be strained to improve performance.

Circuitry or other microelectronic components may be formed in the substrates 200-220. For example, a photosensitive element such as a photodiode may be formed as part of pixel 225 in substrate 200 . The photodiode may be configured to sense or detect light or radiation waves entering the substrate 200 from the side 20 . Pixels 225 (including photodiodes) may collectively form a pixel grid array. Color filters and microlenses may be formed over each pixel to help filter out light of undesired wavelengths (eg, corresponding to various colors) and focus light of desired colors. In this regard, the color filter may enable filtering of radiation waves having different wavelengths, which may correspond to different colors, such as primary colors including red, green and blue, or complementary colors including cyan, yellow and magenta. The color filters may also be positioned such that desired incident optical radiation is directed onto and through the color filters. For example, a color filter may filter incident radiation so that only red light reaches a photodiode or another suitable radiation sensing element. The color filter may include a dye-based (or pigment-based) polymer or resin to achieve filtering of a specific wavelength band.

After the color filters are formed, microlenses are formed over the color filters. Microlenses help direct radiation to a photodiode or other suitable radiation sensing element. The microlenses may be positioned in various arrangements and have various shapes depending on the refractive index of the material used for the microlenses and the distance from the surface of the substrate 200 . In an embodiment, each microlens comprises an organic material, such as a photoresist material or a polymer material. Microlenses are formed by one or more photolithographic processes.

In addition to the pixel, the transistor 230 may be at least partially formed in the substrate 200 , the transistor 240 may be at least partially formed in the substrate 210 , and the transistor 245 may be at least partially formed in the substrate 220 . In some embodiments, transistor 230 may include a pass transistor. Each transfer transistor 230 has a transfer gate formed between a photosensitive element (eg, a photodiode, not shown in FIGS. 5-6 for simplicity) and a floating diffusion region. A transfer gate can be used to transfer the accumulated charge from the photosensitive element to the floating diffusion region. In some embodiments, transistor 230 may also be considered part of pixel 225 .

Meanwhile, transistors 240-245 may be part of a circuit configured to operate pixels of sensor wafer T1. For example, transistors 240-245 may be part of a decoder, register, multiplexer/demultiplexer, amplifier, readout transistor, reference pixel, application specific integrated circuit (ASIC), or the like. Transistors 240 - 245 may control or otherwise interact with the circuitry of pixel 225 and transfer transistor 230 .

According to various aspects of the present disclosure, protection diode 250 is also implemented in CIS 10 . In the embodiment shown in FIGS. 5-6 , protection diode 250 is implemented in logic wafer T2, but it should be understood that in other embodiments protection diode 250 (or other instances of protection diode 250 ) may be implemented. In sensor wafer T1 or logic wafer T3. The protection diode 250 includes a plurality of differently doped regions. For example, as described in detail with reference to FIG. Area 280. Doped regions 260 and 280 may have the same conductivity type, while doped region 270 has a different conductivity type than doped regions 260 and 280 . For example, in an embodiment where the substrate 210 is a P-type substrate, the doped regions 260 and 280 may be N-type doped regions, and the doped region 270 may be a P-type doped region.

In some embodiments, doped region 260 includes a deep N-well (labeled herein as DNW), which contains a lightly doped N-type material, and an N-well (labeled herein as NW), which contains a N-type material at a greater dopant concentration level for the N-well), and a heavily doped N-type region (labeled N+ herein) (which has an even greater dopant concentration than both the deep N-well and the N-well concentration level). The heavily doped N-type region is shallower (eg, has a shallower depth) within doped region 260 than the N-well, which is shallower than the deep N-well. Therefore, the N-type dopant concentration level within the doped region 260 may increase as the depth of the doped region 260 becomes shallower.

In some embodiments, doped region 270 includes a P-well (labeled herein as PW), which contains doped P-type material, and a heavily doped P-type region (labeled herein as P+), which contains a ratio P-well more doped heavily doped P-type material). The heavily doped P-type region is shallower (eg, has a shallower depth) than the P-well within doped region 270 . Therefore, the concentration level of the P-type dopant in the doped region 270 may also increase as the depth of the doped region 270 becomes shallower.

In some embodiments, doped region 280 includes a heavily doped N-type region (again labeled N+ herein). The dopant concentration levels of the doped region 280 , the heavily doped P-type region (ie, P+) of the doped region 270 and the heavily doped N-type region (ie, N+) of the doped region 260 may be the same as each other. For example, these dopant concentration levels may range between about 10 ¹⁰ /cm ² and about 10 ¹⁶ /cm ² . Meanwhile, the dopant concentration levels of the P-well of the doped region 270 and the N-well of the doped region 260 may range between about 10 ¹⁰ /cm ² and about 10 ¹⁶ /cm ² , and the depth of the doped region 260 The dopant concentration level of the N-well may range between about 10 ¹⁰ /cm ² and about 10 ¹³ /cm ² . These ranges are not chosen at random, but are specifically configured such that doped regions 260-280 will help protect the CIS from plasma damage and maintain proper electrical bias to prevent damage to the microelectronic components of the CIS 10.

For example, as discussed above with reference to FIG. 2 , the formation of CIS 10 includes forming TSVs 300 (labeled herein as BTSVs) in logic wafer T2 . The TSVs 300 each extend vertically in the Z direction through the substrate 210 of the logic wafer T2. To form such TSVs 300, one or more etching processes may be performed to etch openings in the substrate 210, and then a metal deposition process may be performed to replace them with a conductive material (e.g., copper, aluminum, tungsten, cobalt, ruthenium, or a combination thereof). ) to fill these openings. One or more etching or metal deposition processes may involve the application of plasma. Unfortunately, the electrical charges associated with the ambient plasma can adversely affect the various microelectronic components of the CIS 10 . For example, sensor wafer T1 may include interconnect structure 310 formed over substrate 200 , and logic wafer T2 may include interconnect structure 310 formed over substrate 210 and bonded to interconnect structure 310 (eg, via HBLs 160 and 170 ). ) interconnect structure 320. Each interconnect structure 310 and 320 may include multiple metal layers having metal lines that are electrically interconnected by conductive vias or contacts. These metallization features of interconnect structures 310 and 320 may be susceptible to damage from plasma charges (generated from etching or deposition processes performed as part of the formation of TSV 300 ). If left unchecked, damaged metallization features may degrade CIS 10 performance and/or reduce CIS 10 yield.

In order to overcome the above-mentioned problems, the present disclosure uses a protection diode 250 to discharge or diffuse plasma charges. For example, doped regions 260 , 270 , and 280 of protection diode 250 are each electrically coupled to interconnect structure 320 (and, by extension, interconnect structure 310 ) through corresponding vias and metal lines. Doped regions 260 , 270 , and/or 280 may help release charges that would otherwise accumulate on metallization features (eg, metal lines, vias, and contacts) of interconnect structures 320 and 310 . Therefore, metallization features are less likely to be damaged by plasma charges generated during the formation of TSV 300 . Furthermore, the performance and/or yield of the CIS 10 can be improved. Such an advantage is an inherent consequence of implementing protection diode 250 on logic wafer T2 (or sensor wafer T1 ) prior to performing the plasma-related process.

Protection diode 250 also protects various microelectronic components of CIS 10 during electrical operation of CIS 10 . For example, pass transistor 230 may operate within a voltage range between about −M volts (V) and about N volts, where M and N are positive numbers, respectively. For example, in an embodiment, M=1.2, N=3, which means that the voltage of pass transistor 230 can swing between about -1.2V and about 3V during electrical operation of CIS 10 . Pass transistor 230 is electrically coupled to substrate 210, which is considered to be electrically grounded. When pass transistor 230 swings to a sufficiently negative voltage, it may also pull down substrate 210 to a negative voltage. This would be undesirable because proper electrical biasing of the various circuits on logic wafer T2 (for their intended electrical operation) assumes that substrate 210 is at electrical ground, rather than at a negative voltage. Therefore, pulling substrate 210 to a negative voltage may adversely interfere with proper electrical operation of CIS 10 .

Here, the present disclosure electrically couples the protection diode 250 to the pass transistor 230 to prevent the aforementioned problems (eg, the substrate 210 being pulled to a negative voltage) from occurring. For example, doped region 260 is electrically biased to a first reference voltage (e.g., via conductive vias and metal lines of interconnect structure 320), and doped region 270 is electrically biased to a second reference voltage (e.g., via interconnect structure 320). another conductive via and metal line of interconnection structure 320 ), and doped region 280 of protection diode 250 is electrically coupled to the gate of pass transistor 230 through the conductive vias and metal line of interconnection structures 320 and 310 .

In the illustrated embodiment, the first reference voltage is a positive voltage, and the second reference voltage is a negative voltage that is more negative than the negative voltage of transistor 230 . For example, the first reference voltage may be about 2.8V, and the second reference voltage may be about −2V, which are common voltage references for other circuits in the logic wafer T2. Because transistor 230 can swing down to a negative voltage of -1.2V at most (where M=1.2) (e.g., to the lower end of its negative voltage range), the second reference voltage is even more negative than the most negative voltage value of pass transistor 230. more negative (for example, -2V is more negative than -1.2V). Such an electrical biasing scheme can effectively prevent the substrate 210 from being pulled to undesired negative voltages. For example, since the doped region 270 surrounds the doped region 280 in a cross-sectional view, the doped region 270 forms a P/N junction with the doped region 280 . When the pass transistor swings to -1.2V (ie, its most negative voltage), doped region 280 can be pulled to this negative voltage of -1.2V. However, doped region 270 is connected to -2V, which is a much more negative voltage than -1.2V at doped region 280 . This means that the P/N junction formed by doped regions 270 and 280 is still reverse biased, which causes very little, if any, current to flow. Thus, the substrate 210 is substantially unaffected (ie, not pulled down to the negative voltage of -1.2V of the pass transistor 230 ) during the entire voltage swing of the pass transistor 230 .

Note that if the doped region 270 is biased to a reference voltage greater than the voltage of the pass transistor (e.g., the second reference voltage is 0V instead of -2V), then the reverse bias condition may not be achieved, which will not prevent pass The negative voltage of the transistor pulls down the substrate 210 to a negative voltage. Accordingly, the present disclosure utilizes not only unique device configurations, but also novel electrical biasing schemes to achieve various operational benefits of the CIS 10 . These operational benefits (eg, isolating substrate 210 from undesired voltage variations) are an inherent consequence of implementing protection diode 250 with a particular configuration of doped regions 260-280 and applying a particular reference voltage.

Another unique physical characteristic of the present disclosure is that doped region 260 (as part of protection diode 250 ) is formed to surround doped region 270 in cross-sectional view. If doped region 260 is not formed, then doped region 270 will be in direct physical connection with substrate 210 . This means that the substrate 210 may have been pulled to any voltage of the second reference voltage, in this case -2V. As noted above, proper operation of many microelectronic components on the CIS 10 requires the substrate 210 to be electrically grounded. Therefore, the negative voltage of the substrate 210 due to the direct connection with the second reference voltage is also undesirable.

Here, the implementation of doped region 260 surrounding doped region 270 serves as an isolation barrier for the second reference voltage. Specifically, the P-type doped region 270 forms another P/N junction with the N-type doped region 260 . Because the N-type doped region 260 is biased to a positive first reference voltage (eg, 2.8V in this case), and the P-type doped region 270 is biased to a negative second reference voltage (eg, In this case -1.2V), so this P/N junction is still reverse biased, which means that little current flows as a result. Therefore, the substrate 210 is not affected by the negative second reference voltage biased by the doped region 270 . In addition, the substrate 210 itself may be a P-type substrate, and since the substrate 210 surrounds the N-type doped region 260 , the substrate 210 forms another P/N junction with the N-type doped region 260 . Since the P-type substrate is at electrical ground (0 volts) and the N-type doped region 260 is biased to a positive voltage (eg, 2.8V here), the P/N junction itself is also reverse biased. This reverse biased P/N junction further cuts off any potential current flow between the substrate 210 and the second reference voltage source. Thus, the substrate 210 is further isolated from other potential electrical disturbances and can still function properly as an electrical ground.

It should be understood that the above specific values of the first reference voltage and/or the second reference voltage are not intended to be limiting unless otherwise explicitly stated. For example, instead of 2.8V as its first reference voltage, other values of 2.5V, 3V or 3.3V could be used. As another example, instead of -2V as its second reference voltage, other values of -2.5V, -3V or -3.3V may also be used.

7-8 are schematic partial cross-sectional side views of a CIS 10 according to another embodiment of the present disclosure. In more detail, FIG. 7 shows details of CIS 10 as a stack of three wafers bonded together: sensor wafer T1, logic wafer T2, and logic wafer T3, and FIG. 8 shows CIS 10 A magnified view of a portion of . For reasons of consistency and clarity, similar components appearing in the embodiment of FIGS. 7-8 have the same numbering as similar components appearing in the embodiment of FIGS. 5-6 .

Referring to FIGS. 7-8 , sensor wafer T1 is bonded to logic wafer T2 via bonding interface 140 , and logic wafer T2 is bonded to logic wafer T3 via bonding interface 150 , eg, via HBLs 160 - 190 . As is the case in the embodiments of FIGS. 5-6 , the photodetection pixel and one or more transistors 230 may be at least partially formed in the substrate 200, and other transistors 240 and 245 may be at least partially formed in the substrate 210, respectively. and substrate 220 .

According to various aspects of the present disclosure, protection diode 250A is implemented in CIS 10 . In the embodiment shown in FIGS. 7-8 , protection diode 250A is implemented in logic wafer T2, but it should be understood that in other embodiments protection diode 250A (or other instances of protection diode 250A) may be implemented In sensor wafer T1 or logic wafer T3. Similar to the protection diode 250 of the embodiment corresponding to FIGS. 5-6 , the protection diode 250A of the embodiment of FIGS. 7-8 includes a plurality of differently doped regions for protecting the CIS 10 during its manufacture and operation. . However, while protection diode 250 includes three doped regions 260 , 270 and 280 , protection diode 250A includes two doped regions 275 and 285 . Doped region 275 is an N-type doped region embedded in substrate 210 , and doped region 285 is a P-type doped region embedded in doped region 275 . In some embodiments, the doped region 275 includes a lightly doped N-well and a heavily doped N-type portion (the heavily doped N-type portion is located on the surface of the substrate 210 or near the surface of the substrate 210 ), and the doped Region 285 includes a heavily doped P-type portion (the heavily doped P-type portion being located at or near the surface of substrate 210 ). In a cross-sectional view, doped region 285 is surrounded by doped region 275 (except for the upper surface of doped region 285 ). Doped region 285 is electrically connected to the gate of pass transistor 230 through metal lines and vias of interconnect structures 310 and 320 . Doped region 275 is electrically connected to a positive reference voltage, in this case 3.6V.

Although the construction and applied voltage references are different between protection diode 250 of FIGS. 5-6 and protection diode 250A of FIGS. 7-8 , protection diode 250A is still configured to maintain its P/N junction (e.g., One P/N junction formed by doped regions 285 / 275 and the other P/N junction formed by substrate 210 and doped region 275 ) are reverse biased regardless of the extent of the voltage swing of pass transistor 230 . That is, when the voltage of the pass transistor 230 swings between -1.2V and 3V, the protection diode 250A still keeps the substrate 210 from being pulled down to the negative voltage value of the pass transistor 230 . In addition, the protection diode 250A also protects the CIS 10 during the fabrication of the CIS 10 , for example, during the etching process used to form the TSV 300 of the logic wafer T2 . Similar to protection diode 250 discussed above, protection diode 250A can help discharge plasma charge that builds up due to etch or deposition processes (which use plasma), and thus, components of CIS 10 are less likely to Damaged during manufacture.

FIG. 9 is a schematic partial cross-sectional side view of a CIS 10 according to yet another embodiment of the present disclosure. Again, for reasons of consistency and clarity, similar components appearing in the embodiment of FIG. 9 have the same labeling as similar components appearing in the embodiment of FIGS. 5-8 .

In the embodiment of FIG. 9 , sensor wafer T1 is still bonded to logic wafer T2 via bonding interface 140 , and logic wafer T2 is still bonded to logic wafer T3 via bonding interface 150 , eg, via HBLs 160 - 190 . As is the case in the embodiments of FIGS. 5-8 , the photodetection pixel and one or more transistors 230 may be at least partially formed in the substrate 200, and other transistors 240 and 245 may be at least partially formed in the substrate 210, respectively. and substrate 220 .

However, unlike the embodiments of FIGS. 5-8 , the embodiment of FIG. 9 implements a protection diode 250 in the sensor wafer T1 . The protection diode 250 includes a doped region 260 embedded in the substrate 200 , a doped region 270 embedded in the doped region 260 , and a doped region 280 embedded in the P-type doped region 270 . As in the embodiment of FIGS. 5-6 , the doped regions 260 and 280 are doped with N-type dopants, and the doped region 270 is doped with P-type dopants. The doped regions 260 and 270 are electrically connected to a first reference voltage (eg, 2.8V) and a second reference voltage (eg, −2V) through vias and metal lines of the interconnection structure 310 , respectively. Doped region 280 is electrically connected to the gate of pass transistor 230 through vias and metal lines of interconnect structure 310 . Again, other voltage references discussed above in connection with the embodiments of FIGS. 5-6 may also be used here.

Similar to the protection diode 250 of the embodiment of FIGS. To form a P/N junction. And similar to the protection diode 250 of the embodiment of FIGS. 5-6 , the structural configuration and electrical biasing of the protection diode 250 here also help to maintain the P/N junction in reverse bias regardless of the voltage of the pass transistor 230 degree of swing. In other words, the protection diode 250 helps to isolate the substrate 210 from being pulled down to a negative voltage by the pass transistor 230 . In addition, the protection diode 250 also protects the CIS 10 during the manufacture of the CIS 10 , for example, during an etching or deposition process for forming the TSV 300 of the logic wafer T2 . Similar to protection diode 250 of the embodiment of FIGS. It is unlikely that components of the CIS 10 were damaged during the manufacture of the CIS 10.

FIG. 10 is a schematic partial cross-sectional side view of a CIS 10 according to yet another embodiment of the present disclosure. Again, for reasons of consistency and clarity, similar components appearing in the embodiment of Fig. 10 have the same labeling as similar components appearing in the embodiment of Figs. 5-9.

In the embodiment of FIG. 10 , sensor wafer T1 is still bonded to logic wafer T2 via bonding interface 140 , and logic wafer T2 is still bonded to logic wafer T3 via bonding interface 150 , eg, via HBLs 160 - 190 . As in the embodiments of FIGS. 5-9 , the photodetection pixel and one or more transistors 230 may be at least partially formed in the substrate 200, and other transistors 240 and 245 may be at least partially formed in the substrate 210, respectively. and substrate 220 .

However, unlike the embodiments of FIGS. 5-9 , the embodiment of FIG. 10 implements protection diode 250 in logic wafer T3 . The protection diode 250 includes a doped region 260 embedded in the substrate 220 , a doped region 270 embedded in the doped region 260 , and a doped region 280 embedded in the doped region 270 . As in the embodiment of FIGS. 5-6 , the doped regions 260 and 280 are doped with N-type dopants, and the doped region 270 is doped with P-type dopants. The doped regions 260 and 270 are electrically connected to a first reference voltage (eg, 2.8V) and a second reference voltage (eg, −2V) through vias and metal lines of the interconnection 330 of the logic wafer T3 , respectively. Doped region 280 is electrically connected to the gate of pass transistor 230 through vias and metal lines of interconnect structures 310-330. Again, other voltage references discussed above in connection with the embodiments of FIGS. 5-6 may also be used here.

Similar to the protection diode 250 in the embodiments of FIGS. To form a P/N junction. And similar to the protection diode 250 of the embodiment of FIGS. 5-6 , the structural configuration and electrical biasing of the protection diode 250 here also help to maintain the P/N junction in reverse bias regardless of the voltage of the pass transistor 230 degree of swing. In other words, the protection diode 250 helps to isolate the substrate 210 from being pulled down to a negative voltage by the pass transistor 230 .

FIG. 11 is a flowchart illustrating a method 800 of manufacturing an image sensor device according to an embodiment of the present disclosure. Method 800 includes step 810 of bonding a first side of a sensor wafer to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic die contains circuitry configured to operate the pixels. The sensor die or the first logic die contains protection diodes.

Method 800 includes step 820 of thinning the first logic wafer from a second side of the first logic wafer opposite the first side.

Method 800 includes step 830 of forming through substrate vias (TSVs) in a first logic wafer. The protection diodes protect the sensor wafer or the first logic wafer from damage during TSV formation.

Method 800 includes step 840 of bonding the second side of the first logic wafer to the second logic wafer.

Method 800 includes step 850 of thinning the sensor wafer from the second side of the sensor wafer.

In some embodiments, step 830 for forming TSVs includes performing one or more etching or deposition processes using plasma. A protection diode protects the sensor wafer or the first logic wafer from plasma damage.

In some embodiments, prior to step 810 for bonding the first side of the sensor wafer to the first side of the first logic wafer, the sensor wafer or the first logic wafer is at least in part by Forming a protection diode: forming a first doped region in the substrate of the sensor wafer or in the substrate of the first logic wafer; forming a second doped region in the first doped region, wherein the second doped The region has a different conductivity type than the first doped region; and a third doped region is formed in the second doped region, wherein the third doped region has the same conductivity type as the first doped region.

In some embodiments, the sensor wafer includes transfer gates.

It should be appreciated that method 800 may include further steps performed before, during, or after steps 810-850. For example, method 800 may include the steps of electrically biasing the first doped region to a first reference voltage, and electrically biasing the second doped region to a second reference voltage different from the first reference voltage. One of the first and second reference voltages is a positive voltage, and the other of the first and second reference voltages is a negative voltage. As another example, method 800 may include the step of electrically connecting the third doped region to the transfer gate. As yet another example, method 800 may include the step of electrically operating an image sensor device. The protection diode protects the image sensor device during electrical operation of the image sensor device. The image sensor device can be operated by applying a voltage between -M volts to N volts to the transfer gate. The second reference voltage is a negative voltage that is more negative than -M volts. Other steps of method 800 may include the steps of forming color filters and microlenses. For simplicity, these additional steps are not discussed in detail in this article.

FIG. 12 illustrates an integrated circuit fabrication system 900 according to an embodiment of the disclosure. The manufacturing system 900 includes a plurality of entities 902 , 904 , 906 , 908 , 910 , 912 , 914 , 916 . . . , N connected by a communication network 918 . Network 918 may be a single network or may be a variety of different networks, such as an intranet and the Internet, and may include wired and wireless communication channels.

In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; and entity 906 represents an engineer, such as a process engineer controlling a process and associated recipe, or monitoring or adjusting Equipment Engineer for Conditioning and Setup of Processing Tools; Entity 908 represents Metrology Tools for IC Test and Measurement; Entity 910 represents Semiconductor Processing Tools, such as EUV Tools for performing photolithography processes to define gate spacers for SRAM devices; Entity 912 represents a virtual metrology module associated with processing tool 910 ; entity 914 represents a high-level process control module associated with processing tool 910 as well as additional other processing tools; and entity 916 represents a sampling module associated with processing tool 910 .

Each entity may interact with other entities and may provide integrated circuit fabrication, process control and/or computing capabilities to other entities and/or receive such capabilities from other entities. Each entity may also include one or more computer systems that perform computations and perform automation. For example, the high-level processing control module of entity 914 may include a piece of computer hardware having software instructions encoded therein. Computer hardware can include hard drives, flash drives, CD-ROMs, RAM memory, display devices (eg, monitor), input/output devices (eg, mouse and keyboard). Software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

Integrated circuit fabrication system 900 enables interaction between entities for the purposes of integrated circuit (IC) fabrication and high-level process control of IC fabrication. In an embodiment, advanced process control includes adjusting processing conditions, settings, and/or recipes applicable to a processing tool for an associated wafer based on metrology results.

In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and/or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to optimal sampling fields/points determined based on various characteristics of process quality and/or product quality.

Among the capabilities provided by the IC manufacturing system 900 is enabling collaboration and access to information in areas such as design, engineering and processing, metrology, and advanced process control. Another capability provided by IC fabrication system 900 may be to integrate the system between facilities, such as between metrology tools and processing tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable more efficient incorporation of manufacturing information into manufacturing process or APC modules, and wafer data from in-line or field measurements can be implemented using metrology tools integrated in related processing tools.

The advanced photolithographic processes, methods and materials described above can be used in many applications, including the implementation of transistors as Fin Field Effect Transistors (FinFETs). For example, the fins can be patterned to create relatively tight pitches between features, for which the above disclosure is well suited. Furthermore, the spacers (also referred to as mandrels) used to form the fins of the FinFETs can be processed according to the above disclosure. It should also be understood that transistors may also be implemented using multi-channel devices, such as gate all around (GAA) devices. To the extent this disclosure relates to fin structures or FinFET devices, such discussions may apply equally to GAA devices.

The present disclosure may provide advantages over conventional devices. It should be understood, however, that not all advantages are discussed herein, that different embodiments may provide different advantages, and that no particular advantage is required by any embodiment. One advantage is to protect the CIS device during its manufacture. As mentioned above, the fabrication of a CIS device may include performing one or more processes involving the use of plasma, for example, an etch process for etching the opening of a through substrate via, a metal deposition process to fill the etched opening, or an ash. chemical process. When the plasma from these processes is exposed to various components of the CIS device (eg, metallization features), it can damage the CIS device. By implementing protection diodes in the sensor wafer or in the logic wafer bonded to the sensor wafer, the plasma can be released or otherwise diffused by the protection diodes, reducing the likelihood of any damage to the CIS device from the plasma. This advantage is an inherent consequence of implementing protection diodes on the appropriate wafers prior to performing the plasma process.

Another advantage is to protect the CIS device during operation of the CIS device. As mentioned above, some circuits (eg, the pass transistors of a sensor wafer) may swing between negative and positive voltage ranges. When the pass transistor swings to a negative voltage, the pass crystal may pull the substrate of the logic wafer down to a negative voltage, which is undesirable because intended operation of circuits on the logic wafer assumes that the substrate is at electrical ground. Here, by electrically connecting the respective doped regions of the protection diodes to the pass transistors as well as a predefined voltage reference, the P/N junctions of the protection diodes are kept reverse biased, which prevents current from flowing, thereby reducing the substrate of the logic wafer. Possibility of any negative voltage pulled down to the pass transistor. This advantage is another inherent result of the protection diode's unique structural configuration and the specific biasing scheme applied to it. Other advantages may include compatibility with existing manufacturing processes and ease and low cost of implementation.

One aspect of the present disclosure relates to an image sensor device. The image sensor device includes a first substrate including a plurality of pixels and at least one transistor. The image sensor device includes a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels. The image sensor device includes a protection diode disposed in the first substrate or in the second substrate. The protection diode includes: a first doped region, a second doped region arranged in the first doped region, and a third doped region arranged in the second doped region. The first doped region and the third doped region have the same conductivity type. The second doped region has a different conductivity type than the first and third doped regions. The third doped region is electrically coupled to the transistor of the first substrate.

Another aspect of the present disclosure relates to an image sensor device. An image sensor device includes a sensor substrate including a plurality of pixels and a transfer gate. The pixels are configured to detect radiation entering the sensor substrate through the backside of the sensor substrate. The image sensor device includes a first non-sensor substrate bonded to the sensor substrate through the front side of the sensor substrate, the first non-sensor substrate including circuitry configured to operate the pixels. The image sensor device includes a second non-sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate including the Other circuitry configured to operate the pixel. The image sensor device includes one or more protection diodes implemented in the sensor substrate, the first non-sensor substrate or the second non-sensor substrate. Each of the one or more protection diodes includes a first doped well, a second doped well within the first doped well, and a third doped well within the second doped well. The second doped well has a different conductivity type than the first and third doped wells. The first doped well is electrically connected to a first reference voltage. The second doped well is electrically connected to a second reference voltage different from the first reference voltage. The third doped well is electrically connected to the transfer gate.

Yet another aspect of the disclosure relates to a method. The first side of the sensor wafer is bonded to the first side of the first logic wafer. The sensor wafer contains pixels configured to detect radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic die contains circuitry configured to operate the pixels. The sensor die or the first logic die contains protection diodes. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. Through-substrate vias (TSVs) are formed in a first logic wafer. The protection diodes protect the sensor wafer or the first logic wafer from damage during TSV formation. The second side of the first logic die is bonded to the second logic die. The sensor wafer is thinned from the second side of the sensor wafer.

The foregoing outlines features of some embodiments so that those of ordinary skill in the art may better understand various aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes as the embodiments introduced herein, and/or achieve the same The same advantages of the introduced embodiments. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is an image sensor device comprising: a first substrate including a plurality of pixels and at least one transistor; a second substrate bonded to the first substrate, the second substrate including a The above-mentioned pixel interaction circuit; and a protection diode, disposed in the first substrate or in the second substrate, the protection diode includes: a first doped region, disposed in the first doped region The second doped region, and the third doped region disposed in the second doped region; wherein: the first doped region and the third doped region have the same conductivity type; the A second doped region has a different conductivity type than the first doped region and the third doped region; and the third doped region is electrically coupled to a transistor of the first substrate.

Example 2 is the image sensor device of Example 1, wherein: the first doped region is electrically coupled to a first reference voltage; and the second doped region is electrically coupled to a first reference voltage different from the first reference voltage. Two reference voltages.

Example 3 is the image sensor device of Example 2, wherein the first reference voltage is a positive voltage, and the second reference voltage is a negative voltage.

Example 4 is the image sensor device of example 3, wherein: when the image sensor device is operating, a voltage associated with the transistor swings from -M volts to N volts; and the negative of the second reference voltage The voltage is more negative than -M volts.

Example 5 is the image sensor device of example 1, wherein the transistor includes a transfer gate.

Example 6 is the image sensor device of example 1, wherein: the protection diode is implemented in the first substrate but not in the second substrate; or the protection diode is implemented in within the second substrate, but not implemented within the first substrate.

Example 7 is the image sensor device of example 1, wherein: a first instance of the protection diode is implemented in the first substrate; and a second instance of the protection diode is implemented in the second substrate Bottom inside.

Example 8 is the image sensor device of Example 1, wherein: the first substrate includes a first surface and a second surface opposite the first surface; the first substrate includes a plurality of pixels, the A plurality of pixels is configured to detect light entering the first substrate from the first surface; and the second substrate is bonded to the second surface of the first substrate.

Example 9 is the image sensor device of Example 1, further comprising: a third substrate bonded to the second substrate or the first substrate.

Example 10 is the image sensor device of Example 9, wherein: the first substrate is part of a sensor wafer; the second substrate is part of a first logic wafer; the third substrate is a a portion of two logic wafers; the first surface of the first logic wafer is bonded to the second logic wafer; and the second surface of the first logic wafer is bonded to the sensor wafer.

Example 11 is the image sensor device of example 9, wherein: the first substrate is part of a first sensor wafer; the third substrate is part of a second sensor wafer; the second substrate is part of a logic wafer; and the first sensor wafer is bonded to the logic wafer through the second sensor wafer.

Example 12 is an image sensor device comprising: a sensor substrate including a plurality of pixels and a transfer gate, wherein the pixels are configured to detect radiation of the substrate; a first non-sensor substrate bonded to the sensor substrate through the front side of the sensor substrate, the first non-sensor substrate including circuitry configured to operate the pixels; a second non-sensor substrate a sensor substrate bonded to the first non-sensor substrate such that the first non-sensor substrate is bonded between the sensor substrate and the second non-sensor substrate, the second non-sensor substrate The bottom includes other circuitry configured to operate the pixel; one or more protection diodes, implemented in the sensor substrate, the first non-sensor substrate, or the second non-sensor substrate; wherein: Each of the one or more protection diodes includes: a first doped well, a second doped well within the first doped well, and a first doped well within the second doped well Three doped wells; the second doped well has a different conductivity type from the first doped well and the third doped well; the first doped well is electrically connected to a first reference voltage; the The second doped well is electrically connected to a second reference voltage different from the first reference voltage; and the third doped well is electrically connected to the transfer gate.

Example 13 is the image sensor device of example 12, wherein: the first reference voltage is a positive voltage; the second reference voltage is a negative voltage; and during operation of the image sensor device, the transfer gate has A voltage in a range between -M volts and N volts, where -M volts is a negative voltage that is less negative than the second reference voltage.

Example 14 is the image sensor device of example 12, wherein the one or more protection diodes include at least a first protection diode embedded in the sensor substrate and a first protection diode embedded in the first non-sensor substrate. second protection diode.

Example 15 is a method of fabricating an image sensor device comprising: bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer contains pixels configured to detecting radiation entering the sensor wafer through a second side of the sensor wafer opposite the first side, wherein the first logic die contains circuitry configured to operate the pixels, and wherein the The sensor wafer or the first logic wafer includes protection diodes; the first logic wafer is thinned from a second side of the first logic wafer opposite the first side; forming through-substrate vias (TSVs) in a logic wafer, wherein the protection diode protects either the sensor wafer or the first logic wafer from damage during the TSV formation; the first logic bonding the second side of the wafer to a second logic wafer; and thinning the sensor wafer from the second side of the sensor wafer.

Example 16 is the method of example 15, wherein: forming the TSVs comprises: performing one or more etch or deposition processes using a plasma; and the protection diode protects the sensor wafer or the first logic die Circles are protected from the plasma damage.

Example 17 is the method of example 15, further comprising: prior to bonding the first side of the sensor wafer to the first side of the first logic wafer, bonding the sensor wafer at least in part by Forming the protection diode in the circle or in the first logic wafer: forming a first doped region in the substrate of the sensor wafer or in the substrate of the first logic wafer; forming a second doped region in the first doped region, wherein the second doped region has a different conductivity type from the first doped region; and forming a third doped region in the second doped region a doped region, wherein the third doped region has the same conductivity type as the first doped region.

Example 18 is the method of Example 17, wherein the sensor wafer includes transfer gates, and wherein the method further comprises: electrically biasing the first doped region to a first reference voltage; The second doped region is electrically biased to a second reference voltage different from the first reference voltage, wherein one of the first reference voltage and the second reference voltage is a positive voltage, and the first The other of a reference voltage and the second reference voltage is a negative voltage; and electrically connecting the third doped region to the transfer gate.

Example 19 is the method of example 18, further comprising electrically operating the image sensor device, wherein the protection diode protects the image sensor device during electrical operation of the image sensor device.

Example 20 is the method of example 19, wherein: electrically operating the image sensor device comprises: applying a voltage between -M volts and N volts to the transfer gate; and the second reference voltage is greater than -M volts Volts are more negative voltages.

Claims (10)

1. An image sensor device, comprising: a first substrate including a plurality of pixels and at least one transistor; a second substrate bonded to the first substrate, the second substrate including circuitry for interacting with the pixels; and a protection diode, disposed in the first substrate or in the second substrate, the protection diode comprising: a first doped region, a second doped region disposed in the first doped region, and a third doped region disposed within the second doped region; in: the first doped region and the third doped region have the same conductivity type; the second doped region has a different conductivity type than the first and third doped regions; and The third doped region is electrically coupled to a transistor of the first substrate. 2. The image sensor device according to claim 1, wherein: the first doped region is electrically coupled to a first reference voltage; and The second doped region is electrically coupled to a second reference voltage different from the first reference voltage. 3. The image sensor device according to claim 2, wherein the first reference voltage is a positive voltage, and the second reference voltage is a negative voltage. 4. The image sensor device according to claim 3, wherein: a voltage associated with the transistor swings from -M volts to N volts when the image sensor device is operating; and The negative voltage of the second reference voltage is more negative than -M volts. 5. The image sensor device of claim 1, wherein the transistor comprises a transfer gate. 6. The image sensor device according to claim 1, wherein: the protection diode is implemented in the first substrate but not in the second substrate; or The protection diode is implemented in the second substrate but not in the first substrate. 7. The image sensor device according to claim 1, wherein: a first instance of the protection diode is implemented within the first substrate; and A second instance of the protection diode is implemented within the second substrate. 8. The image sensor device according to claim 1, wherein: The first substrate includes a first surface and a second surface opposite the first surface; the first substrate includes a plurality of pixels configured to detect light entering the first substrate from the first surface; and The second substrate is bonded to the second surface of the first substrate. 9. An image sensor device, comprising: a sensor substrate comprising a plurality of pixels and a transfer gate, wherein the pixels are configured to detect radiation entering the sensor substrate through the backside of the sensor substrate; a first non-sensor substrate bonded to the sensor substrate through the front side of the sensor substrate, the first non-sensor substrate including circuitry configured to operate the pixels; A second non-sensor substrate bonded to said first non-sensor substrate such that said first non-sensor substrate is bonded between said sensor substrate and said second non-sensor substrate, said second non-sensor substrate the non-sensor substrate includes other circuitry configured to operate the pixel; one or more protection diodes implemented in the sensor substrate, the first non-sensor substrate or the second non-sensor substrate; in: Each of the one or more protection diodes includes a first doped well, a second doped well within the first doped well, and a first doped well within the second doped well. Three doped wells; the second doped well has a different conductivity type than the first doped well and the third doped well; The first doped well is electrically connected to a first reference voltage; the second doped well is electrically connected to a second reference voltage different from the first reference voltage; and The third doped well is electrically connected to the transfer gate. 10. A method of manufacturing an image sensor device, comprising: bonding a first side of a sensor wafer to a first side of a first logic wafer, wherein the sensor wafer includes pixels configured to detect Radiation entering the sensor wafer from the second side, wherein the first logic die contains circuitry configured to operate the pixels, and wherein either the sensor die or the first logic die contains a protective diode; thinning the first logic wafer from a second side of the first logic wafer opposite the first side; forming through-substrate vias (TSVs) in the first logic wafer, wherein the protection diodes protect the sensor wafer or the first logic wafer from damage during formation of the TSVs; bonding the second side of the first logic wafer to a second logic wafer; and The sensor wafer is thinned from a second side of the sensor wafer.