CN116541151A - Thread scheduling method, device, electronic device and medium - Google Patents

Abstract

The application discloses a thread scheduling method, a thread scheduling device, electronic equipment and a thread scheduling medium, and belongs to the field of communication. The thread scheduling method comprises the following steps: acquiring first information under the condition of displaying a user interface of a target application; scheduling a target thread from a first processor core to a second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state, wherein the target thread is used for displaying the user interface of the target application; wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.

Description

Thread scheduling method, device, electronic device and medium

technical field

The present application belongs to the communication field, and in particular relates to a thread scheduling method, device, electronic equipment and medium.

Background technique

Usually, in a scenario where a user uses an electronic device to view a user interface, the electronic device can schedule a thread related to displaying the user interface to a small core for processing, thereby processing the process of displaying the user interface to display the content of the user interface.

However, in the related art, when the user uses the electronic device to view the user interface, there is a problem of stuttering.

Contents of the invention

The purpose of the embodiments of the present application is to provide a thread scheduling method, device, electronic device and medium, which can improve the fluency of displaying a user interface on the electronic device.

In the first aspect, the embodiment of the present application provides a method for thread scheduling, the method includes: when the user interface of the target application is displayed, acquiring first information; when the first information indicates the user interface of the target application In the case of an interface update state, the target thread is scheduled from the first processor core to run on the second processor core, and the target thread is used to display the user interface of the target application; wherein, the first processor The operating frequency of the core is lower than the operating frequency of the second processor core.

In the second aspect, the embodiment of the present application provides a thread scheduling device, which includes: an acquisition module and a scheduling module, wherein: the acquisition module is configured to acquire the first information when the user interface of the target application is displayed; The scheduling module is configured to schedule the target thread from the first processor core to the second processor core when the first information acquired by the acquiring module indicates that the user interface of the target application is in an interface update state The target thread is used to display the user interface of the target application; wherein, the operating frequency of the first processor core is lower than the operating frequency of the second processor core.

In the third aspect, the embodiment of the present application provides an electronic device, the electronic device includes a processor and a memory, and the memory stores programs or instructions that can run on the processor, and when the programs or instructions are executed by the processor, the first aspect is implemented. steps of the method.

In a fourth aspect, the embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method in the first aspect are implemented.

In the fifth aspect, the embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the method in the first aspect.

In a sixth aspect, an embodiment of the present application provides a computer program product, the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the method in the first aspect.

In this embodiment of the present application, the electronic device may acquire the first information when the user interface of the target application is displayed, and when the first information indicates that the user interface of the target application is in an interface update state, the target thread is changed from the first A processor core is scheduled to run on the second processor core, and the target thread is used to display the user interface of the target application, wherein the operating frequency of the first processor core is lower than the operating frequency of the second processor core. Based on this solution, the target thread is scheduled to run on the second processor core with a higher operating frequency, so as to avoid the user interface of the target application from being stuck during the update process and improve the fluency of the electronic device displaying the user interface. .

Description of drawings

FIG. 1 is one of the schematic flow diagrams of a thread scheduling method provided in an embodiment of the present application;

Fig. 2 is the second schematic flow diagram of a thread scheduling method provided by the embodiment of the present application;

Fig. 3 is the third schematic flow diagram of a thread scheduling method provided by the embodiment of the present application;

FIG. 4 is the fourth schematic flow diagram of a thread scheduling method provided by an embodiment of the present application;

FIG. 5 is the fifth schematic flow diagram of a thread scheduling method provided by an embodiment of the present application;

FIG. 6 is one of the structural schematic diagrams of the thread scheduling device provided by the embodiment of the present application;

Fig. 7 is the second structural schematic diagram of the thread scheduling device provided by the embodiment of the present application;

FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of hardware of an electronic device provided by an embodiment of the present application.

Detailed ways

The following will clearly describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, but not all of them. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in this application belong to the protection scope of this application.

Terms involved in the embodiments of the present application will be described below.

With the development of electronic equipment technology, the architecture design of the central processing unit (Central Processing Unit, CPU), which is the core component of the electronic equipment, is becoming more and more diverse. At present, the architecture design of the CPU may include super-large cores, large cores and small cores. Among them, the ultra-large core has the strongest performance, the highest power, and the highest operating frequency, followed by the large core, and the third is the small core. Therefore, the ultra-large core and the large core can speed up task processing and are responsible for running some high-load scenarios, such as: running at the same time Multiple applications, run gaming apps, etc. The small core is responsible for running some low-load scenarios, such as: networking of applications, running in the background, etc.

The terms "first", "second" and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific sequence or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or described herein and that references to "first", "second", etc. to distinguish Objects are generally of one type, and the number of objects is not limited. For example, there may be one or more first objects. In addition, "and/or" in the specification and claims means at least one of the connected objects, and the character "/" generally means that the related objects are an "or" relationship.

The thread scheduling method, device, electronic device, and medium provided by the embodiments of the present application will be described in detail below through specific embodiments and application scenarios with reference to the accompanying drawings.

The thread scheduling method provided by the embodiment of the present application is applied to a scenario where the user interface of an application freezes when it is in an update state. The specific application scenario can be determined according to the usage requirements, and is not limited in this application.

Usually, when a user uses an electronic device to view a user interface such as a webpage, the electronic device can dispatch relevant threads for displaying the webpage to the small core for processing, thereby processing the process of displaying the webpage to display the page content of the webpage. However, since the user may quickly slide the list when the user uses the electronic device to view the webpage, it may take a long time to display the content of the page after the slide, and therefore, a jam occurs during the page slide process. pause.

In this embodiment of the present application, the electronic device may acquire the first information when the user interface of the target application is displayed, and when the first information indicates that the user interface of the target application is in an interface update state, the target thread is changed from the first A processor core is scheduled to run on the second processor core, and the target thread is used to display the user interface of the target application, wherein the operating frequency of the first processor core is lower than the operating frequency of the second processor core. Based on this solution, the target thread is scheduled to run on the second processor core with a higher operating frequency, so as to avoid the user interface of the target application from being stuck during the update process and improve the fluency of the electronic device displaying the user interface. .

The execution subject of the thread scheduling method provided by the embodiment of the present invention may be an electronic device, or may be a functional module and/or a functional entity in the electronic device that can implement the thread scheduling method. The following will take the electronic device as an example to describe the embodiment of the present application. The technical solutions provided are explained.

The embodiment of the present application provides a thread scheduling method. As shown in FIG. 1, the thread scheduling method may include the following steps 201 and 202:

Step 201: The electronic device acquires first information when displaying a user interface of a target application.

In the embodiment of the present application, the above first information is used to indicate an interface update status of the user interface of the target application.

In some embodiments of the present application, the first information includes: a first operating frequency of the first processor core, first interface information and second interface information of the user interface.

It should be noted that the above-mentioned first interface information and second interface information are interface information of the user interface of the target application acquired at different times.

In this embodiment of the present application, the aforementioned target application may be an application running in the foreground.

In some embodiments of the present application, the above-mentioned target application may be any of the following: a video application, a communication application, an editing application, a search application, a document application, and the like.

In some embodiments of the present application, the aforementioned user interface may be a page including list content or an interface including a scroll bar in the target application.

In the embodiment of the present application, when the desktop is displayed, the electronic device may, according to the user's click input on the application identifier of the target application, for example, click input on the application icon of the target application, so that the electronic device displays the user interface corresponding to the target application , so as to obtain the first information.

Step 202: When the first information indicates that the user interface of the target application is in an interface update state, the electronic device schedules the target thread from the first processor core to run on the second processor core.

In the embodiment of the present application, the above-mentioned target thread is used to display the user interface of the target application.

In the embodiment of the present application, the operating frequency of the first processor core is lower than the operating frequency of the second processor core.

In some embodiments of the present application, the CPU may include at least two processor cores. It can be understood that the foregoing processor core is a core of a CPU.

In this embodiment of the present application, the at least two processor cores may be at least one first processor core, at least one second processor core, and at least one third processor core.

In the embodiment of the present application, the operating frequency of the first processor core is higher than the operating frequency of the third processor core.

It should be noted that if the electronic device determines that the user interface of the target application is in a high-load scenario such as the interface update state, for example, during the process of the user rapidly sliding the user interface of the target application, the second processor with a higher operating frequency can core to improve the processing performance of the CPU; if the electronic device determines that the target application is running in the background and other low-load scenarios, for example, the application is in the process of networking, it can use the second processor core or the third processor core with a lower operating frequency processor core to improve CPU performance.

In the embodiment of the present application, when the electronic device is started to run the target application, the first processor core or the third processor core of the CPU can run and start the thread related to the target application, so as to display the user interface of the target application.

In the embodiment of the present application, the first information indicates that the user interface of the target application is in an interface update state, for example, it may be that the user interface of the target application is in a sliding state.

In the embodiment of the present application, the foregoing operating frequency is an actual frequency of the processor core when it is currently running.

In some embodiments of the present application, the above operating frequency may be related to at least one of the following: computing capability, instantaneous response capability, power consumption, and the like.

It can be understood that the higher the operating frequency of the processor core, the higher the computing capability, instantaneous response capability and power consumption of the processor core.

It should be noted that, when the electronic device determines that the user interface of the target application is in an update state, it obtains the target thread displaying the user interface of the target application, and then schedules the target thread from the first processor core to the second processor core run.

In this embodiment of the present application, the electronic device may obtain the first information when displaying the user interface of the target application, and determine whether the user interface of the target application is in the interface update state based on the first information. If the user interface of the target application is in the interface If the status is updated, it means that the target application is running under a high load. If the first processor core with a lower operating frequency is continued to be used, the target thread displaying the user interface of the target application, the computing power of the CPU, and the instantaneous response capability may appear. In the case of a mismatch, it takes a long time to display the updated user interface. Therefore, when the first information indicates that the user interface of the target application is in the state of interface update, the target thread is scheduled from the first processor core to the second It runs on the processor core to improve the performance of the CPU.

Optionally, in this embodiment of the present application, as shown in FIG. 2 , the above first information includes: the first operating frequency of the first processor core, and the above step 202 can be specifically implemented through the following step 202a1:

Step 202a1: When the first operating frequency is greater than or equal to the second operating frequency, the electronic device schedules the target thread from the first processor core to run on the second processor core.

In the embodiment of the present application, the second operating frequency includes any of the following: a preset operating frequency, and an operating frequency of the first processor core before obtaining the first operating frequency.

In some embodiments of the present application, the preset frequency may be a working frequency when the CPU of the electronic device cannot smoothly process multi-thread tasks.

In the embodiment of the present application, if the first operating frequency of the first processor core is greater than or equal to the second operating frequency, it may be considered that the user interface of the target application is in an interface updating state.

Optionally, in this embodiment of the present application, as shown in FIG. 3 , the above-mentioned first information includes first interface information and second interface information of the user interface, and the above-mentioned first interface information and second interface information are acquired at different times For the interface information of the user interface of the target application, the above step 202 can be specifically implemented through the following step 202b1:

Step 202b1: When the first interface information does not match the second interface information, the electronic device schedules the target thread from the first processor core to run on the second processor core.

In some embodiments of the present application, the acquisition time of the above-mentioned first interface information may be earlier than the acquisition time of the second interface information, and may also be later than the acquisition time of the second interface information.

In the embodiment of the present application, if the above-mentioned first interface information does not match the second interface information, it may be understood that the first interface information is different from the second interface information.

In this embodiment of the present application, if the first interface information does not match the second interface information, it means that the user interface of the target application is in an interface update state.

It should be noted that, when the user interface of the target application is in an update state, since the user performs sliding input on the user interface of the target application, the first interface information and the second interface information of the user interface of the target application acquired by the electronic device at different times The information on the two interfaces does not match, that is, the user interface of the target application is in an update state.

In this embodiment of the present application, the electronic device may acquire the first information when the user interface of the target application is displayed, and when the first information indicates that the user interface of the target application is in an interface update state, the target thread is changed from the first A processor core is scheduled to run on the second processor core, and the target thread is used to display the user interface of the target application, wherein the operating frequency of the first processor core is lower than the operating frequency of the second processor core. Based on this solution, the target thread is scheduled to run on the second processor core with a higher operating frequency, so as to avoid the user interface of the target application from being stuck during the update process and improve the fluency of the electronic device displaying the user interface. .

Optionally, in this embodiment of the present application, the "target thread" in step 202 may include at least one of the following: a main thread and a rendering thread.

In the embodiment of the present application, the above-mentioned main thread is a thread for obtaining relevant data of display content in an application page, and the above-mentioned rendering thread is for a thread for rendering display content in an application page. Wherein, the above-mentioned main thread is synchronized with the above-mentioned rendering thread, and the electronic device also obtains the rendering thread when obtaining the main thread, in other words, the electronic device also obtains the main thread when obtaining the rendering thread.

In the embodiment of the present application, the electronic device may acquire the target thread according to the thread identifier.

Optionally, in the embodiment of the present application, as shown in FIG. 4 , before "scheduling the target thread from the first processor core to the second processor core to run" in the above step 202, the embodiment of the present application The provided thread scheduling method also includes the following steps 301 and 302:

Step 301: The electronic device acquires a target thread identifier when the first information indicates that the user interface of the target application is in an interface update state.

In the embodiment of the present application, the target thread identifier is used to indicate the target thread.

In some embodiments of the present application, the target thread identifier may include at least one of the following: target thread ID, target thread number, and the like.

Step 302: The electronic device obtains the target thread according to the target thread identifier.

In this embodiment of the application, one thread identifier corresponds to one thread.

In some embodiments of the present application, the electronic device may obtain all thread identifiers related to the target application from the CPU, and based on these thread identifiers, obtain the target thread identifier for displaying the user interface of the target application, and then determine the target thread identifier according to the target thread identifier. thread.

It can be seen that since the electronic device can obtain the target thread according to the target thread identifier, it can accurately find the target thread for displaying the user interface of the target application from multiple threads, and therefore, the accuracy of obtaining the target thread by the electronic device can be improved.

Optionally, in the embodiment of the present application, as shown in FIG. 5 , before "scheduling the target thread from the first processor core to the second processor core to run" in the above step 202, the embodiment of the present application The provided thread scheduling method also includes the following step 401:

Step 401: When the first information indicates that the user interface of the target application is in an interface update state, the electronic device increases the first priority of the target thread.

In the embodiment of the present application, the above-mentioned first priority includes at least one of the following: a scheduling priority scheduled to run on the second processor core, and an running priority after being scheduled to the second processor core.

Example 1, when the user interface of the target application is in an update state, the electronic device increases the scheduling priority of the target thread for displaying the user interface of the target application, that is, before scheduling the target thread to run on the second processor core , increasing the scheduling priority of the target thread being scheduled to run on the second processor core, so that the target thread can be preferentially scheduled to run on the second processor core.

Example 2, when the user interface of the target application is in an update state, the electronic device increases the running priority of the target thread used to display the user interface of the target application, that is, after the target thread is scheduled to the second processor core, the priority is increased. The priority of the target thread running on the second processor core, so that the target thread can run preferentially on the second processor core.

It can be seen that, since the electronic device can increase the priority of the target thread, the target thread can be preferentially scheduled to run on the second processor core, or run preferentially on the second processor core. Therefore, the task scheduling response corresponding to the target thread can be accelerated and fully supported by the computing power of the second processor core, thus increasing the execution speed of the task corresponding to the target thread of the electronic device.

Optionally, in the embodiment of the present application, the CPU further includes a third processor core. After the above step 201, the thread scheduling method provided in the embodiment of the present application further includes the following step 501.

Step 501: When the first information indicates that the user interface of the target application is not in an interface update state, the electronic device schedules the target thread from the first processor core to run on the third processor core.

In the embodiment of the present application, the operating frequency of the third processor core is lower than the operating frequency of the first processor core.

In the embodiment of the present application, the above-mentioned first information indicates that the user interface of the target application is not in the interface update state, which may be understood as the first information indicates that the user interface of the target application is in the interface static state.

In some embodiments of the present application, the above-mentioned first information includes the first operating frequency of the first processor core. If the first operating frequency is lower than the second operating frequency, it means that the user interface of the target application is not updating the interface. state.

In some embodiments of the present application, the above-mentioned first information includes the first interface information and the second interface information. If the first interface information does not match the second interface information, it means that the user interface of the target application is not in the interface update status.

In some embodiments of the present application, if the first information indicates that the user interface of the target application is not in an interface update state, the first priority of the target thread may be lowered, thereby reducing power consumption of the CPU.

It can be seen that, since the electronic device schedules the target thread from the first processor core to the third processor core whose operating frequency is lower than that of the first processor core when the first information indicates that the user interface of the target application is not in the interface update state. running on the CPU, so that the power consumption of the CPU can be reduced under the condition that the CPU processes thread tasks in an orderly manner.

In the thread scheduling method provided in the embodiment of the present application, the execution subject may be a thread scheduling device. In the embodiment of the present application, the thread scheduling device executed by the thread scheduling device is taken as an example to describe the thread scheduling device provided in the embodiment of the present application.

An embodiment of the present application provides a thread scheduling device. As shown in FIG. 6, the thread scheduling device 400 includes: an acquisition module 401 and a scheduling module 402, wherein: the acquisition module 401 is used for displaying the user interface of the target application Next, acquire the first information; the scheduling module 402 is configured to schedule the target thread from the first processor core to the second processing when the first information acquired by the acquiring module indicates that the user interface of the target application is in an interface update state The target thread is used to display the user interface of the target application; wherein, the operating frequency of the first processor core is lower than the operating frequency of the second processor core.

In the thread scheduling device provided in the embodiment of the present application, the target thread is scheduled to run on the second processor core with a higher operating frequency, so as to prevent the user interface of the target application from being stuck during the update process and improve the display of the electronic device. Fluency in the UI process.

Optionally, in this embodiment of the present application, the above-mentioned first information includes the first operating frequency of the first processor core; the above-mentioned scheduling module 402 is specifically used for when the first operating frequency is greater than or equal to the second operating frequency , the target thread is scheduled from the first processor core to run on the second processor core; wherein, the second operating frequency includes any of the following: preset operating frequency, the work of the first processor core before obtaining the first operating frequency frequency.

Optionally, in this embodiment of the present application, the above-mentioned first information includes the first interface information and the second interface information of the user interface, and the first interface information and the second interface information are interfaces of the user interface of the target application acquired at different times information; the above scheduling module 402 is specifically used to schedule the target thread from the first processor core to run on the second processor core when the first interface information does not match the second interface information.

Optionally, in this embodiment of the present application, the aforementioned target thread includes at least one of the following: a main thread and a rendering thread.

Optionally, in the embodiment of the present application, the acquisition module 401 is further configured to acquire the target thread ID before the target thread is scheduled from the first processor core to run on the second processor core; and according to the target thread ID , to get the target thread; the target thread ID is used to indicate the target thread.

It can be seen that, since the thread scheduling device can obtain the target thread according to the target thread identifier, it can accurately find the target thread used to display the user interface of the target application from multiple threads, therefore, the accuracy of the thread scheduling device in obtaining the target thread can be improved. sex.

Optionally, in the embodiment of the present application, as shown in FIG. 7 , the above-mentioned apparatus further includes: an increase-adjustment module 403, the above-mentioned increase-adjustment module 403 is used to schedule the target thread from the first processor core to the second processing Before running on the processor core, increase the first priority of the target thread; wherein, the first priority includes at least one of the following: the scheduling priority that is scheduled to run on the second processor core, the scheduling priority that is scheduled to the second processor Run priority after kernel.

It can be seen that, since the thread scheduling device can increase the priority of the target thread, the target thread can be preferentially scheduled to run on the second processor core, or run preferentially on the second processor core. Therefore, the task scheduling response corresponding to the target thread can be accelerated and fully supported by the computing power of the second processor core, thus, the execution speed of the task corresponding to the target thread of the thread scheduling device is improved.

The thread scheduling apparatus in the embodiment of the present application may be an electronic device, or may be a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or other devices other than the terminal. Exemplarily, the electronic device may be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR)/virtual reality (virtual reality, VR) device, robot, wearable device, ultra-mobile personal computer (ultra-mobile personalcomputer, UMPC), netbook or personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, network attached storage (Network Attached Storage, NAS) , a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which are not specifically limited in this embodiment of the present application.

The thread scheduling device in the embodiment of the present application may be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in this embodiment of the present application.

The thread scheduling device provided by the embodiment of the present application can implement the various processes implemented by the above method embodiments, and can achieve the same technical effect. To avoid repetition, details are not repeated here.

Optionally, as shown in FIG. 8 , the embodiment of the present application also provides an electronic device 600, including a processor 601 and a memory 602, and the memory 602 stores programs or instructions that can run on the processor 601. The program or When the instructions are executed by the processor 601, the various steps of the thread scheduling method embodiment described above can be achieved, and the same technical effect can be achieved. To avoid repetition, details are not repeated here.

It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

FIG. 8 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 100 includes but is not limited to: a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, and a processor 110, etc. part.

Those skilled in the art can understand that the electronic device 100 can also include a power supply (such as a battery) for supplying power to various components, and the power supply can be logically connected to the processor 110 through the power management system, so that the management of charging, discharging, and function can be realized through the power management system. Consumption management and other functions. The structure of the electronic device shown in FIG. 9 does not constitute a limitation to the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine some components, or arrange different components, and details will not be repeated here. .

Wherein, the above-mentioned processor 110 is configured to obtain the first information when the user interface of the target application is displayed; The processor core is scheduled to run on the second processor core, and the target thread is used to display the user interface of the target application; wherein, the operating frequency of the first processor core is lower than the operating frequency of the second processor core.

In the electronic device provided by the embodiment of the present application, the target thread is scheduled to run on the second processor core with a higher operating frequency, so as to avoid the user interface of the target application from being stuck during the update process, and to improve the user interface of the electronic device. Fluency in the interface process.

Optionally, in the embodiment of the present application, the above-mentioned first information includes the first operating frequency of the first processor core; the above-mentioned processor 110 is specifically used to , the target thread is scheduled from the first processor core to run on the second processor core; wherein, the second operating frequency includes any of the following: preset operating frequency, the work of the first processor core before obtaining the first operating frequency frequency.

Optionally, in this embodiment of the present application, the above-mentioned first information includes the first interface information and the second interface information of the user interface, and the first interface information and the second interface information are interfaces of the user interface of the target application acquired at different times Information; the above processor 110 is specifically configured to schedule the target thread from the first processor core to run on the second processor core when the first interface information does not match the second interface information.

Optionally, in this embodiment of the present application, the aforementioned target thread includes at least one of the following: a main thread and a rendering thread.

Optionally, in the embodiment of the present application, the above-mentioned processor 110 is further configured to acquire the target thread ID before scheduling the target thread from the first processor core to the second processor core to run; and according to the target thread ID , to get the target thread; the target thread ID is used to indicate the target thread.

It can be seen that since the electronic device can obtain the target thread according to the target thread identifier, it can accurately find the target thread for displaying the user interface of the target application from multiple threads, and therefore, the accuracy of obtaining the target thread by the electronic device can be improved.

Optionally, in the embodiment of the present application, the processor 110 is further configured to increase the first priority of the target thread before scheduling the target thread from the first processor core to run on the second processor core; Wherein, the first priority includes at least one of the following: a scheduling priority scheduled to run on the second processor core, and an running priority after being scheduled to the second processor core.

It can be seen that, since the electronic device can increase the priority of the target thread, the target thread can be preferentially scheduled to run on the second processor core, or run preferentially on the second processor core. Therefore, the task scheduling response corresponding to the target thread can be accelerated and fully supported by the computing power of the second processor core, thus increasing the execution speed of the task corresponding to the target thread of the electronic device.

It should be understood that, in the embodiment of the present application, the input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042. Camera) to process the image data of still pictures or videos. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072 . The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts, a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, switch buttons, etc.), trackballs, mice, and joysticks, which will not be repeated here.

The memory 109 can be used to store software programs as well as various data. The memory 109 can mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area can store an operating system, an application program or instructions required by at least one function (such as a sound playing function, image playback function, etc.), etc. Furthermore, memory 109 may include volatile memory or nonvolatile memory, or, memory 109 may include both volatile and nonvolatile memory. Wherein, the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electronically programmable Erase Programmable Read-Only Memory (Electrically EPROM, EEPROM) or Flash. Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synch link DRAM , SLDRAM) and Direct Memory Bus Random Access Memory (Direct Rambus RAM, DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

The processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to the operating system, user interface, and application programs, etc., Modem processors mainly process wireless communication signals, such as baseband processors. It can be understood that the foregoing modem processor may not be integrated into the processor 110 .

The embodiment of the present application also provides a readable storage medium. The readable storage medium stores programs or instructions. When the program or instructions are executed by the processor, the processes of the above-mentioned thread scheduling method embodiments are implemented, and the same To avoid repetition, the technical effects will not be repeated here.

Wherein, the processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk, and the like.

The embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the above thread scheduling method embodiment Each process can achieve the same technical effect, so in order to avoid repetition, it will not be repeated here.

It should be understood that the chips mentioned in the embodiments of the present application may also be called system-on-chip, system-on-chip, system-on-a-chip, or system-on-a-chip.

The embodiment of the present application provides a computer program product, the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the various processes in the above thread scheduling method embodiment, and can achieve the same technical effect , to avoid repetition, it will not be repeated here.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved. Functions are performed, for example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on such an understanding, the technical solution of the present application can be embodied in the form of computer software products, which are stored in a storage medium (such as ROM/RAM, magnetic disk, etc.) , optical disc), including several instructions to enable a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of this application, without departing from the purpose of this application and the scope of protection of the claims, many forms can also be made, all of which belong to the protection of this application.

Claims (14)

1. A method of thread scheduling, the method comprising:

acquiring first information under the condition of displaying a user interface of a target application;

scheduling a target thread from a first processor core to a second processor core for running under the condition that the first information indicates that the user interface of the target application is in an interface updating state, wherein the target thread is used for displaying the user interface of the target application;

wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.

2. The method of claim 1, wherein the first information comprises a first operating frequency of the first processor core;

the scheduling, by the first processor core to run on the second processor core, the target thread if the first information indicates that the user interface of the target application is in an interface update state, includes:

scheduling the target thread from a first processor core to run on the second processor core when the first operating frequency is greater than or equal to a second operating frequency;

wherein the second operating frequency comprises any one of: presetting a working frequency and acquiring the working frequency of the first processor core before the first working frequency.

3. The method of claim 1, wherein the first information includes first interface information and second interface information of the user interface, the first interface information and the second interface information being interface information of a user interface of the target application acquired at different times;

the scheduling, by the first processor core to run on the second processor core, the target thread if the first information indicates that the user interface of the target application is in an interface update state, includes:

and under the condition that the first interface information and the second interface information are not matched, scheduling the target thread to run on a second processor core by the first processor core.

4. The method of claim 1, wherein the target thread comprises at least one of: a main thread and a rendering thread.

5. The method of claim 1, wherein prior to said scheduling the target thread to run on the second processor core by the first processor core, the method further comprises:

acquiring a target thread identifier; the target thread identifier is used for indicating the target thread;

and acquiring the target thread according to the target thread identification.

6. The method of claim 1, wherein prior to said scheduling the target thread to run on a second processor core by a first processor core, the method further comprises;

raising a first priority of the target thread;

wherein the first priority comprises at least one of: scheduling priority of operation scheduled to the second processor core, and operation priority after being scheduled to the second processor core.

7. A thread scheduling apparatus, the apparatus comprising: the device comprises an acquisition module and a scheduling module, wherein:

the acquisition module is used for acquiring first information under the condition of displaying a user interface of a target application;

the scheduling module is used for scheduling a target thread from a first processor core to a second processor core for running when the first information acquired by the acquiring module indicates that the user interface of the target application is in an interface updating state, and the target thread is used for displaying the user interface of the target application;

wherein the operating frequency of the first processor core is less than the operating frequency of the second processor core.

8. The apparatus of claim 7, wherein the first information comprises a first operating frequency of the first processor core;

the scheduling module is specifically configured to schedule, when the first working frequency is greater than or equal to the second working frequency, the target thread to run on the second processor core from the first processor core;

wherein the second operating frequency comprises any one of: presetting a working frequency and acquiring the working frequency of the first processor core before the first working frequency.

9. The apparatus of claim 7, wherein the first information comprises first interface information and second interface information of the user interface, the first interface information and the second interface information being interface information of a user interface of the target application acquired at different times;

the scheduling module is specifically configured to schedule the target thread from the first processor core to the second processor core for running when the first interface information and the second interface information are not matched.

10. The apparatus of claim 7, wherein the target thread comprises at least one of: a main thread and a rendering thread.

11. The apparatus of claim 7, wherein the means for obtaining is further configured to obtain a target thread identification prior to the scheduling the target thread to run on a second processor core by a first processor core; acquiring the target thread according to the target thread identification; the target thread identification is used for indicating the target thread.

12. The apparatus of claim 7, wherein the apparatus further comprises: the heightening module is used for heightening the first priority of the target thread before the target thread is scheduled to run on the second processor core by the first processor core;

wherein the first priority comprises at least one of: scheduling priority of operation scheduled to the second processor core, and operation priority after being scheduled to the second processor core.

13. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the thread scheduling method of any one of claims 1 to 6.

14. A readable storage medium, characterized in that it stores thereon a program or instructions which, when executed by a processor, implement the steps of the thread scheduling method of any one of claims 1 to 6.