CN116526301A - Surface-emitting laser semiconductor array chip and manufacturing method thereof - Google Patents

Abstract

The invention relates to the field of laser semiconductors, in particular to a surface-emitting laser semiconductor array chip and a manufacturing method thereof. The surface-emitting laser semiconductor array chip comprises a substrate assembly, a first reflecting mirror assembly, an active area assembly, a step assembly and a second reflecting mirror assembly, wherein the first reflecting mirror assembly is arranged on the upper surface of the first substrate assembly, the active area assembly is arranged on the upper surface of the first reflecting mirror assembly, the step assembly is arranged on the upper surface of the active area assembly, the second reflecting mirror assembly is arranged on each step of the step assembly, a light emitting unit is arranged on each step of the step assembly, and the light emitting unit is embedded into the second reflecting mirror assembly. The invention designs the graph and wavelength combinations of different array chips, and each batch of array chips has unique ID, and the invention can effectively solve the problem of signal interaction among different radars by adopting the invention as a signal emission light source of the laser radar.

Description

Surface-emitting laser semiconductor array chip and manufacturing method thereof

technical field

The invention relates to the field of laser semiconductors, in particular to a surface emitting laser semiconductor array chip and a manufacturing method thereof.

Background technique

Surface-emitting semiconductor lasers have gradually become a new hot spot in the field of semiconductor lasers due to their many advantages such as vertical light emission, easy integration, low power consumption, and circular light spots. Especially in recent years, due to the development of intelligent perception technologies such as face recognition and laser radar, the vertical cavity surface emitting semiconductor laser VCSEL array chip has become a hotspot in the field of research and industry.

At present, the VCSEL array chip used in the field of face recognition, laser radar and other intelligent perception technologies is mainly based on the gallium arsenide GaAs material system. The central wavelength of the common VCSEL array includes 850 nm, 910 nm, 940 nm, etc. The different light emitting units 110 of the entire VCSEL array chip are prepared based on the same epitaxial structure and have almost the same oscillation cavity length. Therefore, the entire The emission wavelength of the array is generally a single wavelength. At present, the field of laser radar, especially the vehicle laser radar technology, is mainly based on the ToF principle of the time-of-flight method, that is, by continuously emitting light pulses (generally invisible light) to the object under test, and then receiving the light pulses reflected back from the object, through The round-trip time of the light pulse is detected to calculate the distance of the measured object from the camera. A key problem facing the technology in real road conditions is how to distinguish whether the light pulses received by the detector are emitted by itself or by the radar of other vehicles. At present, the laser pulses emitted by the laser radar emitter using the VCSEL array chip only contain energy information, and the laser signals emitted by different laser radars are very difficult to distinguish from each other. The existing array chip has a uniform oscillation cavity length, the laser emitted by the chip has a single central wavelength, the laser signal is not unique, and different laser signals cannot be distinguished from each other.

Contents of the invention

The invention provides a surface-emitting laser semiconductor array chip and a manufacturing method thereof. The surface-emitting laser semiconductor array chip can simultaneously emit multiple lasers with different wavelengths in a single array chip, and the laser light emitted by the array chip The wavelength distribution in the light spot has certain rules, so as to solve at least one technical problem existing in the prior art.

A technical solution of the present invention is as follows: a surface-emitting laser semiconductor array chip, including a substrate assembly, a first mirror assembly, an active area assembly, a step assembly and a second mirror assembly, the first mirror assembly arranged on the upper surface of the first substrate assembly, the active area assembly is arranged on the upper surface of the first mirror assembly, the step assembly is arranged on the upper surface of the active area assembly, and the step assembly A second mirror assembly is arranged on each step, and a light emitting unit is arranged on each step of the step assembly, and the light emitting unit is embedded in the second mirror assembly.

Further, the substrate assembly includes a first electrode layer and a substrate, and the substrate is arranged on the upper surface of the second electrode layer.

Further, the active region assembly includes an active layer, a first confinement layer and a second confinement layer, and the active layer is disposed between the first confinement layer and the second confinement layer.

Further, the step component includes an oxide layer and a step layer, the step layer is arranged on the surface of the oxide layer, and the step layer includes a plurality of steps with different heights.

Further, the light-emitting unit includes an annular groove, a second electrode layer and an insulating layer, the annular groove is embedded in the second reflector assembly, an oxide layer and a step layer, the annular groove and the surrounding oxide layer form an oxidation aperture, so The oxide layer is disposed on the surface of the annular groove and the upper surface of the second mirror assembly, the second electrode layer is disposed on the surface of the oxide layer, and the second electrode layer and the A light hole is opened on the oxide layer.

Further, each step of the step layer is rectangular, and the height of each step changes step by step, and each step is arranged parallel to the edge of the surface-emitting laser semiconductor array chip or at an angle to the edge of the surface-emitting laser semiconductor array chip. 45° included angle setting.

Further, when each step is set at an angle of 45° to the edge of the surface-emitting laser semiconductor array chip, the length of the step at the middle position is greater than the length of the steps on both sides, and the length of the outermost step is the shortest.

Further, the steps of the step layer are annular and arranged concentrically, and the height of the steps decreases sequentially from the center to the edge or decreases and increases sequentially from the center to the edge.

Further, the step width of the ring is 20-500 microns, and the light-emitting aperture of the light-emitting unit is 5-200 microns.

Another technical solution of the present invention is as follows: a method for preparing any one of the above-mentioned surface-emitting laser semiconductor array chips, comprising:

Selecting the substrate component, and epitaxially growing the first reflector component, the active region component and the stepped component substrate on the substrate component in sequence through epitaxial equipment;

Through photolithography and dry etching process, etch multi-level steps with different heights on the substrate of the stepped component;

The second mirror assembly is epitaxially grown on each step, and a light-emitting unit is etched on the second mirror assembly on each step.

Beneficial effects of the present invention: the present invention provides an array chip with patterned wavelength information in the light spot. By designing different array chip graphics and wavelength combinations, each batch of array chips has its own Unique ID, using the VCSEL array chip provided by the present invention as the signal emitting light source of the laser radar, can effectively solve the problem of signal interaction between different radars.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a surface-emitting laser semiconductor array chip according to the present invention.

Fig. 2 is a schematic diagram of the epitaxial structure of a surface-emitting laser semiconductor array chip according to the present invention.

Fig. 3 is a top view of Embodiment 1 of a surface-emitting laser semiconductor array chip of the present invention.

Fig. 4 is a top view of Embodiment 2 of a surface-emitting laser semiconductor array chip of the present invention.

Fig. 5 is a top view of Embodiment 3 of a surface-emitting laser semiconductor array chip of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The described embodiments are only the embodiments of the present invention Some examples, but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

In an embodiment of the present invention, FIG. 1 and FIG. 2 are structural schematic diagrams provided according to the specific structure of a surface-emitting laser semiconductor array chip of the present invention. As shown in FIG. 1 and FIG. 2, the present invention specifically includes: a substrate assembly, a first mirror assembly 102, an active area assembly, a step assembly, and a second mirror assembly 108, and the first mirror assembly 102 is arranged on The upper surface of the first substrate assembly, the active area assembly is arranged on the upper surface of the first mirror assembly 102, the step assembly is arranged on the upper surface of the active area assembly, each of the step assemblies A second reflector assembly 108 is arranged on each step, and a plurality of light emitting units 110 are arranged on each step of the step assembly, and the light emitting units 110 are embedded in the second reflector assembly 108 . Specifically, the bottom of the light emitting unit 110 is slightly embedded in the top of the step component.

As shown in FIG. 1 , the substrate assembly includes a first electrode layer 201 and a substrate 101 , and the substrate 101 is disposed on the upper surface of the first electrode layer 201 . Wherein, the second electrode layer 203101 is an N-type electrode with a thickness between 200 nanometers and 500 nanometers, and the material is an alloy material formed of titanium, platinum, gold, nickel, germanium and the like. The substrate 101102 can be made of N-type GaAs material.

As shown in FIG. 1, the first reflector assembly 102 can be an N-type distributed Bragg reflector (DBR) reflector, specifically a periodically grown InAlGaAs/InAlGaAs (InAlGaAs/InAlGaAs) material, each The In composition of the layer material is 0.5~0.6, and the Al composition is 0.05~0.95. The thickness of each layer of material is the ratio of a quarter of the wavelength of the emitted light to the refractive index of the material. Specifically, it is a quarter of the wavelength of the emitted light divided by the refractive index of the material. The period logarithm ranges from 20 to 40 pairs (including the endpoint value), and the total thickness ranges from 2 to 5 microns (including the endpoint value). The dopant is Si, and the doping concentration is 1E16~8E18/cm ³ .

As shown in Figure 1, the active region assembly includes an active layer 104, a first confinement layer 103 and a second confinement layer 105, and the active layer 104 is arranged between the first confinement layer 103 and the second confinement layer 105 between. Specifically, the active layer 104 is disposed on the upper surface of the first confinement layer 103 , and the second confinement layer 105 is disposed on the upper surface of the active layer 104 . The first confinement layer 103 can be an N-type confinement layer, the N-type confinement layer is aluminum gallium arsenide (AlGaAs) material, the Al composition is 0.05-0.95, the thickness is 0.1 micron-10 microns, the dopant is silicon Si, doped The concentration is 1E16-8E18/cm ³ . The active layer 104 is inactively doped and has a barrier/quantum well/barrier structure, the material is AlGaAs/InAlGaAs/AlGaAs, the In composition is 0~0.2, the Al composition is 0~0.5, and the thickness of the barrier is 1 nm~200 Nanometer, the thickness of the quantum well is 1 nanometer to 20 nanometers, and the light emission band is 700 nanometers to 1100 nanometers. The second confinement layer 105 can be a P-type confinement layer, specifically AlGaAs material, with an Al composition of 0.05-0.95, a thickness of 0.05-0.5 microns, a dopant of C, and a doping concentration of 1E16-8E18/cm ³ .

As shown in FIG. 2 , the step assembly includes an oxide layer 106 and a step layer 107 , the step layer 107 is disposed on the surface of the oxide layer 106 , and the step layer 107 includes multiple steps with different heights. Wherein, the material of the oxide layer 106 is AlGaAs, the Al composition is 0.95-0.98, the thickness is 0.01 micron-0.05 micron, the dopant is C, and the doping concentration is 1E16-8E18/cm ³ . The step layer 107 is P-type, specifically AlGaAs material can be used, the Al composition is 0.05-0.95, the thickness is 0.05-10 microns, the dopant is C, and the doping concentration is 1E16-8E18/cm ³ .

The second reflector assembly 108 can use a P-type distributed Bragg reflector (DBR) reflector, specifically a periodically grown AlGaAs/AlGaAs material, the Al composition of each layer of material is 0.05-0.95, and the thickness of each layer of material is 1/4 Dividing the wavelength of emitted light by the refractive index of the material, the period logarithm ranges from 20 pairs to 40 pairs, inclusive, and the total thickness ranges from 2 microns to 5 microns, inclusive. The dopant is C, and the doping concentration is 1E16-8E18/cm ³ . The second reflector assembly 108 is covered with a cover layer 109, the cover layer 109 is specifically a P-type cover layer 109 made of gallium arsenide (GaAs) material with a thickness of 0.1 μm to 3 μm, the dopant is C, and the doping concentration is It is 1E18-1E20/cm ³ .

The light emitting unit 110 specifically includes an annular groove 206, a second electrode layer 203, an insulating layer 202, and an inner second reflector assembly and a step assembly, and the groove between the light emitting unit 110 and the outer second reflector assembly is an annular groove 206 , wherein the annular groove 206 is formed by an etching process, the annular groove 206 is embedded in the second mirror assembly 108, the oxide layer 106 and the step layer 107, the annular groove 206 and the surrounding oxide layer 106 form an oxide aperture 205, and the light emitting unit 110 The inner second mirror assembly 108 and the stepped assembly are located above the oxidation aperture 205 and in the annular area formed by the annular groove 206, and the oxide layer 106 is arranged on the surface of the annular groove 206 and the surface of the second mirror assembly 108 On the upper surface, the second electrode layer 203 is disposed on the surface of the oxide layer 106 , and a light hole 204 is opened on the second electrode layer 203 and the oxide layer 106 on the upper surface of the second mirror assembly 108 . Wherein, the second electrode layer 203 adopts a P-type electrode with a thickness between 200 nanometers and 500 nanometers, and the material is an alloy material formed of titanium, platinum, gold, nickel, germanium and the like. The insulating layer 202 is made of SiO ₂ or Si ₃ N ₄ with a thickness of 50 nm to 1000 nm.

In the present invention, stepped patterned mesas are formed by etching P-type stepped layers 107 of different heights, and each step includes a different number of light-emitting units 110 to form different patterned designs, which can be used for each batch of surface Laser-emitting semiconductor array chips are given different ID information.

In Embodiment 1 of the present invention, as shown in FIG. 3 , each step of the step layer 107 is rectangular, the height of each step changes step by step, and each step is arranged parallel to the edge of the surface-emitting laser semiconductor array chip. As shown in Figure 3, it specifically includes 4 steps of different heights, all of which are arranged horizontally, and the height of the steps can be reduced or increased step by step from top to bottom. The height difference between different steps can be designed according to specific needs, and the height difference ranges from 0.05 micron to 1 micron. At the same time, different numbers of light emitting units 110 are arranged on steps of each height. In this embodiment, five light emitting units 110 are arranged on each step, and the wavelengths of laser light emitted by the light emitting units 110 on different steps are different.

In Embodiment 2 of the present invention, as shown in Figure 4, each step of the steps is rectangular, the height of each step changes step by step, and each step forms an angle of 45° with the edge of the surface-emitting laser semiconductor array chip set up. Among them, the surface-emitting laser semiconductor array chip has a length ranging from 300 microns to 4000 microns, and a width ranging from 300 microns to 4000 microns. The specific number of steps is 7, the length of the steps in the middle is greater than the length of the steps on both sides, and the length of the outermost steps is the shortest. The height of the seven steps can be increased or decreased step by step from the lower left corner to the upper right corner of the surface-emitting laser semiconductor array chip. The width of each step ranges from 40 microns to 500 microns, and the inclination angle of the steps is 45°. The steps are rectangular, and the rectangular long wave extends to the edge of the surface-emitting laser semiconductor array chip.

The steps from the lower left corner to the upper right corner are distinguished by step 1, step 2, step 3, step 4, step 5, step 6, and step 7. Each of the steps 1 and 7 contains one light-emitting unit 110, and the diameter of the light-emitting unit 110 ranges from 5 microns to 300 microns; on the steps 2 and 6, each contains three light-emitting units 110, the light-emitting unit The diameter of the 110 mesa ranges from 5 microns to 300 microns; each of the steps 3 and 5 contains 6 light-emitting units 110, and the mesa diameter of the light-emitting units 110 ranges from 5 microns to 300 microns; on the step 4, 8 light-emitting units are included. The light emitting unit 110, the diameter of the mesa of the light emitting unit 110 ranges from 5 microns to 300 microns.

In Embodiment 3 of the present invention, as shown in FIG. 5 , the steps of the stepped layer 107 are annular and arranged concentrically, and the height of the steps decreases from the center to the edge or decreases and increases from the center to the edge.

Among them, the surface-emitting laser semiconductor array chip has a length ranging from 300 microns to 4000 microns, and a width ranging from 300 microns to 4000 microns.

Specifically, the surface-emitting laser semiconductor array chip includes 4 different steps arranged in a ring, and the circular step in the center has the highest height, which is recorded as step 1. The diameter of step 1 ranges from 50 microns to 500 microns, and step 1 contains 1 The large-sized light emitting unit 110 has a mesa diameter of 30 microns to 300 microns. The height of the annular step adjacent to step 1 is lower than that of step 1, which is recorded as step 2. The annular width of step 2 ranges from 20 microns to 500 microns. Step 2 contains four light-emitting units 110 arranged in a ring. Micron ~ 200 microns. The height of the ring-shaped step adjacent to step 2 is lower than that of step 2, which is recorded as step 3. The ring width of step 3 ranges from 20 microns to 500 microns. Step 3 contains 8 light-emitting units 110 arranged in a ring. Micron ~ 200 microns. The height of the ring-shaped step adjacent to step 3 is lower than that of step 3, which is recorded as step 4. The annular width of step 4 ranges from 20 microns to 500 microns. Step 4 contains 8 light-emitting units 110 arranged in a ring. Micron ~ 200 microns.

In another technical solution of the present invention, a method for preparing any of the above-mentioned surface-emitting laser semiconductor array chips is provided, including:

The substrate component is selected, and the first reflector component 102, the active region component and the stepped component substrate are epitaxially grown on the substrate component in sequence by means of epitaxial equipment.

Specifically, take an N-type GaAs substrate 101 . An N-type DBR reflector, an N-type confinement layer, an active region, a P-type confinement layer, an oxide layer 106 and a P-type step layer 107 are grown sequentially on the N-type GaAs substrate 101 . The growth equipment is commercial MOCVD or MBE.

Through photolithography and dry etching processes, multiple steps with different heights are etched on the substrate of the stepped component.

Specifically, using traditional photolithography and dry etching processes, periodic stepped mesas are etched on the surface of the substrate 101 on which the P-type stepped layer 107 has been grown, and each period is a surface-emitting laser semiconductor array chip. , the period length ranges from 300 microns to 5000 microns, and the period width ranges from 300 microns to 5000 microns. In the surface-emitting laser semiconductor array chip in Example 1, each period contains four steps of different heights, and the step length and period length Similarly, the width of each step ranges from 50 microns to 1500 microns.

The second reflector assembly 108 is epitaxially grown on each step, and the light emitting unit 110 is etched on the second reflector assembly 108 on each step. Specifically, a secondary epitaxial process is performed on the etched patterned mesa substrate 101 to sequentially grow a P-type DBR mirror and a P-type capping layer 109 to obtain an epitaxial substrate 101 with a complete structure. On the four steps of the epitaxial substrate 101, an annular groove is etched by photolithography and dry etching process, the width of the groove is 5 μm-50 μm, and the groove etching depth is required to etch the peroxide layer 106, by The circular mesa surrounded by the trench directly ranges from 5 microns to 500 microns. The oxidation pore diameter 205 is prepared by the traditional wet oxidation process, and the diameter of the oxidation pore ranges from 3 microns to 300 microns. A silicon oxide or silicon nitride insulating layer 202 is grown on the surface of the epitaxial substrate 101 . Electrode injection windows are etched on the surface of the insulating layer 202 through photolithography and etching processes. A P-type metal electrode is grown, and a light outlet is prepared by a lift-off process. A thinning and polishing process is performed on the back surface of the substrate 101 . N-type metal electrodes are grown. The ohmic contact is formed by an alloy process. Cleavage to form a single surface-emitting laser semiconductor array chip.

Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.

Claims (10)

1. A surface-emitting laser semiconductor array chip, characterized in that it includes a substrate component, a first mirror component (102), an active area component, a ladder component, and a second mirror component (108), the first A mirror assembly (102) is disposed on the upper surface of the first substrate assembly, the active area assembly is disposed on the upper surface of the first mirror assembly (102), and the step assembly is disposed on the active area On the upper surface of the assembly, a second mirror assembly (108) is provided on each step of the step assembly, and a light emitting unit (110) is provided on each step of the step assembly, and the light emitting unit (110) is embedded in the first Two mirror assemblies (108). 2. The surface-emitting laser semiconductor array chip according to claim 1, characterized in that, the substrate assembly includes a first electrode layer (201) and a substrate (101), and the substrate (101) is set on the upper surface of the first electrode layer (201). 3. The surface emitting laser semiconductor array chip according to claim 1, characterized in that, the active region component comprises an active layer (104), a first confinement layer (103) and a second confinement layer (105) , the active layer (104) is disposed between the first confinement layer (103) and the second confinement layer (105). 4. The surface-emitting laser semiconductor array chip according to claim 1, characterized in that, the stepped component includes an oxide layer (106) and a step layer (107), and the step layer (107) is arranged on the oxide layer ( 106), the step layer (107) includes multiple steps with different heights. 5. The surface emitting laser semiconductor array chip according to claim 4, characterized in that, the light emitting unit (110) comprises an annular groove (206), a second electrode layer (203) and an insulating layer (202), the The annular groove (206) is embedded in the second mirror assembly (108), the oxide layer (106) and the step layer (107), and the annular groove (206) and the surrounding oxide layer (106) form an oxide aperture (205), The oxide layer (106) is arranged on the surface of the annular groove (206) and the upper surface of the second reflector assembly (108), and the second electrode layer (203) is arranged on the surface of the oxide layer (106), located on A light hole (204) is opened on the second electrode layer (203) and the oxide layer (106) on the upper surface of the second reflection mirror assembly (108). 6. The surface-emitting laser semiconductor array chip according to claim 4, characterized in that, each step of the step layer (107) is in the shape of a rectangle, and the height of each step changes step by step. The edges of the laser semiconductor array chip are arranged in parallel or at an angle of 45° to the edge of the surface emitting laser semiconductor array chip. 7. The surface-emitting laser semiconductor array chip as claimed in claim 6, wherein when each step is set at an angle of 45° with the edge of the surface-emitting laser semiconductor array chip, the length of the step at the middle position It is longer than the length of the steps on both sides, and the length of the outermost step is the shortest. 8. The surface-emitting laser semiconductor array chip according to claim 4, characterized in that, the steps of the step layer (107) are arranged in a ring shape and concentrically, and the height of the steps decreases from the center to the edge or decreases from the center to the edge. Decrease and increase to the edge. 9. The surface-emitting laser semiconductor array chip according to claim 8, characterized in that, the width of the ring-shaped step is 20-500 microns, and the light-emitting aperture of the light-emitting unit (110) is 5-200 microns. 10. A method for preparing the surface-emitting laser semiconductor array chip described in any one of claims 1-9, characterized in that it comprises: Selecting the substrate component, and epitaxially growing the first reflector component (102), the active region component and the stepped component substrate on the substrate component in sequence through epitaxial equipment; Through photolithography and dry etching process, etch multi-level steps with different heights on the substrate of the stepped component; The second reflective mirror assembly (108) is epitaxially grown on each step, and a light-emitting unit (110) is etched on the second reflective mirror assembly (108) on each step.