CN116467980B - Method for solving parameters of standard unit circuit, electronic equipment and storage medium - Google Patents

Abstract

The application relates to a method for solving parameters of a standard unit circuit, electronic equipment and a storage medium. The method comprises determining the equivalent circuit of a resistor-capacitor circuit connected to the output terminal of the standard cell; solving the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell; determining a preset that matches the equivalent circuit Equivalent circuit: Query the correction parameters corresponding to the preset equivalent circuit in the correction parameter library, and the correction parameters are based on the effective capacitance of the preset equivalent circuit determined based on static timing analysis and the effective capacitance of the preset equivalent circuit determined based on dynamic timing analysis. The effective capacitance is obtained; the output capacitance to be corrected is corrected according to the correction parameter, and the output capacitance of the standard unit is obtained. The solution provided by this application is based on the pre-determined correction parameters of static and dynamic timing analysis, and corrects the output capacitance of the standard cell to be corrected determined based on the static timing analysis, which can improve the solution speed and accuracy of the output capacitance of the standard cell.

Description

Method for solving parameters of standard unit circuit, electronic equipment and storage medium

technical field

The application belongs to the field of circuit technology, and in particular relates to a method for solving parameters of a standard unit circuit, electronic equipment and a storage medium.

Background technique

With the improvement of chip integration, various standard units such as inverters and AND gates are more and more widely used in chips.

For a standard cell, the output capacitance is a key indicator for determining the delay of the standard cell, and the speed and accuracy of solving the output capacitance of the standard cell directly affect the speed and accuracy of solving the delay of the standard cell. At present, there are two ways to solve the output capacitance of standard cells: 1) Static timing analysis; 2) Dynamic timing analysis. Among them, the accurate standard cell output capacitance can be obtained based on dynamic timing analysis, but the process of solving the standard cell output capacitance takes a long time; the process of solving the standard cell output capacitance based on static timing analysis is relatively short, but the obtained standard cell The accuracy of the cell output capacitance is not high.

Therefore, how to improve the parameter solution speed and solution accuracy of the standard cell circuit has become an urgent problem to be solved.

Contents of the invention

In view of the above technical problems, the present application provides a parameter solving method of a standard unit circuit, an electronic device and a computer storage medium, which can improve the parameter solving speed and accuracy of the standard unit circuit.

This application provides a solution method for a standard unit circuit, including:

determining an equivalent circuit of a resistor-capacitor circuit connected to an output terminal of the standard cell based on a preset circuit model;

Solving the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell;

determining a preset equivalent circuit matching the equivalent circuit;

Query the correction parameters corresponding to the preset equivalent circuit in the correction parameter library, wherein the correction parameter library includes the correspondence between multiple preset equivalent circuits and multiple correction parameters, and the correction parameters are in the When the preset equivalent circuit is set as the output of the standard cell, according to the first effective capacitance of the preset equivalent circuit determined based on static timing analysis and the first effective capacitance of the preset equivalent circuit determined based on dynamic timing analysis obtained by processing the second effective capacitance;

The output capacitance to be corrected is corrected according to the correction parameter, so as to obtain the output capacitance of the standard cell.

In one embodiment, the effective capacitor causes the standard cell to have the same delay as the equivalent circuit causes the standard cell to delay.

In an embodiment, the preset equivalent circuit and the equivalent circuit adopt the same preset circuit model.

In one embodiment, the calculating the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell includes:

According to the first capacitance value of the equivalent circuit and the input transition time of the standard cell, query the nonlinear delay model library to determine the output transition time of the standard cell, wherein the first capacitance value represents the equal The overall capacitance of the effective circuit; based on the static timing analysis, according to the output transition time of the standard cell, the resistance value of the equivalent circuit and the second capacitance value, the effective capacitance of the equivalent circuit is solved to obtain the obtained The to-be-corrected output capacitance of the standard unit, wherein the second capacitance value is the capacitance value of each capacitance in the equivalent circuit.

In one embodiment, based on the static timing analysis, the effective capacitance of the equivalent circuit is calculated according to the output conversion time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value, so as to The step of obtaining the output capacitance to be corrected of the standard unit includes:

According to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value, determine the effective capacitance of the equivalent circuit; judge whether the effective capacitance converges; if not converge, then the The effective capacitance is used as the first capacitance value of the equivalent circuit, and the input conversion time according to the first capacitance value of the equivalent circuit and the standard unit is returned, and the nonlinear delay model library is queried to determine the standard unit The step of the output conversion time; if it converges, the effective capacitance is used as the output capacitance to be corrected of the standard unit.

In one embodiment, the effective capacitance of the equivalent circuit is calculated according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value, including:

converting the time-domain expression of the driving voltage of the standard unit into a frequency-domain expression; determining the standard unit according to the frequency-domain expression of the driving voltage and the resistance value and the second capacitance value of the equivalent circuit The frequency domain expression of the driving current, and the frequency domain expression of the driving current is converted into a time domain expression, and the time domain expression of the driving current is used to characterize the output transition time and operating voltage of the standard unit , driving time, the resistance value of the equivalent circuit, the relationship between the second capacitance value and the driving current; obtaining the target driving voltage selected for solving the delay of the standard cell, and the corresponding target driving voltage Target driving time; according to the target driving time and the target driving voltage, the time domain expression of the driving current is processed, so that the driving current of the standard cell can charge the circuit with the charging power of the circuit under the target driving time The effective capacitance of the equivalent circuit is equal to the charging power of the circuit under the target driving voltage; the expression obtained from the processing is transformed so that the output conversion time of the standard unit and the resistance value of the equivalent circuit and the second capacitance value to obtain the effective capacitance of the equivalent circuit.

In one embodiment, the step of establishing the correction parameter library includes:

Constructing a preset number of preset equivalent circuits; performing the static timing analysis on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit; performing a static sequence analysis on each preset equivalent circuit The dynamic timing analysis is to determine the second effective capacitance of each preset equivalent circuit; determine the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit; determine according to the deviation correcting parameters, and associating the correcting parameters with corresponding preset equivalent circuits, so as to establish the correcting parameter library.

In one embodiment, the step of performing the static timing analysis on each preset equivalent circuit and determining the first effective capacitance of each preset equivalent circuit includes:

Based on the static timing analysis, according to the resistance value and capacitance value in each preset equivalent circuit and the output conversion time of the standard unit corresponding to each preset equivalent circuit, determine the preset values The first effective capacitance of the effective circuit.

In one embodiment, determining a preset equivalent circuit matching the equivalent circuit includes: comparing the resistance value and capacitance value of the equivalent circuit with the resistance value and capacitance value of the preset equivalent circuit Comparing: determining a preset equivalent circuit matching the equivalent circuit according to the comparison result.

In one embodiment, after the output capacitance to be corrected is corrected according to the correction parameter to obtain the output capacitance of the standard cell, the method further includes: according to the input conversion time of the standard cell and the output capacitance of the standard cell, and query the nonlinear delay model library to obtain the delay of the standard cell.

The present application also provides an electronic device, the electronic device includes a memory, a processor, and a computer program stored in the memory and operable on the processor, when the processor executes the computer program, the The steps of the parameter solving method of the above-mentioned standard cell circuit.

The present application also provides a computer storage medium, the computer storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned method for solving parameters of the standard unit circuit are realized.

The application provides a method for solving parameters of a standard unit circuit, electronic equipment and computer storage media, based on static timing analysis to solve the effective capacitance of the equivalent circuit, can quickly obtain the output capacitance of the standard unit to be corrected, and improve the output capacitance of the standard unit. Solution speed, in addition, based on the static timing analysis and dynamic timing analysis to the pre-determined correction parameters of the preset equivalent circuit solution results, the output capacitor to be corrected can be corrected, the accurate output capacitance of the standard cell can be obtained, and the output capacitance of the standard cell can be improved. In addition, in the process of solving the standard cell output capacitance, it is not necessary to perform dynamic timing analysis on the equivalent circuit, which can further improve the solution speed of the standard cell output capacitance. In this way, the solution speed and solution accuracy of the standard cell output capacitance can be guaranteed at the same time.

Description of drawings

FIG. 1 is a schematic flowchart of a method for solving parameters of a standard unit circuit provided in Embodiment 1 of the present application.

FIG. 2 is a schematic structural diagram of an equivalent circuit provided in Embodiment 1 of the present application.

FIG. 3 is a schematic diagram of solving an effective capacitance of an equivalent circuit based on static timing analysis provided by Embodiment 1 of the present application.

FIG. 4 is a schematic diagram of the established correction parameter library provided by Embodiment 1 of the present application.

FIG. 5 is a schematic diagram of solving an effective capacitance of an equivalent circuit based on dynamic timing analysis provided by Embodiment 1 of the present application.

FIG. 6 is a schematic structural diagram of an electronic device provided in Embodiment 2 of the present application.

Detailed ways

The technical solution of the present application will be further elaborated below in combination with the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application. As used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

FIG. 1 is a schematic flowchart of a method for solving parameters of a standard unit circuit provided in Embodiment 1 of the present application. As shown in Figure 1, the parameter solution method of the standard unit circuit of the present application may include the following steps:

Step S10: Based on the preset circuit model, determine the equivalent circuit of the resistance-capacitance circuit connected to the output terminal of the standard cell;

Step S20: Solve the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell;

Step S30: determining a preset equivalent circuit matching the equivalent circuit;

Step S40: Query the correction parameters corresponding to the preset equivalent circuits in the correction parameter library, wherein the correction parameter library includes the correspondence between multiple preset equivalent circuits and multiple correction parameters, and the correction parameters are the preset etc. When the effective circuit is set as the output of the standard unit, it is obtained by processing the first effective capacitance of the preset equivalent circuit determined based on static timing analysis and the second effective capacitance of the preset equivalent circuit determined based on dynamic timing analysis;

Step S50 : Correct the output capacitance to be corrected according to the correction parameters, so as to obtain the output capacitance of the standard unit.

The standard cell solution method provided in Embodiment 1 of the present application is based on static timing analysis to solve the effective capacitance of the equivalent circuit, which can quickly obtain the output capacitance of the standard cell to be corrected, and improve the solution speed of the output capacitance of the standard cell. In addition, based on static The pre-established correction parameters of the results of timing analysis and dynamic timing analysis can be corrected to correct the output capacitance of the standard cell, which can obtain the accurate output capacitance of the standard cell and improve the solution accuracy of the output capacitance of the standard cell. Moreover, in the process of solving the output capacitance of the standard cell, There is no need to perform dynamic timing analysis on the equivalent circuit, which can further improve the solution speed of the output capacitance of the standard cell.

Optionally, the standard unit includes an inverter, an AND gate, etc., and each standard unit corresponds to a plurality of unit circuits with different sizes and different driving capabilities. The standard unit circuit includes a standard unit and a resistance-capacitance circuit connected to the output terminal of the standard unit (RC circuit). The preset circuit model is a π model (Pi-model), which includes two parallel capacitors and a resistor connected in series with the two parallel capacitors. Based on the π model, the resistance-capacitance circuit connected to the output end of the standard unit is converted to obtain the equivalent circuit shown in Figure 2, that is, the resistance-capacitance circuit connected to the output end of the standard unit is converted into a π model circuit, The first capacitor _C1 is connected in parallel with the second capacitor _C2 , and the resistor R is connected in series between the first capacitor _C1 and the second capacitor _C2 .

In one embodiment, the effective capacitance of the equivalent circuit is solved based on static timing analysis in step S20 to obtain the output capacitance to be corrected of the standard cell, including:

According to the first capacitance value of the equivalent circuit and the input transition time (Input TransitionTime) of the standard cell, query the nonlinear delay model library to determine the output transition time (Output TransitionTime) of the standard cell, where the first capacitance value represents the equivalent circuit the overall capacitance;

Based on the static timing analysis, according to the output conversion time of the standard cell, the resistance value of the equivalent circuit and the second capacitance value, the effective capacitance of the equivalent circuit is solved to obtain the output capacitance to be corrected of the standard cell, wherein the second capacitance value is The capacitance value of each capacitor in the equivalent circuit.

Wherein, the effective capacitance of the equivalent circuit is the output correction capacitance of the standard unit.

In one embodiment, based on static timing analysis, according to the output conversion time of the standard cell, the resistance value of the equivalent circuit and the second capacitance value, the effective capacitance of the equivalent circuit is solved to obtain the output capacitance of the standard cell to be corrected, include:

determining the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value;

Determine whether the effective capacitance is convergent;

If it does not converge, use the effective capacitance as the first capacitance value of the equivalent circuit, and return the output conversion time of the standard unit by querying the nonlinear delay model library based on the first capacitance value of the equivalent circuit and the input conversion time of the standard unit A step of;

If it converges, the effective capacitance is taken as the output capacitance to be corrected of the standard unit.

Continuing to refer to Figure 2, select the total capacitance C _total =C ₁ +C ₂ of the equivalent circuit as the initial first capacitance value, query the nonlinear delay model library according to the total capacitance C _total and the input conversion time _Tri of the standard unit, and determine The first output transition time Tr ₁ of the standard cell, and then determine the effective capacitance of the equivalent circuit according to the first output transition time Tr ₁ of the standard cell, the resistance R of the equivalent circuit, the first capacitance C ₁ and the second capacitance C ₂ A C _{eff_s1} . Judging whether the effective capacitance is converged, specifically, the condition for the convergence of the effective capacitance includes that the deviation between the effective capacitance values obtained by two adjacent calculations is within a preset range, and the effective capacitance solved for the first time is the initial first capacitance value , the effective capacitance to be solved for the second time is the effective capacitance C _{eff_s1} , thus, judging whether the deviation between the initial first capacitance value and the effective capacitance C _{eff_s1} is within a preset range can determine whether the effective capacitance is converged.

If the effective capacitance converges, the effective capacitance C _{eff_s1} is used as the output capacitance to be corrected of the standard cell, and if the effective capacitance does not converge, then the effective capacitance C _{eff_s1} is used as the updated first capacitance value, and the input conversion time of the standard cell Tr _i together, query the nonlinear delay model library again to determine the second output transition time Tr ₂ of the standard unit, and then according to the second output transition time Tr ₂ of the standard unit, the resistance R of the equivalent circuit, the first capacitance C ₁ and The second capacitor C ₂ determines the effective capacitor C _{eff_s2} of the equivalent circuit. Judging whether the effective capacitance is convergent, at this time, it is calculated whether the deviation between the effective capacitance 2 C _{eff_s2} and the effective capacitance 1 C _{eff_s1} is within the preset range, and if so, the effective capacitance is convergent, and the effective capacitance 2 C _{eff_s2} is used as the waiting time of the standard unit Correct the output capacitance, if not, the effective capacitance has not converged, and the effective capacitance C _{eff_s2} is used as the first capacitance value of the equivalent circuit again, and the above-mentioned process of searching the model library and solving the effective capacitance is continued until the effective capacitance of the equivalent circuit is Converge, and use the effective capacitance of the last solution as the output capacitance to be corrected of the standard unit.

In one embodiment, according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value, the effective capacitance of the equivalent circuit is solved, including:

Convert the time-domain expression of the driving voltage of the standard cell into a frequency-domain expression;

According to the frequency domain expression of the driving voltage and the resistance value and the second capacitance value of the equivalent circuit, the frequency domain expression of the driving current of the standard unit is determined, and the frequency domain expression of the driving current is converted into a time domain expression, and the driving The time-domain expression of the current is used to characterize the relationship between the output conversion time of the standard cell, the operating voltage, the driving time, the resistance value of the equivalent circuit, the second capacitance value, and the driving current;

Obtain the target driving voltage selected by the delay of solving the standard unit, and the target driving time corresponding to the target driving voltage;

According to the target driving time and the target driving voltage, the time-domain expression of the driving current is processed, so that the driving current of the standard cell can charge the circuit at the target driving time and the effective capacitance of the equivalent circuit can charge the circuit at the target driving voltage. The charging power is equal;

Transform the obtained expression to obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value.

Among them, the delay produced by the standard cell caused by the effective capacitance is the same as the delay produced by the standard cell caused by the equivalent circuit. When the charging power of the circuit is equal, the condition that the delay produced by the standard cell caused by the effective capacitance is the same as the delay produced by the standard cell by the equivalent circuit is satisfied. It should be understood that the same power or the same delay may be completely the same, or may be considered the same when they are within a preset deviation.

As shown in (a) of Figure 3, when the driving voltage reaches , the driving time corresponds to /> . According to the relationship between the driving voltage and the driving time, the time-domain expression of the driving voltage of the standard cell is obtained:

in, Indicates the driving time of the standard cell to the equivalent circuit, /> Indicates the driving voltage of the standard cell that changes with the driving time, which is the driving voltage source after the standard cell is equivalent, /> Indicates the operating voltage of the standard unit, /> express with /> The drive time of the corresponding standard unit, that is, the output conversion time.

Combining Figure 2 and Figure 3 (b), the standard unit in Figure 2 is equivalent to a driving voltage source, and the circuit shown in Figure 3 (b) is obtained, and its circuit parameters include: the driving voltage source acts on the The driving voltage on the effect circuit varies with the output transition time And the driving current I(t), the current I ₁ (t) passing through the first capacitor in the equivalent circuit that changes with the driving time, the current I ₂ that passes through the resistance and the second capacitor in the equivalent circuit that changes with the driving time (t), wherein the value of the first capacitor is C ₁ , the value of the first capacitor is C ₂ , and the value of the resistor is R.

According to the conversion relationship between the time domain and the frequency domain, the circuit parameters shown in (b) in Figure 3 are converted from the time domain to the frequency domain, and the circuit parameters shown in (c) in Figure 3 are obtained, including: driving voltage source The driving voltage acting on the equivalent circuit that varies with the driving frequency And the driving current I(s), the current I ₁ (s) passing through the first capacitor in the equivalent circuit that changes with the driving frequency, the current I ₂ that passes through the resistance and the second capacitor in the equivalent circuit that changes with the driving frequency (s), wherein the value of the first capacitor is 1/C ₁ s, the value of the second capacitor is 1/C ₂ s, and the value of the resistor is R.

Correspondingly, the time-domain expression of the driving voltage of the standard cell is converted to obtain the frequency-domain expression of the driving voltage of the standard cell:

in, Indicates the driving frequency of the standard cell to the equivalent circuit, /> Indicates the driving voltage of the standard cell that changes with the driving frequency.

According to the circuit shown in (c) in Figure 3 and its circuit parameters, determine the frequency domain expressions of the current passing through the first capacitor, the current passing through the resistor and the second capacitor, and the frequency domain expressions of the driving current—respectively :

Substituting the frequency domain expression of the driving voltage of the standard unit into the frequency domain expression 1 of the driving current, the following frequency domain expression 2 of the driving current is obtained:

Optionally, the frequency-domain expression 2 of the driving current is transformed by inverse Laplace transform to obtain the time-domain expression of the driving current:

Optionally, selected /2 is used as the target drive voltage to solve the delay of the standard cell, and the target drive voltage can be determined according to the relationship shown in (a) in Figure 3 The target driving time corresponding to /2 is Tr/2.

As shown in (d) of Figure 3, with the target driving voltage /2 is used as the threshold point, the delay between the input voltage passing through the threshold point and the output voltage passing through the threshold point is the delay T _d of the standard cell. Typically, most nonlinear delay model libraries use the /> /2 is used as the threshold point for calculating the standard cell delay, but it is understood that the threshold point is not limited to /> /2.

Therefore, combined with (c), (d), and (e) in Figure 3, the effective capacitance satisfying the equivalent circuit Under the condition that the delay produced by the standard cell is the same as that produced by the equivalent circuit, the driving current of the standard cell charges the circuit with the effective capacitance of the equivalent circuit at the target drive time Tr/2. at target drive voltage /> /2 will equalize the charging power of the circuit.

Based on the above-mentioned relationship that the charging power is equal, according to the target driving time Tr/2 and the target driving voltage /2 processes the time-domain expression of the drive current to obtain the following expression:

Among them, Q represents electric quantity. Transform the obtained expression, and solve the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value:

In one embodiment, the step of establishing a correction parameter library includes:

Construct a preset equivalent circuit of a preset quantity;

Static timing analysis is performed on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit;

Performing dynamic timing analysis on each preset equivalent circuit to determine the second effective capacitance of each preset equivalent circuit;

determining the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit;

The correction parameter is determined according to the deviation, and the correction parameter is associated with the corresponding preset equivalent circuit to establish a correction parameter library.

Wherein, the preset equivalent circuit and the equivalent circuit adopt the same preset circuit model. Optionally, the constructed preset equivalent circuit covers possible equivalent circuits of the RC network as much as possible, for example, there are 90,000 preset equivalent circuits, wherein the resistance values of any two preset equivalent circuits and/or or different capacitance values. Optionally, the ratio of the first effective capacitance C _{eff_s} to the second effective capacitance C _{eff_d} is used to characterize the deviation between the first effective capacitance C _{eff_s} and the second effective capacitance C _{eff_d} . Number the 90,000 preset equivalent circuits, take the number of the preset equivalent circuit as the abscissa, and take the ratio of the first effective capacitance C _{eff_s} to the second effective capacitance C _{eff_d} as the ordinate, as shown in Figure 4 In the correction parameter library shown, in the correction parameter library, the ratio of the first effective capacitance C _{eff_s} to the second effective capacitance C _{eff_d} is used as the correction parameter, and the number of each preset equivalent circuit uniquely corresponds to a first effective capacitance C _{eff_s} The ratio to the second effective capacitance C _{eff_d} uniquely corresponds to one correction parameter.

In one embodiment, the step of performing static timing analysis on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit includes:

Based on static timing analysis, the first effective capacitance of each preset equivalent circuit is determined according to the resistance value and capacitance value in each preset equivalent circuit and the output conversion time of the standard unit corresponding to each preset equivalent circuit.

Specifically, the process of determining the first effective capacitance of the preset equivalent circuit based on the static timing analysis refers to the above-mentioned process of determining the effective capacitance of the equivalent circuit of the resistance-capacitance circuit connected to the output terminal of the standard cell based on the static timing analysis, here I won't repeat them here.

In addition, the standard unit delay analysis of the preset equivalent circuit shown in (a) in Figure 5 through dynamic timing analysis can obtain accurate delay calculation results, driven by the same input signal (the input transition time is _Tri ) , the capacitance value C _eff (as shown in (b) in Figure 5 ) when the preset equivalent circuit shown in Figure 5 (a) achieves the same standard cell delay, that is, (a ) The second effective capacitance of the preset equivalent circuit shown.

In one embodiment, the determination of a preset equivalent circuit matching the equivalent circuit in step S30 includes:

Comparing the resistance value and capacitance value of the equivalent circuit with the resistance value and capacitance value of the preset equivalent circuit;

According to the comparison result, a preset equivalent circuit matching the equivalent circuit is determined.

Specifically, after the output capacitance to be corrected of the standard cell is obtained based on static timing analysis, the resistance value and capacitance value of the equivalent circuit of the standard cell are compared with the resistance value and capacitance value of the preset equivalent circuit, and the equivalent circuit is determined. preset equivalent circuit for effective circuit matching. Based on the correction parameter library shown in Figure 4, the corresponding correction parameters are queried according to the number of the matched preset equivalent circuit, and the output capacitance to be corrected is corrected according to the correction parameters to obtain the output capacitance of the standard unit. In this way, when solving the output capacitance of the standard cell, no dynamic timing analysis is required, the solution speed is fast, and the correction parameters are obtained in advance combined with the dynamic timing analysis, which can ensure the accuracy of the solution.

In an embodiment, after correcting the output capacitance to be corrected according to the correction parameter to obtain the output capacitance of the standard unit, the method further includes:

According to the input conversion time of the standard cell and the output capacitance of the standard cell, query the nonlinear delay model library to obtain the delay of the standard cell.

The parameter solution method of the standard cell circuit provided in Embodiment 1 of the present application can quickly solve the output capacitance of the standard cell to be corrected based on the static timing analysis. In addition, the correction parameters to be corrected are pre-established based on the results of the static timing analysis and dynamic timing analysis. The output capacitance is corrected to obtain an accurate standard cell output capacitance. Based on the accurate standard cell output capacitance obtained by the fast solution, querying the nonlinear delay model library can improve the solution speed and accuracy of the standard cell delay, and in the process of solving the standard cell delay, there is no need for dynamic timing analysis of the equivalent circuit. The solution speed of standard cell delay can be further improved.

FIG. 6 is a schematic structural diagram of an electronic device provided in Embodiment 2 of the present application. The electronic device of the present application includes: a processor 110 , a memory 111 , and a computer program 112 stored in the memory 111 and operable on the processor 110 . When the processor 110 executes the computer program 112 , the steps in the above embodiment of the method for solving parameters of the standard unit circuit are realized.

The electronic device may include, but not limited to, a processor 110 and a memory 111 . Those skilled in the art can understand that FIG. 6 is only an example of an electronic device, and does not constitute a limitation to the electronic device. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as Electronic devices may also include input and output devices, network access devices, buses, and so on.

The processor 110 can be a central processing unit (Central Processing Unit, CPU), and can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.

The storage 111 may be an internal storage unit of the electronic device, such as a hard disk or memory of the electronic device. The memory 111 can also be an external storage device of the electronic device, such as a plug-in hard disk equipped on the electronic device, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash memory card (FlashCard), etc. Further, the memory 111 may also include both an internal storage unit of the electronic device and an external storage device. The memory 111 is used to store computer programs and other programs and data required by the electronic device. The memory 111 can also be used to temporarily store data that has been output or will be output.

The present application also provides a computer storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above embodiment of the method for solving parameters of the standard unit circuit are realized.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

As used herein, the terms "comprises", "comprises" or any other variation thereof are intended to cover a non-exclusive inclusion of elements other than those listed and also other elements not expressly listed.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (10)

1. A parameter solution method of a standard cell circuit, characterized in that, comprising: determining an equivalent circuit of a resistor-capacitor circuit connected to an output terminal of the standard cell based on a preset circuit model; Solving the effective capacitance of the equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of the standard cell; determining a preset equivalent circuit matching the equivalent circuit; Query the correction parameters corresponding to the preset equivalent circuit in the correction parameter library, wherein the correction parameter library includes the correspondence between multiple preset equivalent circuits and multiple correction parameters, and the correction parameters are in the When the preset equivalent circuit is set as the output of the standard cell, according to the first effective capacitance of the preset equivalent circuit determined based on static timing analysis and the first effective capacitance of the preset equivalent circuit determined based on dynamic timing analysis The deviation between the second effective capacitance is determined; The output capacitance to be corrected is corrected according to the correction parameter, so as to obtain the output capacitance of the standard cell. 2. The method according to claim 1, wherein said solving the effective capacitance of said equivalent circuit based on static timing analysis to obtain the output capacitance to be corrected of said standard cell comprises: According to the first capacitance value of the equivalent circuit and the input transition time of the standard cell, query the nonlinear delay model library to determine the output transition time of the standard cell, wherein the first capacitance value represents the equal The overall capacitance of the effective circuit; Based on the static timing analysis, according to the output conversion time of the standard cell, the resistance value of the equivalent circuit and the second capacitance value, the effective capacitance of the equivalent circuit is solved to obtain the to-be-corrected value of the standard cell An output capacitor, wherein the second capacitance value is the capacitance value of each capacitor in the equivalent circuit. 3. The method according to claim 2, wherein, based on the static timing analysis, according to the output transition time of the standard cell, the resistance value and the second capacitance value of the equivalent circuit, the The effective capacitance of above-mentioned equivalent circuit, to obtain the step of the output capacitance to be corrected of described standard unit, comprising: determining an effective capacitance of the equivalent circuit according to the output conversion time of the standard cell, the resistance value of the equivalent circuit, and the second capacitance value; judging whether the effective capacitance converges; If it does not converge, then use the effective capacitance as the first capacitance value of the equivalent circuit, return the first capacitance value according to the equivalent circuit and the input conversion time of the standard unit, and query the nonlinear delay a model library, the step of determining the output conversion time of the standard cell; If converged, the effective capacitance is used as the output capacitance to be corrected of the standard unit. 4. the method as claimed in claim 2 or 3 is characterized in that, according to the output conversion time of described standard cell, the resistance value and the second capacitance value of described equivalent circuit, solve the effective capacitance of described equivalent circuit ,include: converting the time-domain expression of the driving voltage of the standard cell into a frequency-domain expression; According to the frequency domain expression of the driving voltage, the resistance value of the equivalent circuit, and the second capacitance value, determine the frequency domain expression of the driving current of the standard cell, and convert the frequency domain expression of the driving current to Converted to a time-domain expression, the time-domain expression of the driving current is used to characterize the output conversion time of the standard unit, the operating voltage, the driving time, the resistance value of the equivalent circuit and the second capacitance value and the The relationship between the driving current; Obtaining a target driving voltage selected for solving the delay of the standard cell, and a target driving time corresponding to the target driving voltage; According to the target driving time, the time-domain expression of the driving current is processed, so that the charging power of the circuit by the driving current of the standard cell at the target driving time is equal to the effective capacitance of the equivalent circuit at the specified time. The charging power of the circuit under the target driving voltage is equal; Transforming the obtained expression to obtain the effective capacitance of the equivalent circuit according to the output conversion time of the standard unit, the resistance value of the equivalent circuit and the second capacitance value. 5. The method according to claim 1, characterized in that the step of setting up the correction parameter library comprises: Construct a preset equivalent circuit of a preset quantity; performing the static timing analysis on each preset equivalent circuit, and determining the first effective capacitance of each preset equivalent circuit; performing the dynamic timing analysis on each of the preset equivalent circuits to determine the second effective capacitance of each of the preset equivalent circuits; determining the deviation between the first effective capacitance and the second effective capacitance of each preset equivalent circuit; A correction parameter is determined according to the deviation, and the correction parameter is associated with a corresponding preset equivalent circuit to establish the correction parameter library. 6. The method according to claim 5, wherein the step of performing the static timing analysis on each preset equivalent circuit to determine the first effective capacitance of each preset equivalent circuit comprises: Based on the static timing analysis, according to the resistance value and capacitance value in each preset equivalent circuit and the output conversion time of the standard unit corresponding to each preset equivalent circuit, determine the preset values The first effective capacitance of the effective circuit. 7. The method according to claim 1, wherein determining a preset equivalent circuit matching the equivalent circuit comprises: comparing the resistance value and capacitance value of the equivalent circuit with the resistance value and capacitance value of the preset equivalent circuit; According to the comparison result, a preset equivalent circuit matching the equivalent circuit is determined. 8. The method according to claim 1, wherein, after the output capacitance to be corrected is corrected according to the correction parameter to obtain the output capacitance of the standard unit, the method further comprises: According to the input conversion time of the standard cell and the output capacitance of the standard cell, query the nonlinear delay model library to obtain the delay of the standard cell. 9. An electronic device, characterized in that the electronic device comprises a memory, a processor, and a computer program stored in the memory and operable on the processor, when the processor executes the computer program Implementing the steps of the method as claimed in any one of claims 1 to 8. 10. A computer storage medium storing a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 8 when the computer program is executed by a processor.