CN116434823A

CN116434823A - Memory, test method thereof and memory test system

Info

Publication number: CN116434823A
Application number: CN202310493697.XA
Authority: CN
Inventors: 汪锡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-07-14

Abstract

The embodiment of the disclosure provides a memory, a testing method thereof and a memory testing system, wherein the testing method of the memory comprises the following steps: setting redundancy enabling to be effective, and writing first data into all storage units in a normal storage array; after the first data is written, setting redundancy enable to be invalid, and writing second data in a first redundancy unit in a redundancy storage array of the memory, wherein the second data is different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array; after the second data is written, setting redundancy enabling to be effective, and reading the data in all the storage units of the normal storage array; when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently; and determining whether the first redundant unit is used for correctly replacing the first fault unit according to the reading result of the data in the normal storage array.

Description

Memory, test method thereof and memory test system

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a memory, a testing method thereof and a memory testing system.

Background

For a memory cell array (cell array) in a dynamic random access memory (DRAM, dynamic Random Access Memory), there are typically normal (normal) memory cells as well as redundant (redundancy) memory cells. In the event that a normal memory cell has a failed (fail) memory cell, such as is unable to provide normal read and write or storage functions, the failed memory cell may be replaced with a redundant memory cell to ensure that the memory is functioning properly.

How to detect whether a failed memory cell in a memory is properly replaced by a redundant memory cell is a problem that needs to be solved.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a memory, a testing method thereof, and a memory testing system.

According to a first aspect of an embodiment of the present disclosure, there is provided a method for testing a memory, including:

setting redundancy enabling to be effective, and writing first data into all storage units in a normal storage array;

after the first data is written, setting the redundancy enable to be invalid, and writing second data in a first redundancy unit in a redundancy storage array of the memory, wherein the second data is different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

After the second data is written, setting the redundancy enabling to be effective, and reading the data in all storage units of the normal storage array; when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently;

and determining whether the first redundant unit correctly replaces the first fault unit according to the reading result of the data in the normal storage array.

In the above aspect, before writing the first data in the normal storage array of the memory, the method further includes:

determining the first fault unit and acquiring a fault address corresponding to the first fault unit;

distributing the corresponding first redundant unit for the first fault unit, and acquiring a redundant address corresponding to the first redundant unit and a fuse address corresponding to the redundant address;

determining a corresponding first OTP cell in a one-time programmable OTP array of the memory based on the fuse address; the fault address is programmed into a repair address in the first OTP unit; the repair address corresponds to a failure address of the first failure unit; when the redundancy enabling is effective, the access to the fault unit is mapped to a redundancy address corresponding to the first OTP unit which has programmed the fault address according to the fault address;

The determining whether the first redundancy unit correctly replaces the first failure unit according to the reading result of the data in the normal storage array comprises the following steps:

and determining whether the fault address is correctly mapped to the redundant address according to the reading result of the data in the normal storage array.

In the above solution, the determining whether the failure address is correctly mapped to the redundant address according to the read result of the data in the normal storage array includes:

when the reading result shows that a first repair unit with a reading value of second data exists in the normal storage array, determining whether the fault address is correctly mapped to the redundant address according to whether a repair address corresponding to the first repair unit is identical to the fault address;

and when the reading result shows that no storage unit with the reading value of the second data exists in the normal storage array, determining that the mapping relation between the fuse address and the redundant address is wrong.

In the above solution, the determining whether the failure address is correctly mapped to the redundant address according to whether the repair address corresponding to the first repair unit is the same as the failure address, includes:

When the repair address corresponding to the first repair unit is the same as the fault address, determining that the fault address is correctly mapped to the redundant address;

and when the repair address corresponding to the first repair unit is different from the fault address, determining that the mapping relation between the fuse address and the redundant address is wrong or the mapping relation between the fuse address and the fault address is wrong.

In the above scheme, the first failure unit is one memory row and/or one memory column in the normal memory array.

In the above solution, the normal storage array includes a plurality of failure units, and the method further includes:

after determining whether the first redundancy unit correctly replaces the first failed unit, it is determined whether the next failed unit is correctly replaced.

In the above solution, the acquiring the first failure unit includes:

performing fault detection on all storage units contained in a normal storage array of the memory;

determining at least one fault unit in the normal storage array according to the detection result;

any one of the at least one faulty unit is selected as the first faulty unit.

According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising:

the storage array comprises a normal storage array and a redundant storage array;

repair logic test circuitry, coupled to the memory array, configured to:

In the above scheme, the memory further comprises an OTP array;

before writing the first data in the normal memory array, the repair logic test circuitry is configured to:

According to a third aspect of embodiments of the present disclosure, there is provided a memory test system,

comprising the following steps: at least one memory and a test device connected to the at least one memory; wherein,,

the memory comprises a normal memory array and a redundant memory array;

the test device is configured to:

In various embodiments of the present disclosure, a method for testing a memory is used to determine whether a first redundancy unit correctly replaces a first failure unit, including two levels of validation: first, confirm that the first faulty cell maps to the first redundant cell instead of to any redundant cell (non-specific one of the redundant memory arrays except the first redundant cell); second, it is confirmed that the first redundancy unit is mapped to the first failed unit (a specific one of the normal storage arrays or a failed unit for being correctly replaced by the first redundancy unit) instead of being mapped to any one of the normal units/failed units (an unspecified one of the normal units/failed units other than the first failed unit of the normal storage arrays). In this way, the false detection risk is not existed or reduced in the process of redundant repair of the memory; the flow of redundant repair of a memory test system or memory is properly directed.

Drawings

FIG. 1a illustrates a flow diagram of one redundancy repair of a memory test system or memory provided in an embodiment of the present disclosure; FIG. 1b is a schematic flow chart of the test after programming in FIG. 1 a;

FIGS. 2 a-2 d are schematic flow diagrams of the run post-bake test of FIG. 1 b;

FIG. 3 illustrates a block diagram of a memory test system provided in an embodiment of the present disclosure;

FIG. 4 illustrates a block diagram of a memory provided in an embodiment of the present disclosure;

FIG. 5a shows a schematic diagram of the memory array of FIG. 3 or FIG. 4; FIG. 5b shows a schematic diagram of the memory bank of FIG. 5 a;

FIGS. 6 a-6 d are flow diagrams illustrating a test mode of operation of the memory test system of FIG. 3 or the memory of FIG. 4;

FIG. 7a illustrates a flow diagram of another redundancy repair test of the memory test system of FIG. 3 or the memory of FIG. 4; FIG. 7b shows a schematic flow chart of the operational test mode of FIG. 7 a;

fig. 8a to 11d are schematic flow diagrams showing different read results obtained by the operation test mode of fig. 7 b.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure.

FIG. 1a illustrates a flow diagram of a memory test system or a redundancy repair test for a memory provided in an embodiment of the present disclosure.

Referring to FIG. 1a, a memory test system includes a test device or memory including repair logic test circuitry; the test equipment or repair logic test circuit is configured to perform a redundancy repair comprising the steps of:

S101, determining a first fault unit; acquiring a fault address FA_i corresponding to a first fault unit;

s102, distributing a first redundant unit for a first fault unit; acquiring a redundant address RA_i corresponding to the first redundant unit and a fuse address FuA _k corresponding to the redundant address; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

s103, writing a repair address FA2_j in a fuse unit corresponding to the fuse address FuA _k;

s104, running a test after programming to determine whether the first redundant unit correctly replaces the first fault unit.

FIG. 1b is a schematic flow diagram of a run post-write test in a redundancy repair test of a memory test system or memory provided in an embodiment of the present disclosure.

Here, the running post-programming test includes the steps of:

s1041, setting redundancy enable to be effective, and writing first data into all storage units of a normal storage array;

s1042, after first data are written, setting redundancy enable to be invalid, and writing second data in the first redundancy unit based on a redundancy address RA_i, wherein the second data are different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

S1043, after the second data is written, setting the redundancy enabling to be effective, and reading the data in all the storage units of the normal storage array; when the redundancy enabling is effective, the access of the fault unit based on the fault address is automatically switched to the access of the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently;

s1044, determining whether the first redundancy unit correctly replaces the first failure unit according to whether the read result of the data in the normal storage array is inconsistent with the written data (hereinafter, referred to as read result is consistent with expectations).

In some embodiments, the repair logic test circuitry may be provided in an external test device (see in particular FIG. 3 below) or may be provided within the memory (see in particular FIG. 4 below).

In some embodiments, the memory test system or memory includes a DRAM in which only row Refresh (ROR, RAS-only Refresh) is performed after each of the above steps is performed until the next step is entered, ensuring that the data in the DRAM memory cells is not changed. Here and in the following description, a memory test system or a memory including a DRAM is taken as an example. However, the inventive concept is not limited thereto.

Here and hereinafter, the redundancy enable is set to be valid/invalid (when the redundancy enable is valid/invalid, or when the redundancy enable is valid/invalid), instead of setting the redundancy memory cell corresponding to the redundancy address to be valid/invalid, the fuse cell in the OTP array or the fuse block in the OTP memory 27 (refer to fig. 4 described below) is set to be valid/invalid, ensuring that the access to the failed cell cannot be switched to the redundancy cell through the OTP memory when the redundancy enable is set to be invalid, and the access to the failed cell can be automatically switched to the corresponding redundancy cell when the redundancy enable is set to be valid.

It should be noted that fig. 2a to 2d show a part of a memory array, and the memory includes a plurality of memory banks (including the first memory bank 101). A portion of each bank may be a normal memory array and the remaining memory arrays may be redundant memory arrays. The first bank 101 is described below as an example, and the first bank 101 includes a normal memory array 110 and a redundant memory array 120. Illustratively, the redundant cells 121 in the redundant storage array may be used to replace the failed cells 111 in the normal storage array.

The specific process of running the post-burn-in test in the redundancy repair test is described in detail below with reference to fig. 1b, 2a, 2b, and 2 c.

Step S1041 is performed, as shown in fig. 2a, to write the first data W1 to all the memory cells in the normal memory array 110 when the redundancy enable is valid. The first data W1 is written in the normal memory array 110 except for the first failure unit 111, the first failure unit 111 is written to automatically skip the first redundancy unit 121, and the first redundancy unit 121 in the redundant memory array 120 is written to the first data W1.

After the first data W1 is written, the second data W2 is written in the first redundancy unit 121 based on the redundancy address ra_i when the redundancy enable is disabled, as shown in fig. 2b, and the second data W2 is different from the first data W1. The first data W1 stored in all the memory cells in the normal memory array 110 remains unchanged, and the data stored in the first redundancy unit 121 is changed from the first data W1 to the second data W2.

Here and below, the second data W2 is exemplarily represented as a logical "1", and the first data W1 is represented as a logical "0"; alternatively, the second data W2 is represented as a logical "0", and the first data W1 is represented as a logical "1".

After the second data W2 is written, the data R1 is read from all the memory cells of the normal memory array 110 when the redundancy enable is valid as shown in fig. 2c after steps S1043 and S1044 are performed. The read result of the normal memory array 110 except the first failure unit 111 is the first data W1, which corresponds to the written first data W1 as shown in fig. 2 a; the first failure unit 111 is read by automatically skipping the first redundancy unit 121, the read result of the first failure unit 111 is different from the write first data W1 shown in fig. 2b in the first redundancy unit 121 (i.e. when the first redundancy unit is correctly replaced by the first failure unit, the write result of the data stored in the redundancy unit in fig. 2b will change the read result of the failure unit in the storage array, and the read result of the data read from all the storage units in the storage array according to the method of the present application should be not identical, which is the case in short for the read result to meet the expectation, and conversely, the write result of the data stored in the redundancy unit in fig. 2b will not change the read result of the data read from the storage array when the first redundancy unit cannot correctly replace the first failure unit, so the read result of the data read from all the storage units in the storage array according to the method of the present application is identical, which is the read result for short for the data read to meet the expectation.

In other embodiments, the specific process of running the post-burn-in test in the redundancy repair test is described in detail below in conjunction with FIGS. 1b, 2a, 2d, and 2 c.

Step S1041 is performed, and is described with reference to fig. 2a, and is not described herein.

After the first data W1 is written, the second data W2 is written to all the memory cells in the normal memory array 110 based on the redundancy address ra_i when the redundancy enable is invalid, as shown in fig. 2d, and the second data W2 is different from the first data W1. The first data W1 stored in the first redundancy unit 121 remains unchanged without jumping to write the first redundancy unit 121 to the first failure unit 111. The data stored in all the memory cells in the normal memory array 110 is changed from the first data W1 to the second data W2, and the first data W1 stored in the first redundancy unit 121 remains unchanged.

After the second data W2 is written, the data R1 is read from all the memory cells of the normal memory array 110 when the redundancy enable is valid as shown in fig. 2c after steps S1043 and S1044 are performed. The read result of the normal memory array 110 except the first failure unit 111 is the second data W2, which corresponds to the written second data W2 as shown in fig. 2 d; reading the first faulty unit 111 automatically jumps to read the first redundant unit 121, where the result of reading the first faulty unit 111 is that the first data W1 stored in the step of fig. 2a in the first redundant unit 121 is different from the result of writing the second data W2 as shown in fig. 2d (i.e. when the first redundant unit correctly replaces the first faulty unit, the result of writing the storage data of all the storage units in the normal storage array 110 in fig. 2d will change the result of writing the storage data of the faulty unit in the storage array, and the result of reading the data from all the storage units in the storage array according to the method of the present application should not be identical, which is the case where the result of reading is expected, and conversely, when the first redundant unit fails to correctly replace the first faulty unit, the result of writing the storage data of all the storage units in the storage array will not change the result of writing the data of the faulty unit in the storage array, so that the result of reading the data from all the storage units in the storage array according to the method of the present application is identical, which is the result of reading is expected.

Here, it is determined whether the first redundancy unit correctly replaces the first defective unit according to whether the read result is not in conformity with the expectation.

It should be noted that, fig. 2a, fig. 2d, fig. 2c, fig. 2a, fig. 2b, fig. 2c illustrate a case where the first redundancy unit correctly replaces the first failure unit, that is, a case where the first failure unit is correctly mapped to the first redundancy unit.

In the embodiment of the application, a certain error message can be filtered out by running the test after programming; however, if the allocated redundant cells are different from the redundant cells actually replaced, a mapping error (i.e., if the read data are the same) can be determined, and if the read data are different, an error that cannot be determined occurs.

Here, the error that cannot be judged may be: 1. a mapping error exists between the plurality of failure units and the plurality of redundant storage units; this is the case that an error occurs in the above-described step S102; 2. in the case where the first redundant memory cell ra_i is replaced with another memory cell (instead of the first failed cell), an error occurs in step S103, that is, the first failed address to be repaired by programming is fa_i, but other addresses fa2_j are programmed.

In this way, when detecting whether a defective memory cell in the memory test system or the memory is correctly replaced with a redundant memory cell, an erroneous situation may occur that cannot be judged. Therefore, it is necessary to determine whether the failed storage unit is correctly replaced by the redundant storage unit by further performing a judgment to identify an error that cannot be judged.

It should be noted that, in details not mentioned in the embodiments of the disclosure shown in fig. 1a, fig. 1b, fig. 2a, fig. 2b, fig. 2c, fig. 2d, other specific details of each structure or component in each flow diagram, and steps of the testing method and so on may be referred to in the following fig. 7a, fig. 7b, fig. 6a to fig. 6d, fig. 8a to fig. 8d, fig. 9a to fig. 9d, fig. 10a to fig. 10d, and fig. 11a to fig. 11d, which are not repeated herein.

Based on this, in order to solve one or more of the above problems, embodiments of the present disclosure provide a memory, a testing method thereof, and a memory testing system.

FIG. 3 illustrates a block diagram of a memory test system provided in an embodiment of the present disclosure.

Referring to fig. 3, a memory test system 10 is provided according to an embodiment of the present disclosure, including: at least one memory 13 and a test device 11 connected to the at least one memory 13; wherein,,

The memory 13 includes a normal memory array and a redundant memory array;

a test device 11 configured to:

after the first data is written, setting redundancy enabling to be invalid, and writing second data in a first redundancy unit in the redundancy storage array, wherein the second data is different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

after the second data is written, setting redundancy enabling to be effective, and reading the data in all the storage units of the normal storage array; when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently;

and determining whether the first redundant unit is used for correctly replacing the first fault unit according to the reading result of the data in the normal storage array.

Memory test system 10 may be implemented in a module architecture such as a dual in-line memory module (DIMM) or a High Bandwidth Memory (HBM) device in which memory and test equipment are integrated into one substrate.

The memory test system 10 comprises at least one memory 13 and a test device 11 connected to the at least one memory. The memory 13 may include volatile memory and nonvolatile memory.

The memory 13 includes a memory array (not shown in fig. 3), which may include a normal memory array and a redundant memory array. A portion of the storage arrays may be normal storage arrays and the remaining storage arrays may be redundant storage arrays. The redundant cells in the redundant memory array may be used to replace failed cells in the normal memory array. The normal storage array may be characterized as a subscriber unit accessible to a host (not shown in fig. 3).

In some embodiments, the memory may be a non-volatile memory. In an exemplary embodiment, the memory may be a high-capacity storage medium, such as a Solid State Drive (SSD) or a memory card. Under control of a host (not shown in fig. 3), the test device may store data to the nonvolatile memory, or may read data stored in the nonvolatile memory.

In some embodiments, the memory may be volatile memory. In an exemplary embodiment, the memory may be any of a variety of memory devices supporting high speed operation, such as a DRAM. For example, write data received from a host (not shown in fig. 3) or data read from a nonvolatile memory may be temporarily stored to a volatile memory.

The test device 11 may store various information (e.g., metadata information and a mapping table) required for the operation of the memory test system 10 to the volatile memory, and may access the nonvolatile memory based on the information stored in the volatile memory.

The test device 11 is configured to: and running a test mode to determine whether the redundant unit correctly replaces the fault unit. The detailed process is described with reference to the following fig. 6a to 6d, and will not be repeated here.

Fig. 4 shows a block diagram of a memory provided in an embodiment of the present disclosure.

Referring to fig. 4, an embodiment of the present disclosure provides a memory 20, comprising:

a storage array 23 including a normal storage array 210 and a redundant storage array 220;

repair logic test circuitry 21, coupled to memory array 23, is configured to:

setting redundancy enable to be active, writing first data to all memory cells in the normal memory array 210;

after the first data is written, setting redundancy enable to be invalid, and writing second data in a first redundancy cell in the redundant memory array 220 of the memory, the second data being different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

After the second data is written, the redundancy enable is set to be valid, and the data in all the memory cells of the normal memory array 210 are read; when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently;

The memory 20 may be a nonvolatile memory. In an exemplary embodiment, the memory may be a high-capacity storage medium, such as a Solid State Drive (SSD) or a memory card. The repair logic test circuitry may store data to the non-volatile memory or may read data stored in the non-volatile memory under control of the test device (not shown in fig. 4).

The memory 20 may be a volatile memory. In an exemplary embodiment, the memory may be any of a variety of memory devices supporting high speed operation, such as a DRAM. For example, write data received from the test device or data read from the nonvolatile memory may be temporarily stored to the volatile memory.

The repair logic test circuit 21 may store various information (e.g., metadata information and a mapping table) required for the operation of the test device to the volatile memory, and may access the nonvolatile memory based on the information stored in the volatile memory.

The memory 20 includes at least one memory array 23 and repair logic test circuitry 21 coupled to the at least one memory array 23.

The storage array 23 may include a normal storage array 210 and a redundant storage array 220. A portion of the storage array 23 may be a normal storage array and the remaining storage arrays 23 may be redundant storage arrays. The redundant cells in the redundant memory array may be used to replace failed cells in the normal memory array. A normal memory array may be characterized as a memory cell accessible to a test device.

Repair logic test circuit 21 includes control logic circuit 25, OTP memory 27, row decoder 29, and column decoder 31.

The row decoder 29 may be connected to the memory array 23 through a word line WL. The row decoder 29 may select one of the word lines WL based on the address ADDR, and may control the voltage of the selected word line.

The column decoder 31 may be connected to the memory array 23 through a bit line BL. The column decoder 31 may select a portion of the bit line BL based on the address ADDR, and may control or sense a voltage of the selected bit line. In some embodiments, column decoder 31 may be coupled to memory array 23 via normal bit lines NBL and redundant bit lines RBL.

The control logic 25 may be configured to respond to fuse settings for the OTP memory 27 with repair operations by the memory controller or test equipment. The failed cell in the normal memory array 210 may be replaced with the associated cell of the redundant memory array 220 by the fuse setting of the OTP memory 27. For example, OTP memory 27 may receive address ADDR from control logic circuit 25. The address ADDR may be an address associated with a normal bit line NBL corresponding to the failed column (i.e., a failed address). In this case, the OTP memory 27 may allocate a redundancy cell for the failed cell, burn-in a failure address in a fuse cell corresponding to the redundancy cell to repair the failed cell, and output a repair address corresponding to the redundancy cell to allow the column decoder 31 to select the redundancy bit line RBL instead of the normal bit line NBL.

The repair logic test circuit 21 is configured to: and running a test mode to determine whether the redundant unit correctly replaces the fault unit. The detailed process is described with reference to the following fig. 6a to 6d, and will not be repeated here.

In some embodiments, the memory comprises dynamic random access memory.

Here and in the following description, a memory is exemplified as a DRAM. However, the inventive concept is not limited thereto. Hereinafter, the volatile memory may be referred to as a DRAM.

FIG. 5a shows a schematic diagram of the memory array of FIG. 3 or FIG. 4; fig. 5b shows a schematic diagram of the memory bank of fig. 5 a.

Referring to fig. 4 and 5a, the memory array 23 of the memory 20 includes a plurality of memory banks 201 to 204. Since each of the memory banks 201 to 204 may have substantially the same structure. However, the present invention is not limited to this particular structure; rather, the storage array 23 of the memory 20 may be configured with any of a number of different types of structures depending on the memory type or memory function.

Referring to fig. 5a and 5b, a portion of each memory bank may be a normal memory array and the remaining memory arrays may be redundant memory arrays. Each memory bank includes a plurality of memory cells arranged in a row and column array, the memory cells being the smallest unit of memory for storing a bit of

binary code

0 or 1. The first bank 201 is described below as an example, and the first bank 201 includes a normal memory array 210 and a redundant memory array 220. Illustratively, the first redundant cell 221 in the redundant memory array 220 may be a replacement for the first failed cell 211 in the normal memory array.

Fig. 6a to 6d show a flow diagram of an operation test mode of the memory test system of fig. 3 or the memory of fig. 4.

Referring to fig. 4 and 6a to 6d, the operation test mode includes the steps of:

after the first data is written, setting redundancy enable to be invalid, and writing second data in a first redundancy unit in a redundancy storage array of the memory, wherein the second data is different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

It should be noted that, under the Test Mode Select (TMS), the redundancy enable disable or the redundancy enable of the memory Test system or the memory may be implemented through a certain Test Mode command: when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enable is inactive, both the failed unit and the redundant unit are accessed independently.

Here and hereinafter, redundancy enable disable or redundancy enable for a memory test system or a memory is not actually set to be active/inactive for a redundant memory cell corresponding to a redundancy address, but set to be active/inactive for a fuse cell in an OTP array or a fuse block in the OTP memory 27, ensuring that access to a failed cell cannot be switched to a redundant cell through the OTP memory when the redundancy enable is set to be inactive, and that access to a failed cell can be automatically switched to a corresponding redundant cell when the redundancy enable is set to be active.

The case where the first failure unit 211 is correctly replaced with the first redundancy unit 221 will be described with reference to fig. 6a to 6 d:

as shown in fig. 6a, when redundancy enable is active, the first data W1 is written to all memory cells in the normal memory array 210. The first data W1 is written in the normal memory array 210 except the first failure unit 211, the first failure unit 111 is written to automatically skip the first redundancy unit 221, and the first redundancy unit 221 in the redundancy memory array 220 is written to the first data W1.

As shown in fig. 6b, after the first data W1 is written, when the redundancy enable is disabled, the second data W2 is written in the first redundancy unit 221 based on the redundancy address ra_i, and the second data W2 is different from the first data W1. The first data W1 stored in all the memory cells in the normal memory array 210 remains unchanged, and the data stored in the first redundancy unit 221 is changed from the first data W1 to the second data W2.

As shown in fig. 6c, after the second data W2 is written, the data R1 is read from all the memory cells of the normal memory array 210 when the redundancy enable is valid. The read result of the normal memory array 210 except the first failure unit 211 is the first data W1, which corresponds to the written first data W1 as shown in fig. 6 a; the first redundancy unit 121 is read by automatically skipping the first failure unit 111, and the read result of the first redundancy unit 221 is different from the second data W2 stored in the step of fig. 6b, and the first data W1 written in the first redundancy unit 121 as shown in fig. 6 a.

As shown in fig. 6d, when the first redundancy unit correctly replaces the first failure unit, the overwriting of the stored data in the redundancy unit in fig. 6b will change the result of reading the data from the failure unit in the storage array, and the result of reading the data from all the storage units in the storage array according to the method of the present application should not be identical, which is the case in short below, where the read result is as expected; in contrast, when the first redundancy unit fails to replace the first failure unit correctly, the result of reading the data in the storage array is not changed by overwriting the data stored in the redundancy unit in fig. 6b, so that the result of reading the data from all the storage units in the storage array according to the method of the present application is identical, and the following abbreviated as the reading result meets the expectations. Illustratively, the read result is a first unexpected result fail-0 indicating that the read result of the first failure unit 211 of fig. 6c is unexpected, and the first failure unit 211 is correctly replaced by the first redundancy unit 221 according to the first unexpected result fail-0, such that the read result is indicative of the unexpected result.

The running test pattern may determine whether the first faulty unit must be mapped to the first redundant unit without the risk of false detection of the test pattern or reduced.

FIG. 7a illustrates a flow diagram of another redundancy repair test of the memory test system of FIG. 3 or the memory of FIG. 4.

Referring to FIG. 7a, a memory test system includes a test device or memory includes repair logic test circuitry; the test device or repair logic test circuit is configured to perform a redundancy repair test comprising the steps of:

s701, acquiring a first fault unit; obtaining a fault address FA_i;

s702, distributing a first redundant unit; obtaining a redundant address RA_i;

s703, writing a repair address FA2_j in the first OTP unit corresponding to the fuse address FuA _k;

s704, running a test mode;

s705, determining whether the first redundancy unit correctly replaces the first failure unit. Referring to fig. 7a, in some embodiments, a first faulty cell is acquired and the repair logic test circuit is configured to perform step S701:

Any one of the at least one faulty unit is selected as the first faulty unit.

The failed address includes a row address of a memory row and/or a column address of a memory column of failed memory cells in the normal memory array. Illustratively, the failed address fa_i is the column address of the first failed cell.

Referring to fig. 7a, in some embodiments, a first redundancy unit is allocated and the repair logic test circuitry is configured to perform step S702, step S703:

performing state detection on all OTP units contained in an OTP array of an OTP memory;

and according to the detection result, allocating an un-programmed OTP unit for programming the repair address, wherein the un-programmed OTP unit corresponds to the first redundancy unit.

The redundant addresses include row addresses of one memory row and/or column addresses of one memory column of redundant memory cells in the redundant memory array. Illustratively, the redundant address ra_i is the column address of the first redundant cell.

In some embodiments, the memory further comprises a one-time programmable (OTP, one Time Programmable) memory, the OTP memory comprising an OTP array, the OTP array for storing a failed address of a failed memory cell in the normal memory array, the address of the OTP array for corresponding to a redundant address of a redundant memory cell in the redundant memory array.

In some embodiments, the OTP array includes a plurality of OTP memory cells arranged in a row and column array. The OTP memory is the smallest memory cell of the OTP memory for storing one bit of

binary code

0 or 1, and cannot be changed or cleared again after writing the one bit of binary code. An OTP cell may include one or more OTP memory cells for storing one or more bits of binary code.

Illustratively, the OTP cell includes an antifuse (anti-fuse) structure. By the high voltage being able to breakdown the antifuse structure dielectric layer, the antifuse structure before breakdown exhibits a high resistance state and the antifuse structure after breakdown exhibits a low resistance state, which enables programming of the OTP cell to write the necessary information in the OTP cell, such as to write the fail address fa_i here. It should be noted that, after the fault address fa_i is written, it cannot be changed or cleared again.

Referring to fig. 7a, in the process of redundancy repair, the mapping relationship between the failure unit and the redundancy single redundancy includes two levels of mapping relationships: first, a fuse address FuA _k corresponding to the redundant address ra_i is found; second, the repair address fa2_j obtained by writing the information corresponding to the fail address fa_i on the fuse corresponding to the fuse address FuA _k. It can be understood that if the fuse address FuA _k is found to be not corresponding to the redundancy address ra_i, or if the address information written on the fuse corresponding to the fuse address FuA _k, that is, the repair address fa2_j is not consistent with the failure address fa_i, an error may occur in the mapping relationship between the failure unit and the redundancy single redundancy, resulting in incorrect redundancy repair; when redundancy enable is active, a read or write to the failed address fa_i will not correctly map to the corresponding redundant address read or write.

For example, when the fuse address FuA _k is the address of the first OTP unit and correctly corresponds to the redundant address ra_i, and the repair address fa2_j is the information stored after programming in the first OTP unit and the stored information is consistent with the information of the fault address fa_i, the fuse address FuA _k may correctly correspond to the redundant address ra_i, the repair address fa2_j may correctly correspond to the fault address fa_i, and the mapping relationship between the redundant address ra_i and the fault address fa_i may be obtained. When the redundancy enable is active, the reading or writing of the failed address fa_i can be correctly mapped to the reading or writing of the redundant address ra_i.

When the fuse address FuA _k is the address of the first OTP unit and cannot correctly correspond to the redundant address RA_i, or when the repair address FA2_j is the information stored in the first OTP unit after programming, and the stored information is inconsistent with the information of the fault address FA_i, the mapping relationship between the redundant address RA_i and the fault address FA_i is incorrect. When the redundancy enable is active, the reading or writing of the failed address fa_i cannot be correctly mapped to the reading or writing of the redundant address ra_i.

FIG. 7b illustrates a flow diagram of a test mode of operation in a redundancy repair test of a memory test system or memory provided in an embodiment of the present disclosure.

Here, the operation test mode includes the steps of:

s7041, setting redundancy enabling to be effective, and writing first data into all storage units in a normal storage array;

s7042, after writing the first data, setting redundancy enable to be invalid, writing second data in a first redundancy unit in a redundancy storage array of the memory, the second data being different from the first data; the first redundancy unit is used for repairing a first fault unit in the normal storage array;

s7043, after the second data is written, setting redundancy enabling to be effective, and reading data in all storage units of the normal storage array; when the redundancy enabling is effective, the access fault unit is automatically switched to access the redundancy unit corresponding to the fault unit; when the redundancy enabling is invalid, the fault unit and the redundancy unit are required to be accessed independently;

s7044, based on the read result of the data in the normal storage array, it is determined whether the first redundancy unit correctly replaces the first failure unit.

The specific procedure of the operation test mode in the redundancy repair test will be described in detail with reference to fig. 7b, 8a to 8d, 9a to 9d, 10a to 10d, and 11a to 11 d.

Referring to fig. 7b, step S704 is performed, and the test mode is run to obtain a read result; step S705 (including step S7051, determining whether the read result meets the expectation, and step S7052, determining whether fa2_j and fa_i meet), determining whether the first redundant unit correctly replaces the first failed unit according to the read result.

In some embodiments, the repair logic test circuitry is configured to perform step S7051:

when the read result shows that the first data of the first repair unit with the read value is in the normal storage array (the read result accords with the expectation), determining whether the fault address is correctly mapped to the redundant address according to whether the repair address corresponding to the first repair unit is the same as the fault address (the repair address FA2_j accords with the fault address FA_i);

when the read result shows that the memory cell with the read value of the first data does not exist in the normal memory array (the read result does not accord with the expectation), the mapping relation between the fuse address and the redundant address is determined to be wrong (comprising a first result END1 and a second result END 2).

In some embodiments, the repair logic test circuitry is configured to perform step S7052:

when the repair address corresponding to the first repair unit is the same as the fault address, determining that the fault address is correctly mapped to the redundant address (refer to fig. 7b, 8a to 8d for understanding that the expected result is not met);

when the repair address corresponding to the first repair unit is different from the fail address, determining that the mapping relationship between the fuse address and the redundant address is wrong (refer to fig. 7b, and the second unexpected result fail-1 in fig. 9a to 9 d) or the mapping relationship between the fuse address and the fail address is wrong (refer to fig. 7b, and the third unexpected result fail-2 in fig. 10a to 10 d).

It should be noted that, when the read result indicates that the read value of the first repair unit exists in the normal memory array as the first data, and the repair address corresponding to the first repair unit is the same as the failure address, the correspondence relationship between the fuse address and the redundancy address, and between the fuse address and the failure address is determined to be correct (refer to fig. 7b, fig. 11a to fig. 11d, and the fourth non-conforming expected result fail-3 is understood).

Referring to fig. 7b, 8a to 8d, when the read result shows that the read value of any cell in the normal memory array is the first data, that is, should be corresponding to the first redundancy cell 221, since the correspondence between the fuse address FuA _k and the redundancy address ra_i is wrong, the fuse address FuA _k corresponds to one of the unused second redundancy cells 223, and it is determined that the failure address is not correctly mapped to the redundancy address, as follows:

as shown in fig. 8a, when redundancy enable is active, the first data W1 is written in the normal memory array 210. The normal memory array 210 is written with the first data W1 except the first fail cell 211; the write first failure unit 211 automatically jumps to write the first redundancy unit 221, and the first redundancy unit 221 is written with the first data W1. No faulty cells in the normal memory array 210 are mapped to the second redundancy cells 223 (or, here, the second redundancy cells 223 are unused), and the second redundancy cells 223 are not written with the first data W1.

As shown in fig. 8b, after the first data W1 is written, when the redundancy enable is disabled, the second data W2 is written in the second redundancy cell 223 in the redundant memory array 220, and the second data W2 is different from the first data W1. The normal memory array 210 remains written with the first data W1 except for the first fail cell 211, and the first redundancy cell 221 remains written with the first data W1, and the second redundancy cell 223 is written with the second data W2.

As shown in fig. 8c, after the second data W1 is written, the read data R1 in the normal memory array 210 is read when the redundancy enable is valid. The first redundancy unit 221 remains written in the first data W1, and the read result of the read first failure unit 211 is the first data W1, i.e. the read result of the read normal memory array 210 including the first failure unit 211 is the first data W1; the first redundancy unit 221 is automatically jumped to read by the first failure unit 211, and the read data of the first failure unit 211 is the first data W1.

As shown in fig. 8d, the read result is the first result END1, and the first result END1 shows that all the read data (refer to the first data W1 in fig. 8 c) are identical to the write data (refer to the first data W1 in fig. 8 a) (hereinafter, the read result is not expected), and it is determined that the first redundancy unit does not correctly replace the first failure unit. Illustratively, the read result indicates that the read result of the first faulty unit 211 is not expected to be the first data W1 and the written first data W1 are not expected, but because the fuse address FuA _k and the redundancy address ra_i are wrongly associated, and correspond to the second redundant unit 223 which is not used, the final read result indicates that the read value of any unit in the normal memory array is the first data (i.e. the read result is not expected), and it may be determined that the first redundant unit 221 is not correctly substituted for the first faulty unit 211 according to the first result END 1.

Referring to fig. 7b, 9a to 9d, when there is first data in the normal memory array as the read value of the first repair unit and the repair address corresponding to the first repair unit is different from the fail address, that is, should be corresponding to the first redundancy unit 221, since the correspondence between the fuse address FuA _k and the redundancy address ra_i is wrong, the fuse address FuA _k corresponds to a third redundancy unit 225 that has been used, and it is determined that the fail address is not correctly mapped to the redundancy address, as follows:

as shown in fig. 9a, when redundancy enable is active, the first data W1 is written in the normal memory array 210. Except the first failure unit 211 and the second failure unit 213 in the normal memory array 210, the first redundancy unit 221 and the third redundancy unit 225 are written with the first data W1; the first and

second failure units

211 and 213 are written to the first and

third redundancy units

221 and 225 by automatic skip writing, and the first and

third redundancy units

221 and 225 are written as the first data W1.

As shown in fig. 9b, after the first data W1 is written, when the redundancy enable is disabled, the second data W2 is written in the third redundancy unit 225 in the redundant memory array 220, and the second data W2 is different from the first data W1. The normal memory array 210 is kept to be written with the first data W1 except the first failure unit 211 and the second failure unit 213, the first redundancy unit 221 is kept to be written with the first data W1, the third redundancy unit 225 is written with the second data W2 different from the second data, and the data stored in the third redundancy unit 225 is changed from the first data W1 to the second data W2.

As shown in fig. 9c, after the second data W2 is written, the read data R1 in the normal memory array 210 is read when the redundancy enable is enabled. Although the first redundancy unit 221 remains written with the first data W1, the read result of the first failure unit 211 is the first data W1; however, the third redundancy unit 225 is written to the second data W2, and the read result of the third redundancy unit 225 is the second data W2; the first and

second fault units

211 and 213 are automatically jumped to read the first and third

redundant units

221 and 225, wherein the read data of the first fault unit 211 is the first data W1, and the read data of the second fault unit 213 is the second data W2.

As shown in fig. 9d, the read result is the second result END2, and the second result END2 shows that the read data (refer to the second data W2 of the third redundancy unit 225 in fig. 9 c) is different from the write data (refer to the first data W1 of the third redundancy unit 225 in fig. 9 a), so that it is determined that the first redundancy unit does not correctly replace the first failure unit. Illustratively, the read result indicates that the read result of the second faulty unit 213 is not in accordance with the written first data W1, but corresponds to a used third redundant unit 225 because of the error in the correspondence between the fuse address FuA _k and the redundant address ra_i, the final read result indicates that the read value of the second faulty unit 213 is the first data (i.e. the read result is in accordance with the expectation), but not the read value of the first faulty unit 211 is the first data, and the first redundant unit 221 may not correctly replace the first faulty unit 211 according to the second result END 2.

Referring to fig. 7b, 10a to 10d, when there is first data in the normal memory array as the read value of the first repair unit and the repair address corresponding to the first repair unit is different from the fail address, that is, the fuse address FuA _k corresponds correctly to the redundancy address ra_i, but should correspond to the fail address of the first fail unit 211, since the address information written on the fuse corresponding to the fuse address FuA _k, that is, the repair address fa2_j does not coincide with the fail address fa_i, the repair address fa2_j corresponds to the first normal cell 215 in one normal memory array, it is determined that the fail address is not correctly mapped to the redundancy address, as follows:

as shown in fig. 10a, when redundancy enable is active, first data W1 is written in the normal memory array 210. The first redundancy unit 221 is written to the first data W1 except the first normal unit 215 in the normal memory array 210; the write first normal unit 215 automatically jumps to write the first redundancy unit 221, and the write data of the first normal unit 215 is the first data W1.

As shown in fig. 10b, after the first data W1 is written, when the redundancy enable is disabled, the second data W2 is written in the first redundancy cell 221 in the redundant memory array 220, and the second data W2 is different from the first data W1. The normal memory array 210 remains written with the first data W1 except for the first normal cell 215, and the first redundancy cell 221 is written with the second data W2. The data stored by the first redundancy unit 221 is changed from the first data W1 to the second data W2.

As shown in fig. 10c, after the second data W2 is written, the read data R1 in the normal memory array 210 is read when the redundancy enable is enabled. The first redundancy unit 221 is written into the second data W2, and the read first normal unit 215 automatically jumps to read the first redundancy unit 221, and the read data of the first normal unit 215 is the second data W2.

As shown in fig. 10d, the read result is the second result END2, and the second result END2 shows that the read data (the read data of the first normal unit 215 is the second data W2 with reference to fig. 10 c) is different from the write data (the write data of the first normal unit 215 is the first data W1 with reference to fig. 10 a) (hereinafter, the read result is consistent with expectations), and it is determined that the first redundant unit does not correctly replace the first failure unit. Illustratively, the read result of the first normal unit 215 indicates that the second data W2 does not correspond to the written first data W1, and although the corresponding relationship between the fuse address FuA _k and the redundant address ra_i is correct, the corresponding relationship should be the failure address of the first failure unit 211, and since the repair address fa2_j, which is the address information written on the fuse corresponding to the fuse address FuA _k, does not correspond to the failure address fa_i, the first redundancy unit 221 may not correctly replace the first failure unit 211 according to the second result END 2.

Referring to fig. 7b, 11a to 11d, when the read result shows that the read value of the first repair unit exists in the normal memory array as the first data, and the repair address corresponding to the first repair unit is the same as the fail address, that is, the fuse address FuA _k corresponds correctly to the redundancy address ra_i, and the address information written on the fuse corresponding to the fuse address FuA _k, that is, the repair address fa2_j corresponds to the fail address fa_i, it is determined that the fail address is correctly mapped to the redundancy address, as follows:

as shown in fig. 11a, when redundancy enable is active, the first data W1 is written in the normal memory array 210. The normal memory array 210 is written with the first data W1 except the first fail unit 211, and the first redundancy unit 221 is written with the first data W1; the write first failure unit 211 automatically jumps to write the first redundancy unit 221, and the write data of the first failure unit 211 is the first data W1.

As shown in fig. 11b, after the first data W1 is written, when the redundancy enable is disabled, the second data W2 is written in the first redundancy cell 221 in the redundant memory array 220, and the second data W2 is different from the first data W1. The normal memory array 210 remains written with the first data W1 except for the first fail cell 211, and the first redundancy cell 221 is written with the second data W2. The data stored by the first redundancy unit 221 is changed from the first data W1 to the second data W2.

As shown in fig. 11c, after the second data W2 is written, the read data R1 in the normal memory array 210 is read when the redundancy enable is enabled. The first redundancy unit 221 is written into the second data W2, and the read first failure unit 211 automatically jumps to read the first redundancy unit 221, and the read data of the first failure unit 211 is the second data W2.

As shown in fig. 11d, the read result is the third result END3, and the third result END3 shows that the read data (the read data of the first redundancy unit 221 is the second data W2 with reference to fig. 11 c) and the write data (the write data of the first redundancy unit 221 is the first data W1 with reference to fig. 11 a) are different (hereinafter, the read result is consistent with expectations), and it is determined that the first redundancy unit correctly replaces the first failure unit. Illustratively, the read result of the first redundancy unit 221 indicates that the second data W2 does not correspond to the written first data W1, the corresponding relationship between the fuse address FuA _k and the redundancy address ra_i is correct, the address information written on the fuse corresponding to the fuse address FuA _k, that is, the repair address fa2_j corresponds to the failure address fa_i, and the first redundancy unit 221 can be determined to replace the first failure unit 211 correctly according to the third result END 3.

In some embodiments, the normal storage array includes a plurality of failed cells therein, and the repair logic test circuitry is configured to:

after determining whether the first redundant unit correctly replaces the first failed unit, it is determined whether the next failed unit is correctly replaced.

Here, the first faulty unit and the next faulty unit are both a storage row and/or a storage column where the faulty storage element in the normal storage array is located. The memory cell is the smallest unit of memory that is used to hold one bit of

binary code

0 or 1.

Illustratively, the first faulty unit is a storage column where the faulty storage element in the normal storage array is located, and the next faulty unit is a storage row where the faulty storage element in the normal storage array is located; the first failure unit is a storage row where the failure storage element in the normal storage array is located, and the next failure unit is a storage column where the failure storage element in the normal storage array is located.

In various embodiments of the present disclosure, determining whether a first redundant unit correctly replaces a first failed unit during redundancy repair of a memory includes two levels of validation: first, confirm that the first faulty cell maps to the first redundant cell (a specific redundant cell in the redundant memory array or a redundant cell for correctly replacing the first faulty cell), or confirm that the first faulty cell maps to any redundant cell (an unspecified redundant cell other than the first redundant cell in the redundant memory array); second, it is confirmed that the first redundancy unit is mapped to the first fail unit (a specific fail unit in the normal storage array or a fail unit for being correctly replaced by the first redundancy unit), or it is confirmed that the first redundancy unit is mapped to any one of the normal units/fail units (an unspecified normal unit/fail unit other than the first fail unit in the normal storage array). In this way, the false detection risk is not existed or reduced in the process of redundant repair of the memory; the flow of redundant repair of a memory test system or memory is properly directed.

The embodiment of the disclosure provides a method for testing a memory, which comprises the following steps:

In some embodiments, prior to writing the first data in the normal storage array of the memory, the method further comprises:

determining a first fault unit and acquiring a fault address corresponding to the first fault unit;

Distributing a corresponding first redundant unit for the first fault unit, and acquiring a redundant address corresponding to the first redundant unit and a fuse address corresponding to the redundant address;

determining a corresponding first OTP cell in the one-time programmable OTP array of the memory based on the fuse address; burning the fault address as a repair address in the first OTP unit; the repair address corresponds to the fault address of the first fault unit; when the redundancy enabling is effective, the access to the fault unit maps the fault address to the redundancy address corresponding to the first OTP unit which has programmed the fault address;

determining whether the first redundancy unit correctly replaces the first failure unit according to the reading result of the data in the normal storage array comprises the following steps:

In some embodiments, determining whether the failed address correctly maps to the redundant address based on the read of the data in the normal storage array comprises:

when the reading result shows that a first repair unit with a reading value of second data exists in the normal storage array, determining whether the fault address is correctly mapped to the redundant address according to whether the repair address corresponding to the first repair unit is identical to the fault address;

And when the reading result shows that the memory cell with the reading value of the second data does not exist in the normal memory array, determining that the mapping relation between the fuse address and the redundant address is wrong.

In some embodiments of the present invention, in some embodiments,

according to whether the repair address corresponding to the first repair unit is the same as the fault address, determining whether the fault address is correctly mapped to the redundant address includes:

In some embodiments, the first failed cell is a memory row and/or a memory column in a normal memory array.

In some embodiments, the normal storage array includes a plurality of failed cells therein, the method further comprising:

In some embodiments, obtaining the first faulty unit includes:

any one of the at least one faulty unit is selected as the first faulty unit.

The memory provided with the method for testing the application memory according to the embodiments of the present disclosure is similar to the memory in the above embodiments, and for technical features that are not fully disclosed in the embodiments of the present disclosure, reference is made to the above embodiments for understanding, and details are not repeated here.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for testing a memory, the memory comprising a normal memory array and a redundant memory array, comprising:

2. The method of testing of claim 1, wherein prior to writing the first data in the normal storage array of the memory, the method further comprises:

3. The method according to claim 2, wherein determining whether the failed address is correctly mapped to the redundant address based on a read result of data in the normal storage array, comprises:

4. A test method according to claim 3, wherein said determining whether said failed address is correctly mapped to said redundant address based on whether said repair address corresponding to said first repair unit is the same as said failed address comprises:

5. The method of claim 1, wherein the first failed cell is a memory row and/or a memory column in the normal memory array.

6. The method of testing of claim 5, wherein the normal storage array includes a plurality of failed cells therein, the method further comprising:

7. The method of testing of claim 2, wherein the obtaining the first faulty unit comprises:

Any one of the at least one faulty unit is selected as the first faulty unit.

8. A memory, comprising:

repair logic test circuitry, coupled to the memory array, configured to:

9. The memory of claim 8, further comprising an OTP array;

10. A memory test system, the system comprising: at least one memory and a test device connected to the at least one memory; wherein,,

the memory comprises a normal memory array and a redundant memory array;

the test device is configured to: