CN116401976A - A small chip-oriented VLSI standard cell layout method and related equipment - Google Patents

Abstract

The invention provides a VLSI standard cell layout method and related equipment for a small chip, comprising the following steps: step 1, obtaining a netlist of a target circuit diagram, process library information and layout constraint information; step 2, expressing the netlist as a hypergraph model, and dividing the hypergraph model according to connectivity of the hypergraph model to obtain a division result; step 3, according to the process library information and the layout constraint information, taking the half-cycle length of the bare chip as an optimization target, and carrying out global layout on the division result on the bare chip to obtain a standard unit layout result; step 4, carrying out layout on the interconnection terminals on the basis of the standard cell layout result to obtain a layout result of the target circuit diagram on the bare chip; compared with the prior art, the method improves the qualification rate of processing the large chip, reduces the complexity of design and accelerates the manufacturing period of the chip.

Description

A small chip-oriented VLSI standard cell layout method and related equipment

technical field

The invention relates to the technical field of integrated circuit layout, in particular to a small chip-oriented VLSI standard cell layout method.

Background technique

In the current VLSI (Very Large Scale Integration, VLSI) layout, with the continuous development of science and technology, the scale of integrated circuits continues to increase, and advanced technology continues to advance, making Moore's law gradually invalid, and the chip's The layout problem is an NP-hard problem. Layout is a crucial process of physical design. The quality of the layout result will directly affect the performance of the entire chip. With the rapid increase of the number of standard cells on a chip, it brings great challenges to the layout design of the chip. Therefore, it is very important to find a new and efficient circuit layout algorithm.

In the post-Moore era, in order to continue Moore's Law, chiplet technology came into being. A chiplet is a tiny integrated circuit IC that contains a well-defined subset of functions. It's designed to be combined with other chiplets on an interposer in a single package, and a set of chiplets can be realized by mash-ups into "Lego-like" components. Chiplet technology is a new chip design method after the system-on-chip (SoC) integration has developed to a certain extent. It divides the SoC into smaller die (Die), and then divides these modular small Chips are interconnected, and new packaging technology is used to package small chips with different functions and different processes together to form a heterogeneous integrated chip.

However, in the existing three-dimensional layout of integrated circuits, a rough three-dimensional layout result is obtained by first dividing the layers as a whole, and then two-dimensional layout, legalization, and detailed layout are performed to obtain the overall layout result. In the layout process, the traditional three-dimensional layout has no way to apply different processes to each layer, and at the same time, it does not optimize the number of interconnection lines between layers.

Contents of the invention

The invention provides a small-chip-oriented VLSI standard unit layout method and related equipment, the purpose of which is to improve the qualified rate of large-scale chip processing.

In order to achieve the above object, the present invention provides a VLSI standard cell layout method for small chips, including:

Step 1, obtaining the netlist, process library information and layout constraint information of the target circuit diagram;

Step 2, representing the netlist as a hypergraph model, dividing the hypergraph model according to the connectivity of the hypergraph model, and obtaining the division result;

Step 3, according to the process library information and layout constraint information, with the half-circular line length of the die as the optimization target, perform global layout on the division results on the die to obtain the standard cell layout result;

Step 4, lay out the interconnect terminals on the basis of the layout results of the standard cells, and obtain the layout results of the target circuit diagram on the bare chip.

Further, step 2 includes:

Express the netlist as a hypergraph model H={V, E};

Among them, V={v ₁ ,v ₂ ,...,v _n } represents the set of standard cells, E={e ₁ ,e ₂ ,...,e _n } represents the set of line nets;

Detect the connectivity of the hypergraph model H, and divide the hypergraph model H into a plurality of fully connected first sub-hypergraph models H _i according to the connectivity;

According to the number of nodes of the first sub-hypergraph model H _i , use the formula k=min(2+log ₂ |V|, α) to divide each first sub-hypergraph model H _i respectively to obtain k block division results;

Among them, α is a hyperparameter, α=22.

Further, before step 3, it also includes:

Aggregate all the standard units in each division result to obtain multiple aggregation results, and calculate the sum of the areas of the standard units in each aggregation result;

In each aggregation result, remove the wire net connected with only one node and deduplicate all the same wire nets to obtain the deduplicated aggregation result;

In the aggregated result after deduplication, weights are added to the line network to obtain the second sub-hypergraph model H _j with k nodes.

Further, before step 3, it also includes judging the validity of the second sub-hypergraph model:

Enumerate all the solutions S of the second sub-hypergraph model, and for each solution, calculate the sum of the area consumed by the bare chip under the solution S, and determine whether the sum of the areas exceeds the maximum usable area;

If the sum of the areas is greater than the maximum usable area, it is determined that the second sub-hypergraph model is illegal;

If the sum of the areas is less than or equal to the maximum usable area, it is determined that the second sub-hypergraph model is legal, and the legal second sub-hypergraph model is taken as the division result.

Further, the calculation of the sum A(S,d) of the area consumed by the die d under the solution S is:

COSt_d表示已使用面积，a_d,j表示标准单元在裸片上所占的面积，d_j表示所在裸片。in,

COSt _d represents the used area, a _d,j represents the area occupied by the standard cell on the die, and d _j represents the die where it is located.

Further, step 3 includes:

For the pin p connected to the net e, p=1,2,...,n;

For the interconnection net e, the area enclosed by all the pins on the die d is recorded as B _{d, e} , then the coordinates of the area B _{d, e} are:

The half-circle length HPWL(m,e) of the wire net e on the die is:

HPWL(m,e)=yur _d,e +xur _d,e -xll _d,e -yll _d,e

Then the total half-circle length HPWL(m) on the die d is:

Among them, (x _p , y _p ) is the coordinates of pin p, d _p is the die where pin p is located, and (xll _{d, e} , yll _{d, e} ) is the coordinates of the lower left corner of area B _{d, e} , (xur _{d, e} , yur _{d, e} ) are the coordinates of the upper right corner of area B _{d, e} ;

Taking the total half-cycle line length HPWL(m) on the die d as the optimization target, use the placer to perform global layout on the division results on the die, and obtain the standard cell layout results.

Further, before laying out interconnection terminals based on the layout results of standard cells, it also includes:

It is preset that the interval between any two interconnection terminals and the die boundary satisfies the interval constraint, then the interval constraint of the x-axis coordinates of each interconnection terminal is:

Then the interval constraints of the y-axis coordinates of each interconnection terminal are:

Among them, l represents the side length of the interconnection terminal, pitch represents the given interval, (x _e , y _e ) represents the center coordinates of the interconnection terminal t _e , (x, y) represents the upper right coordinates of the layout area, a and b represent Subscripts for different interconnecting nets.

The present invention also provides a VLSI standard cell layout device for small chips, comprising:

The obtaining module is used to obtain the netlist, process library, process library information and layout constraint information of the target circuit diagram;

The division module is used to represent the netlist as a hypergraph model, and divides the hypergraph model according to the connectivity of the hypergraph model to obtain a division result;

The standard cell layout module is used to perform global layout on the division results on the bare chip according to the process library information and layout constraint information, with the half-circular line length of the bare chip as the optimization target, and obtain the standard cell layout result;

The interconnection terminal layout module is used for laying out the interconnection terminals on the basis of the layout result of the standard cell, and obtaining the layout result of the target circuit diagram on the bare chip.

The present invention also provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, a chiplet-oriented VLSI standard cell layout method is realized.

The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the computer program, it realizes a chiplet-oriented VLSI standard cell layout method.

Said scheme of the present invention has following beneficial effect:

The present invention acquires the netlist of the target circuit diagram, process library information and layout constraint information; expresses the netlist as a hypergraph model, divides the hypergraph model according to the connectivity of the hypergraph model, and obtains the division result; according to the process library information and Layout constraint information, with the half-circumferential line length of the die as the optimization target, perform global layout on the division results on the die to obtain the standard cell layout results; based on the standard cell layout results, perform layout on the interconnection terminals to obtain the target circuit diagram The layout results on the bare chip; compared with the existing technology, it improves the pass rate of large chips, reduces the complexity of the design, and speeds up the manufacturing cycle of the chip; at the same time, it can be manufactured with different processes, materials and nodes. Each is optimized for its specific function.

Other beneficial effects of the present invention will be described in detail in the following specific embodiments.

Description of drawings

Fig. 1 is the schematic flow chart of the embodiment of the present invention;

FIG. 2 is a schematic diagram of an optimal layout area of a wire net in an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments. Apparently, the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation, therefore, should not be construed as limiting the invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a locking connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as there is no conflict with each other.

Aiming at the existing problems, the invention provides a chip-oriented VLSI standard cell layout method and related equipment.

As shown in FIG. 1, the embodiment of the present invention provides a VLSI standard cell layout method for small chips, including:

Step 1, obtaining the netlist, process library information and layout constraint information of the target circuit diagram;

Step 2, representing the netlist as a hypergraph model, dividing the hypergraph model according to the connectivity of the hypergraph model, and obtaining the division result;

Step 3, according to the process library information and layout constraint information, with the half-circular line length of the die as the optimization target, perform global layout on the division results on the die to obtain the standard cell layout result;

Step 4, lay out the interconnect terminals on the basis of the layout result of the standard cell, and obtain the layout result of the target circuit diagram on the bare chip.

Specifically, the netlist represents the connection relationship between standard cells, the process library represents the length, width, and pin coordinates of standard cells, and the die includes the row height, row width, row number, size, and maximum area usage of the die. The rate and the process used, the interconnection terminals include the size and minimum spacing of the interconnection terminals.

Specifically, step 2 includes:

Express the netlist as a hypergraph model H={V, E};

Among them, V={v ₁ ,v ₂ ,...,v _n } represents the set of standard cells, E={e ₁ ,e ₂ ,...,e _n } represents the set of line nets;

Detect the connectivity of the hypergraph model H, and divide the hypergraph model H into multiple fully connected first sub-hypergraph models H _i ={V _i , E _i } according to the connectivity; the fully connected hypergraph model is defined as : Starting from any node, the hypergraph model of all nodes in the hypergraph model that can be traversed through breadth-first traversal;

According to the number of nodes |V _{i |} of the first sub-hypergraph model H _i , each first sub-hypergraph model H _i is divided into Carry out division to obtain k block division results;

Wherein, α is a hyperparameter. In the embodiment of the present invention, α=22. Increasing the value of α will lengthen the running time of the division process, and decreasing the value of α will reduce the quality of the division result.

Specifically, before step 3, it also includes:

Aggregate all standard units in each division result to obtain multiple aggregation results, and calculate the sum of the areas of standard units in each aggregation result under the two processes;

In each aggregation result, remove the wire net connected with only one node and deduplicate all the same wire nets to obtain the deduplicated aggregation result;

In the aggregated result after deduplication, weights are added to the line network to obtain the second sub-hypergraph model H _j with k nodes.

Specifically, before step 3, it also includes judging the legality of the second sub-hypergraph model:

Enumerate all the solutions S of the second sub-hypergraph model, and for each solution, calculate the sum of the area consumed by the bare chip under the solution S, and determine whether the sum of the areas exceeds the maximum usable area;

Specifically, the sum A(S,d) of the area consumed by the die d under the solution S is calculated as:

COSt_d表示已使用面积，a_d,j表示标准单元在裸片上所占的面积，d_j表示节点所在裸片。where, S∈[ ^0,2k -1],

COSt _d represents the used area, a _d,j represents the area occupied by standard cells on the die, and d _j represents the die where the node is located.

If the sum of the areas is less than or equal to the maximum usable area, it is determined that the second sub-hypergraph model is legal, and the legal second sub-hypergraph model is taken as the division result.

In the embodiment of the present invention, when A(S,d)≤a _d *util _d , the number of interconnection nets Cuts is calculated, and the interconnection net is defined as the net connecting two bare chips. For the second sub-super The network e _j in the graph model, j=1, 2,..., n, write w _j as the weight of the network e _j , then the number of interconnected network is:

表示线网e_j连接的两个不同的标准单元，即当线网e_j为互连线网时β(e_j)为1，否则为0；in,

Indicates two different standard units connected by the net e _j , that is, when the net e _j is an interconnected net, β(e _j ) is 1, otherwise it is 0;

If the sum of the areas is greater than the maximum usable area, it is judged that the second subhypergraph model is illegal; that is, when A(S,d)>a _d *util _d , the solution is skipped.

Record the minimum number of interconnection lines and its corresponding solution S, map the solution S back to the hypergraph model H, and take out the next second sub-hypergraph model H _j+1 , if all the enumerated solutions do not satisfy A When (S,d)≤a _d *util _d , re-aggregate.

Specifically, step 3 includes:

For the pin p connected to the net e, p=1,2,...,n;

For the interconnection net e, the area enclosed by all the pins on the die d is recorded as B _{d, e} , then the coordinates of the area B _{d, e} are:

The half-circle length HPWL(m,e) of the wire net e on the die is:

HPWL(m,e)=yur _d,e +xur _d,e -xll _d,e -yll _d,e

Then the half-circle length HPWL(m) on the die d is:

Among them, (x _p , y _p ) is the coordinates of pin p, d _p is the die where pin p is located, and (xll _{d, e} , yll _{d, e} ) is the coordinates of the lower left corner of area B _{d, e} , (xur _{d, e} , yur _{d, e} ) are the coordinates of the upper right corner of area B _{d, e} ;

Taking the half-peripheral line length HPWL(m) on the die d as the optimization target, use the placer to perform global layout on the division results on the die, and use ntuplace3 to perform legalization and detailed layout on the global layout results to obtain the standard cell layout results.

Specifically, before laying out interconnection terminals based on the layout results of standard cells, it also includes:

In the embodiment of the present invention, each interconnection network e needs to be assigned an interconnection terminal t _e , through which the inter-die communication and interconnection are performed, and (x _e , y _e ) are the interconnection terminals The center coordinates of t _e , calculate the change value of the half-circle length of the x-axis on the die d after adding the interconnection terminal t _e :

After adding the interconnect terminal t _e , the half-circle length change value of the y-axis on the die is the same as the x-axis. When two dies are considered at the same time, the half-circle length change value of the wire network e is:

For the interconnection net e, the area surrounded by all the pins on the die d is recorded as B _d,e , when the interconnection terminal t _e is in the optimal layout area, the half-circle length change value of the net e is the smallest, the optimal layout area is shown in Figure 2, and the coordinates of the optimal layout area are:

In the layout of interconnect terminals, it is necessary to preset the interval between any two interconnect terminals and the boundary of the die to meet the interval constraint. The interval constraint is defined as the interval between any two interconnect terminals or between any terminal and the layout boundary. The interval must be given. For the layout area R, its size is the same as the size of the die, and its lower left coordinates are regarded as the coordinate origin (0, 0) and the upper right coordinates are (x, y). Each terminal is a square of the same size , record its side length as l, then the interval constraints of the x-axis coordinates of each interconnection terminal are:

Then the interval constraints of the y-axis coordinates of each interconnection terminal are:

Among them, l represents the side length of the interconnection terminal, pitch represents the given interval, (x _e , y _e ) represents the center coordinates of the interconnection terminal t _e , (x, y) represents the upper right coordinates of the layout area, a and b represent Subscripts for different interconnection nets.

In the embodiment of the present invention, the layout of the interconnection terminal satisfies the interval constraint and at the same time optimizes the semicircular line length change value. Specific steps are as follows:

In the first step, the placement area is initialized as a grid map with m*n grids, each grid is a square with a side length of 1+pitch, which allows each grid to place exactly one interconnection terminal, m and n are calculated according to the following formula:

For any grid b _i,j , i=1,2,...,m; j=1,2,...,n; write w _i,j as the congestion weight of grid b, (x _i,j ,y _{i ,j} ) is the center coordinate of grid b _i,j , then the coordinates of grid b _i,j are:

If the number of interconnection terminals is greater than m*n, the layout area R cannot place all the interconnection terminals, there is no legal solution, and the algorithm exits.

In the second step, when the coordinates (x _i,j , y _i,j ) of the grid b _i,j are within the optimal layout area of the interconnection network e, the congestion weight is added to the weight w of the interconnection network e _e . Traverse all the interconnection network e, calculate the optimal layout area of the interconnection network e, and increase the congestion weight of all grids whose center coordinates are in the optimal layout area w _e , if there is no grid in the optimal layout area , find the grid whose coordinates are closest to the optimal layout area, and increase its congestion weight by w _e .

The third step is to traverse all the interconnection network e, and place its interconnection terminal t _e in the unmarked grid b _{i,j with the smallest congestion weight in the optimal layout area,} and the coordinates of t _e are equal to grid b _i, The coordinates of _j , labeled grid b _i,j , indicate that interconnection terminals have been placed on this grid. If all the grids in the optimal layout area are marked, use the breadth-first traversal algorithm to gradually traverse the nearest grids outside the optimal layout area, and then find the unmarked grid with the smallest congestion weight, if all the grids are still marked , continue to search outward until the interconnection terminal t _e is placed on the grid, mark the grid, and exit the breadth-first traversal; complete the optimization of the change value of the total half-cycle line length.

The embodiment of the present invention acquires the netlist of the target circuit diagram, process library information, and layout constraint information; expresses the netlist as a hypergraph model, and divides the hypergraph model according to the connectivity of the hypergraph model to obtain the division result; according to the process library Information and layout constraint information, with the half-peripheral line length of the die as the optimization target, the global layout of the division results is performed on the die to obtain the standard cell layout results; the interconnection terminals are laid out on the basis of the standard cell layout results to obtain the target The layout result of the circuit diagram on the bare chip; compared with the existing technology, it improves the pass rate of large chips, reduces the complexity of the design, and speeds up the manufacturing cycle of the chip; at the same time, it can be manufactured with different processes, materials and nodes , each optimized for its specific functionality.

The embodiment of the present invention also provides a small chip-oriented VLSI standard cell layout device, including:

The obtaining module is used to obtain the netlist, process library, process library information and layout constraint information of the target circuit diagram;

The division module is used to represent the netlist as a hypergraph model, and divides the hypergraph model according to the connectivity of the hypergraph model to obtain a division result;

The standard cell layout module is used to perform global layout on the division results on the bare chip according to the process library information and layout constraint information, with the half-circular line length of the bare chip as the optimization target, and obtain the standard cell layout result;

The interconnection terminal layout module is used for laying out the interconnection terminals on the basis of the layout result of the standard cell, and obtaining the layout result of the target circuit diagram on the bare chip.

It should be noted that the information interaction and execution process between the above-mentioned devices/units are based on the same concept as the method embodiment in the embodiment of the present invention, and its specific functions and technical effects can be found in the method implementation The example part is not repeated here.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used for illustration. In practical applications, the above-mentioned functions can be assigned to different functional units, Completion of modules means that the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit, and the above-mentioned integrated units may adopt hardware It can also be implemented in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present invention. For the specific working processes of the units and modules in the above system, reference may be made to the corresponding processes in the aforementioned method embodiments, and details will not be repeated here.

The embodiment of the present invention also provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, a chiplet-oriented VLSI standard cell layout method is implemented.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the embodiment of the present invention implements all or part of the processes in the methods of the above embodiments, which can be completed by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can realize the steps of the above-mentioned various method embodiments. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying computer program codes to a construction device/terminal device, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. Such as U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunication signals under legislation and patent practice.

The embodiment of the present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the computer program, it implements a chiplet-oriented VLSI standard cell layout method.

It should be noted that the terminal device may be a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC, Ultra-mobile Personal Computer), a netbook, a personal digital assistant (PDA, PersonalDigital Assistant) and other terminal devices, for example, the terminal The device can be a station (ST, STION) in the WLAN, and can be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP, Session Initiation Protocol) phone, a wireless local loop (WLL, Wireless Local Loop) station, a personal digital processing ( PDA, Personal Digital Assistant) device, handheld device with wireless communication function, computing device or other processing device connected to a wireless modem, computer, laptop computer, handheld communication device, handheld computing device, satellite wireless device, etc. The embodiment of the present invention does not impose any limitation on the specific type of the terminal device.

The so-called processor can be a central processing unit (CPU, Central Processing Unit), and the processor can also be other general-purpose processors, a digital signal processor (DSP, Digital Signal Processor), an application specific integrated circuit (ASIC, Application Specific Integrated Circuit ), off-the-shelf programmable gate array (FPGA, Field-Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.

In some embodiments, the storage may be an internal storage unit of the terminal device, such as a hard disk or memory of the terminal device. In some other embodiments, the memory may also be an external storage device of the terminal device, such as a plug-in hard disk equipped on the terminal device, a smart memory card (SMC, Smart Media Card), a secure digital (SD, Secure Digital) card, flash memory card (Flash Card), etc. Further, the memory may also include both an internal storage unit of the terminal device and an external storage device. The memory is used to store operating system, application program, boot loader (BootLoader), data and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

It should be noted that the information interaction and execution process between the above-mentioned devices/units are based on the same concept as the method embodiment in the embodiment of the present invention, and its specific functions and technical effects can be found in the method implementation The example part is not repeated here.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (10)

1. A method of chiplet-oriented VLSI standard cell layout comprising:

step 1, obtaining a netlist of a target circuit diagram, process library information and layout constraint information;

step 2, the netlist is expressed as a hypergraph model, and the hypergraph model is divided according to connectivity of the hypergraph model to obtain a division result;

step 3, according to the process library information and the layout constraint information, taking the half-cycle length of the bare chip as an optimization target, and performing global layout on the dividing result on the bare chip to obtain a standard unit layout result;

and 4, carrying out layout on the interconnection terminals on the basis of the standard cell layout result to obtain the layout result of the target circuit diagram on the bare chip.

2. The method of claim 1, wherein step 2 comprises:

representing the netlist as a hypergraph model h= { V, E };

wherein v= { V ₁ ,v ₂ ,...,v _n The symbol } represents a set of standard cells, e= { E ₁ ,e ₂ ,...,e _n -representing a collection of nets;

detecting connectivity of the hypergraph model H, and dividing the hypergraph model H into a plurality of completely communicated first sub-hypergraph models H according to the connectivity _i ；

According to the first sub hypergraph model H _i Using the formula k=min (2+log ₂ V, α) will each of the first sub hypergraph models H, respectively _i Dividing to obtain k block dividing results;

where α is a super parameter, α=22.

3. The method of claim 2, further comprising, prior to step 3:

aggregating all standard units in each block of the dividing result to obtain a plurality of aggregation results, and calculating the area sum of the standard units in each aggregation result;

in each aggregation result, removing the wire net connected with only one node and carrying out de-duplication on all the same wire nets to obtain an aggregation result after de-duplication;

in the aggregate result after the duplication removal, the weight is added to the network to obtain a second sub hypergraph model H with the node number of k _j 。

4. The method of claim 3, further comprising, prior to said step 3, determining the legitimacy of said second sub-hypergraph model:

enumerating all solutions S of the second sub hypergraph model, calculating the sum of the areas consumed by the bare chips under the solutions S for each solution, and judging whether the sum of the areas exceeds the maximum usable area;

if the sum of the areas is larger than the maximum usable area, judging that the second sub hypergraph model is illegal;

and if the sum of the areas is smaller than or equal to the maximum usable area, judging that the second sub-hypergraph model is legal, and taking the legal second sub-hypergraph model as a division result.

5. The chiplet-oriented VLSI standard cell layout method of claim 4 wherein calculating the sum of areas consumed by die d at solution S, a (S, d), is:

wherein,,

COSt _d indicating the area used, a _d,j Representing the area occupied by a standard cell on a die, d _j Indicating the die on which it is located.

6. The method of claim 5, wherein the step 3 comprises:

for pin p of net e connection, p=1, 2, …, n;

for interconnection net e, the area around all pins on die d is denoted as B _d,e Region B _d,e The coordinates of (2) are:

the half-cycle length HPWL (m, e) of net e on the die is:

HPWL(m,e)＝yur _d,e +xur _d,e -xll _d,e -yll _d,e

the total half-perimeter length HPWL (m) on die d is:

wherein, (x) _p ，y _p ) Is the coordinate of pin p, d _p For the die where pin p is located, note (xll _d,e ，yll _d,e ) Is region B _d,e Lower left corner coordinates (xur) _d,e ，yur _d,e ) Is region B _d,e Is the upper right corner coordinates of (2);

and carrying out global layout on the division result on the bare chip by using a layout device by taking the total half-cycle length HPWL (m) on the bare chip d as an optimization target to obtain a standard cell layout result.

7. The chiplet-oriented VLSI standard cell layout method of claim 6, further comprising, prior to laying out the interconnect terminals based on layout results of the standard cells:

presetting that the interval between any two interconnection terminals and the boundary of the bare chip meets the interval constraint, wherein the interval constraint of the x-axis coordinate of each interconnection terminal is as follows:

the spacing constraint for the y-axis coordinate of each interconnect terminal is:

where l represents the side length of the interconnect terminal, pitch represents a given spacing, (x) _e ,y _e ) Representing an interconnection terminal t _e (x, y) represents the upper right coordinates of the layout area and a, b represent the subscripts of the different interconnection nets.

8. A chiplet-oriented VLSI standard cell layout apparatus comprising:

the acquisition module is used for acquiring the netlist of the target circuit diagram, the process library information and the layout constraint information;

the partitioning module is used for representing the netlist as a hypergraph model, and partitioning the hypergraph model according to connectivity of the hypergraph model to obtain a partitioning result;

the standard cell layout module is used for carrying out global layout on the dividing result on the bare chip by taking the half-cycle length of the bare chip as an optimization target according to the process library information and the layout constraint information to obtain a standard cell layout result;

and the interconnection terminal layout module is used for carrying out layout on the interconnection terminals on the basis of the standard cell layout result to obtain the layout result of the target circuit diagram on the bare chip.

9. A computer readable storage medium storing a computer program, which when executed by a processor implements the chiplet-oriented VLSI standard cell layout method of any of claims 1-7.

10. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the chiplet-oriented VLSI standard cell layout method of any of claims 1-7 when the computer program is executed.

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