CN116404002B - Method for manufacturing semiconductor chip - Google Patents
Method for manufacturing semiconductor chip Download PDFInfo
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- CN116404002B CN116404002B CN202310383244.1A CN202310383244A CN116404002B CN 116404002 B CN116404002 B CN 116404002B CN 202310383244 A CN202310383244 A CN 202310383244A CN 116404002 B CN116404002 B CN 116404002B
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- 238000000034 method Methods 0.000 title claims abstract description 101
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 74
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 30
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 238
- 229920005591 polysilicon Polymers 0.000 claims description 238
- 238000005468 ion implantation Methods 0.000 claims description 76
- 239000010410 layer Substances 0.000 claims description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000002344 surface layer Substances 0.000 claims description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 11
- 238000007517 polishing process Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 238000001259 photo etching Methods 0.000 abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 19
- 230000000694 effects Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 241001391944 Commicarpus scandens Species 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910001423 beryllium ion Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/921—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The application discloses a manufacturing method of a semiconductor chip, which comprises the following steps: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer, and the hard mask dielectric layer comprises first silicon oxide and first silicon nitride; removing the hard mask dielectric layer of the first set area by adopting photoetching and etching processes; forming a first groove in the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting an etching process; growing second silicon dioxide in the first groove by adopting a thermal oxidation process; removing the first silicon nitride and growing second silicon nitride; removing the second silicon nitride and the first silicon oxide in the second set area by adopting photoetching and etching processes; the second setting area is an area of the preset groove type semiconductor chip unit cell. The application has the advantages of eliminating the step height difference and the like.
Description
Technical Field
The present application relates to the field of chip manufacturing, and in particular, to a method for manufacturing a semiconductor chip.
Background
The electrostatic discharge phenomenon exists in various links such as packaging and using of the semiconductor chip, and is easy to cause chip damage, so that the electrostatic protection circuit is required to be designed in the semiconductor chip or at the periphery of the semiconductor chip.
The trench semiconductor chip is one of semiconductor chips, including trench MOSFET, trench IGBT and other chips, and the gate oxide layers of these semiconductor chips are very thin (only 10-100 nm), so that they are very easy to break down by electrostatic discharge. In a specific process method, a thicker insulating layer (usually silicon oxide) is needed to isolate a cell area of the trench type semiconductor chip from the diode in the chip, and the diode is usually a polysilicon diode, namely the polysilicon diode is arranged on the surface of the insulating layer, so that a larger step height difference exists between an electrostatic protection circuit area and the cell area in a process structure in the chip, the step height difference increases the difficulty of a later stage process, and the integration level of the chip is reduced.
Aiming at the problem of step height difference caused by the integrated electrostatic protection circuit in the chip, the technical proposal 201610768814.9 discloses a technical proposal which adopts a local oxidation technology to grow a field oxide layer on the surface of silicon and then manufacture a polysilicon diode on the surface of the field oxide layer, and the technical proposal can understand that a part of silicon is consumed in the process of growing the field oxide layer by the local oxidation technology, namely the bottom of the field oxide layer is lower than the silicon plane, but the top of the field oxide layer manufactured by the method is still obviously higher than the silicon plane, and the top of the polysilicon grown on the surface of the field oxide layer is far higher than the silicon plane, so the technical proposal does not fundamentally solve the problem of step height difference (but only slightly reduces the step height difference and attempts to solve other problems disclosed by the inventor), the difficulty of the later-stage technology of the method is still very large, and the integration level of the chip is still very low.
It is known to those skilled in the art that in order to achieve the effect of rapidly discharging the electrostatic pulse energy, the polysilicon diode needs to be made into a zener diode, and more commonly, one side of the PN junction is heavily doped and the other side is lightly doped, for example, heavily doped P-type polysilicon and lightly doped N-type polysilicon, or heavily doped N-type polysilicon and lightly doped P-type polysilicon form a PN junction, and such a PN junction forms the polysilicon diode; on the other hand, the polysilicon gate of the trench-type semiconductor chip is necessarily heavily doped polysilicon, the larger the doping concentration is, the better (the smaller the parasitic resistance of the gate is in this way), and the doping type is the same as the channel type of the chip, namely, the polysilicon gate of the N-channel semiconductor chip is heavily doped N-type polysilicon, and the polysilicon gate of the P-channel semiconductor chip is heavily doped P-type polysilicon. Thus, at least three different doping types (or different doping concentrations) of polysilicon are present inside the chip. In order to realize the three kinds of polysilicon with different doping types (or different doping concentrations), the most conceivable method is to use two layers of polysilicon to respectively manufacture a polysilicon gate and a polysilicon diode, but this method has some technical hidden trouble in practical process, so in the traditional method, the simpler method is to use one layer of polysilicon to realize both the polysilicon gate and the polysilicon diode, but there is an unavoidable contradiction in this method: in order to ensure the filling effect of the polysilicon gate in the trench, the deposition thickness of the polysilicon is required to be increased as much as possible in the process, and in order to improve the electrostatic protection capability of the polysilicon diode, the deposition thickness of the polysilicon is required to be increased as much as possible in the process, so that the PN junction area of the polysilicon diode is increased, but the step height difference inside the chip is remarkably increased by the polysilicon with larger thickness, the problems of the later stage process difficulty and the integration level are generated, but if the polysilicon gate and the polysilicon diode are manufactured by adopting relatively thin polysilicon, on one hand, the electrostatic protection capability of the polysilicon diode is greatly reduced, and on the other hand, the filling effect of the polysilicon in the trench is poor, and a series of risks such as potential polysilicon filling holes, polysilicon etching holes, contact hole etching punching and the like are generated.
The scheme provides a new manufacturing method for solving the problems of step height difference in the process of integrating an electrostatic protection circuit inside a groove type semiconductor chip and the process contradiction and problems in the process method for manufacturing a polysilicon gate and a polysilicon diode by only adopting one layer of polysilicon in the prior art.
Disclosure of Invention
The application provides a manufacturing method of a semiconductor chip, which has the advantages of eliminating the step height difference, reducing the process difficulty and greatly improving the integration level of the chip, and solves the problems of the prior art that the step height difference inside the chip is increased, the back-end process difficulty and the integration level are improved.
The manufacturing method of the semiconductor chip provided by the embodiment of the application comprises the following steps:
growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer, and the hard mask dielectric layer comprises first silicon oxide and first silicon nitride;
removing the hard mask dielectric layer of the first set area by adopting photoetching and etching processes;
forming a first groove in the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting an etching process;
growing second silicon dioxide in the first groove by adopting a thermal oxidation process;
removing the first silicon nitride and growing second silicon nitride;
removing the second silicon nitride and the first silicon oxide in the second set area by adopting photoetching and etching processes; the second setting area is an area of a preset groove type semiconductor chip cell;
forming a second groove in the semiconductor substrate by using the second silicon nitride as a barrier layer and adopting an etching process;
removing the second silicon nitride; growing third silicon oxide with the thickness of 10-100 nanometers in the second groove by adopting a thermal oxidation process;
depositing undoped polysilicon;
performing first ion implantation doping on the polysilicon to form first doped polysilicon on the surface layer of the polysilicon;
performing second ion implantation doping on the polysilicon in the third set area by adopting photoetching and ion implantation processes, and forming second doped polysilicon on the surface layer of the polysilicon; the third setting area comprises a second setting area, and the third setting area is not overlapped with the first setting area;
high-temperature annealing, wherein dopants in the first doped polysilicon and the second doped polysilicon on the surface layer of the polysilicon diffuse to the bottom of the polysilicon, and the polysilicon is diffused thoroughly to form the first doped polysilicon and the second doped polysilicon which are uniformly distributed from the surface layer to the bottom layer;
the polysilicon in the first set region, namely the first groove, is first doped polysilicon, and the polysilicon in the second set region, namely the second groove, is second doped polysilicon;
removing the first doped polysilicon and the second doped polysilicon which are higher than the upper surface of the first silicon oxide by adopting a chemical mechanical polishing process, and reserving the first doped polysilicon in the first groove and the second doped polysilicon in the second groove;
forming a body region by adopting an ion implantation and annealing process;
forming a source region by adopting photoetching, ion implantation and annealing processes, and synchronously forming third doped polysilicon in a fourth set region, wherein the fourth set region is positioned in the first set region;
forming a first contact hole, a second contact hole and a third contact hole by adopting photoetching and etching processes, wherein the first contact hole is used for leading out a source region of a groove type semiconductor chip, and the second contact hole and the third contact hole are respectively used for leading out two ends of a polysilicon diode which is an electrostatic protection circuit;
and a thermal oxidation process is adopted to grow second silicon dioxide in the first groove, wherein the thickness of the second silicon dioxide is 150-600 nanometers, and is far greater than that of the third silicon oxide and smaller than the depth of the first groove.
Preferably, the thickness of the first silicon oxide is 20-30 nanometers, and the thickness of the first silicon nitride is 200-400 nanometers.
Preferably, the hard mask dielectric layer is used as a barrier layer, and an etching process is adopted to form a first groove in the semiconductor substrate, wherein the depth of the first groove is 600-2000 nanometers, the width of the first groove is 150-200 micrometers, and the width of the first groove is larger than the etching width of the hard mask dielectric layer.
Preferably, the thickness of the polysilicon is greater than the step height difference from the upper surface of the second silicon dioxide to the silicon plane, the first ion implantation doping is performed on the polysilicon, the first doped polysilicon is formed on the surface layer of the polysilicon, the second ion implantation doping is performed on the polysilicon of the third set region by adopting the photoetching and ion implantation process, and the second doped polysilicon is formed on the surface layer of the polysilicon.
Preferably, the first ion implantation is doped with boron, the concentration is 5E 13-2E 14/CM 2 The first doped polysilicon is P-type, the second ion implantation is doped with phosphorus, and the concentration is 4E 15-1E 16/CM 2 The formed second doped polysilicon is of N type; or alternatively
The first ion implantation is doped with phosphorus with the concentration of 5E 13-2E 14/CM 2 The first doped polysilicon is N-type, the second ion implantation is doped with boron, and the concentration is 4E 15-1E 16/CM 2 The second doped polysilicon is formed as a P type;
the first doped polysilicon in the first groove is lightly doped polysilicon, and the second doped polysilicon in the second groove is heavily doped polysilicon.
Preferably, a chemical mechanical polishing process is adopted to remove the first doped polysilicon and the second doped polysilicon higher than the upper surface of the first silicon oxide, the first doped polysilicon in the first groove and the second doped polysilicon in the second groove are reserved, and the unnecessary polysilicon is polished down from top to bottom by the chemical mechanical polishing process and finally stays on the upper surface of the first silicon oxide; the thickness of the first doped polysilicon in the first groove is equal to the difference between the step height of the upper surface of the second silicon dioxide and the silicon plane plus the thickness of the first silicon oxide, wherein the difference between the step height of the upper surface of the first silicon oxide and the silicon plane is negligible compared with the thickness of the first silicon oxide, and the top of the first doped polysilicon is basically flush with the silicon plane and is completely flush with the upper surface of the first silicon oxide.
Preferably, the photolithography, ion implantation and annealing processes are adopted to form a source region, and third doped polysilicon is synchronously formed in a fourth set region, wherein the fourth set region is positioned in the first set region;
the doping type of the ion implantation doping is opposite to that of the first ion implantation doping, the doping type of the ion implantation doping is the same as that of the second ion implantation doping, and the doping concentration of the third ion implantation doping is far greater than that of the first ion implantation doping;
when the first ion implantation is doped with boron, the third ion implantation is doped with phosphorus or arsenic, and the concentration is 1E 15-8E 15/CM 2 The formed third doped polysilicon is of N type; or alternatively
When the first ion implantation is doped with phosphorus, the third ion implantation is doped with boron, and the concentration is 1E 15-8E 15/CM 2 The third doped polysilicon is formed as P-type.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
1. the polysilicon diode formed by the application is positioned in the groove, the top of the polysilicon diode is basically level with the silicon plane, the problem of step height difference is completely eliminated, the process difficulty is reduced, and the integration level of the chip can be greatly improved.
2. The application adopts only one layer of polysilicon, thus realizing the polysilicon gate and the polysilicon diode, and having lower cost, but no process contradiction point related to the thickness of polysilicon in the traditional method.
3. Because the application adopts only one layer of polysilicon to realize the polysilicon gate and the polysilicon diode, the doping type of the polysilicon gate can only be ion implantation doping, and therefore, the square resistance of the formed polysilicon gate is slightly larger than that of the polysilicon doped in situ (doped at the same time of deposition), and the polysilicon gate is more suitable for the application fields with not particularly strict requirements on parasitic resistance of the gate but rather strict requirements on cost.
4. From practice, the inventor repeatedly researches and demonstrates that all the process steps and process parameters are skillfully designed and matched, so that the process steps and the physical structure are buckled, and the effect that the traditional method cannot form is finally generated.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic structural diagram of step (1.1) of the present application;
FIG. 2 is a schematic structural diagram of the step (1.2) of the present application;
FIG. 3 is a schematic structural diagram of the step (1.3) of the present application;
FIG. 4 is a schematic structural diagram of the step (1.4) of the present application;
FIG. 5 is a schematic structural diagram of step (1.5) of the present application;
FIG. 6 is a schematic structural diagram of step (1.6) of the present application;
FIG. 7 is a schematic structural diagram of the step (1.7) of the present application;
FIG. 8 is a schematic structural diagram of step (1.8) of the present application;
FIG. 9 is a schematic diagram of the structure of the step (1.9) of the present application;
FIG. 10 is a schematic diagram of the structure of the step (1.10) of the present application;
FIG. 11 is a schematic structural diagram of step (1.11) of the present application;
FIG. 12 is a schematic diagram of the structure of step (1.12) of the present application;
FIG. 13 is a schematic diagram of the structure of step (1.13) of the present application;
FIG. 14 is a schematic diagram of the structure of step (1.14) of the present application;
FIG. 15 is a schematic diagram of the structure of step (1.15) of the present application;
FIG. 16 is a schematic diagram of the structure of step (1.16) of the present application;
FIG. 17 is a schematic diagram of the structure of step (1.17) of the present application;
FIGS. 18-20 are enlarged schematic views of the cross-sectional structure of an electrostatic protection circuit (polysilicon diode) integrated inside a chip made in accordance with the present application;
fig. 21 and 22 are schematic plan view structures of electrostatic protection circuits (polysilicon diodes) integrated inside a chip, which are fabricated according to the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
The application provides a novel manufacturing method for solving the problems of step height difference in the process of integrating an electrostatic protection circuit inside a groove type semiconductor chip and the technical problems in the process of respectively manufacturing a polysilicon gate and a polysilicon diode by adopting two layers of polysilicon in the prior art.
The application provides a method for manufacturing a semiconductor chip, which comprises the following steps:
(1.1) growing a hard mask dielectric layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate 1 and a lightly doped epitaxial layer 2, the hard mask dielectric layer comprising a first silicon oxide 3, a first silicon nitride 4; (please refer to FIG. 1)
(1.2) removing the hard mask dielectric layer of the first set area by adopting photoetching and etching processes; (please refer to FIG. 2)
It can be understood that the first setting area is an area where the electrostatic protection circuit is preset.
(1.3) forming a first trench 5 in the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting an etching process; (please refer to FIG. 3)
(1.4) growing a second silicon dioxide 6 in the first trench 5 using a thermal oxidation process; (please refer to FIG. 4)
(1.5) removing the first silicon nitride 4 and growing a second silicon nitride 7; (please refer to FIG. 5)
(1.6) removing the second silicon nitride 7 and the first silicon oxide 3 in the second set region by adopting photoetching and etching processes; (please refer to FIG. 6)
It can be understood that the second set region is a region of the preset trench type semiconductor chip cell.
(1.7) forming a second trench 8 in the semiconductor substrate by using the second silicon nitride 7 as a barrier layer and adopting an etching process; (please refer to FIG. 7)
(1.8) removing the second silicon nitride 7; (please refer to FIG. 8)
(1.9) growing a third silicon oxide 9, namely a gate oxide layer, with the thickness of 10-100 nanometers in the second groove 8 by adopting a thermal oxidation process; (please refer to FIG. 9)
(1.10) depositing undoped polysilicon 10; (please refer to FIG. 10)
(1.11) performing first ion implantation doping on the polysilicon 10 to form first doped polysilicon 10.1 on the surface layer of the polysilicon 10; (please refer to FIG. 11)
(1.12) performing second ion implantation doping on the polysilicon 10 in the third set region by adopting photoetching and ion implantation processes, and forming second doped polysilicon 10.2 on the surface layer of the polysilicon 10; (please refer to FIG. 12)
It will be appreciated that the third set area includes (includes) the second set area but does not overlap with the first set area.
(1.13) high-temperature annealing, wherein the dopants in the first doped polysilicon 10.1 and the second doped polysilicon 10.2 on the surface layer of the polysilicon 10 diffuse to the bottom of the polysilicon, and the polysilicon 10 is diffused thoroughly to form the first doped polysilicon 10.1 and the second doped polysilicon 10.2 which are uniformly distributed from the surface layer to the bottom layer; (please refer to FIG. 13)
As can be seen from the above, the polysilicon in the first set region, i.e., the first trench 5, is the first doped polysilicon 10.1, and the polysilicon in the second set region, i.e., the second trench 8, is the second doped polysilicon 10.2;
(1.14) removing the first doped polysilicon 10.1 and the second doped polysilicon 10.2 which are higher than the upper surface of the first silicon oxide 3 by adopting a chemical mechanical polishing process, and reserving the first doped polysilicon 10.1 in the first groove 5 and the second doped polysilicon 10.2 in the second groove 8; (please refer to FIG. 14)
It can be understood that the first doped polysilicon 10.1 is a predetermined electrostatic protection circuit region (i.e., polysilicon diode region), the second doped polysilicon 10.2 is a polysilicon gate of the trench type semiconductor chip, and the second silicon oxide 6 is an isolation layer between the electrostatic protection circuit and a cell region of the trench type semiconductor chip;
(1.15) forming a body region 11 by adopting an ion implantation and annealing process; (please refer to FIG. 15)
(1.16) forming the source region 12 using photolithography, ion implantation (third ion implantation doping as described below), an annealing process, and simultaneously forming third doped polysilicon 10.3 in a fourth set region, the fourth set region being located in the first set region; (please refer to FIG. 16)
(1.17) forming a first contact hole 13.1, a second contact hole 13.2 and a third contact hole 13.3 by adopting photoetching and etching processes, wherein the first contact hole 13.1 is used for leading out a source region 12 of the groove type semiconductor chip, and the second contact hole 13.2 and the third contact hole 13.3 are respectively used for leading out two ends of a polysilicon diode which is an electrostatic protection circuit. (please refer to FIG. 17)
The subsequent process steps are conventional process steps, and are not described in detail in the present application.
It is understood that the thickness of the first silicon oxide 3 is 20 to 30 nm and the thickness of the first silicon nitride 4 is 200 to 400 nm.
In the step of forming the first trench 5 in the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting an etching process, the depth D1 of the first trench 5 is 600-2000 nm (i.e., 0.6-2 μm), and the width W1 is 150-200 μm, which is significantly larger than the depth.
The etching process is isotropic etching, that is, horizontal etching occurs at the same time of vertical etching, and the etching depth of the vertical etching and the horizontal etching is adjustable, for example, the vertical etching depth D1 is 0.8 micrometers, and the horizontal etching depth D2 is 0.2 micrometers.
Because of the above-mentioned lateral etching, the width of the first trench 5 is greater than the etching width of the hard mask dielectric layer, i.e. the edge of the first trench 5 is located under the hard mask dielectric layer. (please refer to FIG. 3)
Because of this, it is ensured that the top of the second silicon oxide 6 grown in said step (1.4) does not protrude above the silicon plane, i.e. the lower surface of the first silicon oxide 3, which is also one of the distinguishing features of the present application from the disclosed application patent 201610768814.9, in the application patent 201610768814.9 the top of the grown field oxide layer is significantly above the silicon plane.
It will be appreciated that in the step of growing the second silicon oxide 6 in the first trench 5 using the thermal oxidation process, the thickness D3 of the second silicon oxide 6 is 150 to 600 nm (i.e., 0.15 to 0.6 μm), which is much greater than the thickness of the third silicon oxide 9, i.e., the gate oxide layer, and is smaller than the depth D1 of the first trench 5, for example, the depth D1 of the first trench 5 is 0.8 μm, and the thickness D3 of the second silicon oxide 6 is 0.2 μm.
Due to the blocking effect of the first silicon nitride 4, during the process of growing the second silicon oxide 6 by this thermal oxidation process, the silicon oxide will grow only in the area not covered by the first silicon nitride 4, that is, the second silicon oxide 6 will grow only on the bottom and the side of the first trench 5, and a step height difference is formed between the upper surface of the second silicon oxide 6 grown on the bottom of the first trench 5 and the silicon plane:
it is known to those skilled in the art that 0.44 unit thickness of silicon is consumed for growing a unit thickness of silicon oxide by a thermal oxidation process, and after growing a second silicon oxide 6 with a thickness of D3 by this oxidation process, the depth of the first trench 5 is changed to d1+d3 by 0.44, and the step height difference D4 from the upper surface of the second silicon oxide 6 to the silicon plane is d1+d3 by 0.44-d3=d1-d3 by 0.56, which is lower than the former. (please refer to FIG. 4)
In the step of removing the first silicon nitride 4 and growing the second silicon nitride 7, the purpose of this step is to:
the second silicon oxide 6 in the first trench 5 is a preset isolation layer, and in the process of forming the second trench 8 in the second set region in the step (1.7) by adopting an etching process, the surface of the second silicon oxide 6 needs to be protected from being etched to the surface, so that the isolation effect is poor, and therefore, the second silicon nitride 7 grows on the surface of the second silicon oxide as a barrier layer in the step (1.7).
It will be appreciated that the thickness of the polysilicon 10 must be greater than D4 (otherwise, the polysilicon 10 is not filled in the first trench, a step height difference is formed after step 1.14, i.e. the top of the polysilicon 10 is lower than the silicon plane), the polysilicon 10 is doped by first ion implantation, the polysilicon 10.1 is formed on the surface layer of the polysilicon 10, and the polysilicon 10 in the third set region is doped by second ion implantation using photolithography and ion implantation processes, and the polysilicon 10.2 is formed on the surface layer of the polysilicon 10;
the doping type of the first ion implantation doping is opposite to that of the second ion implantation doping, and the doping concentration of the second ion implantation doping is far greater than that of the first ion implantation doping, specifically:
the first ion implantation is doped withBoron concentration of 5E 13-2E 14/CM 2 The first doped polysilicon 10.1 is P-type, the second ion implantation is doped with phosphorus, and the concentration is 4E 15-1E 16/CM 2 The second doped polysilicon 10.2 is formed as N type; or alternatively
The first ion implantation is doped with phosphorus with the concentration of 5E 13-2E 14/CM 2 The first doped polysilicon 10.1 is N-type, the second ion implantation is doped with boron, and the concentration is 4E 15-1E 16/CM 2 The second doped polysilicon 10.2 is formed to be P-type.
It can be seen that after the step (1.13), the first doped polysilicon 10.1 in the first trench 5 is lightly doped polysilicon), and the second doped polysilicon 10.2 in the second trench 8 is heavily doped polysilicon, so that the resistivity is relatively low (the requirement of the trench type semiconductor chip on the resistivity of the polysilicon gate is met, and the gate resistance can be reduced).
It can be understood that the chemical mechanical polishing process is adopted to remove the first doped polysilicon 10.1 and the second doped polysilicon 10.2 higher than the upper surface of the first silicon oxide 3, and keep the first doped polysilicon 10.1 in the first trench 5 and keep the second doped polysilicon 10.2 in the second trench 8;
the cmp process grinds away unwanted polysilicon from top to bottom and eventually stays on the upper surface of the first silicon oxide 3.
The first doped polysilicon 10.1 in the first trench 5 has a thickness (D5) equal to D4 plus the thickness of the first silicon oxide 3, wherein the thickness of the first silicon oxide 3 is negligible compared to D4, i.e. D5 is approximately equal to D4, whereby it can be seen that the top of the first doped polysilicon 10.1 is substantially flush with the silicon plane and is completely flush with the upper surface of the first silicon oxide 3.
So far, the upper surface of the internal structure of the whole chip is flat, and no step height difference exists.
It will be appreciated that the formation of the source region 12 using photolithography, ion implantation, annealing processes, and the simultaneous formation of the third doped polysilicon 10.3 in a fourth set region, which is located in the first set region;
the ion implantation (third ion implantation doping) is opposite to the doping type of the first ion implantation doping, the doping type of the third ion implantation doping is the same as the doping type of the second ion implantation doping, and the doping concentration of the third ion implantation doping is far greater than that of the first ion implantation doping, specifically:
when the first ion implantation is doped with boron, the third ion implantation is doped with phosphorus or arsenic, and the concentration is 1E 15-8E 15/CM 2 Forming 10.3-bit N type of third doped polysilicon; or alternatively
When the first ion implantation is doped with phosphorus, the third ion implantation is doped with boron, and the concentration is 1E 15-8E 15/CM 2 And forming the third doped polysilicon 10.3-bit P type.
The fourth setting area is located in the first setting area, specifically:
the fourth setting region is a plurality of regions (shown in fig. 16) which are distributed at intervals, so that the formed third doped polysilicon 10.3 is a plurality of doped regions which are arranged at intervals, and the region between the third doped polysilicon 10.3 is still the first doped polysilicon 10.1, that is, the first doped polysilicon 10.1 and the third doped polysilicon 10.3 are opposite in doping type and are arranged at intervals, so that a polysilicon diode composed of a forward PN junction and a reverse PN junction which are connected in series is formed, and in the step (1.17), the second contact hole 13.2 and the third contact hole 13.3 are manufactured and are respectively used for leading out two ends of the polysilicon diode and are respectively connected to the grid electrode and the source electrode of the trench type semiconductor chip, that is, the trench type semiconductor chip of the internal integrated electrostatic protection circuit is formed.
Fig. 18, 19 and 20 are enlarged schematic views of the cross-sectional structure of the electrostatic protection circuit (polysilicon diode) integrated in the chip manufactured by the present application, and fig. 21 and 22 are schematic views of the planar structure of the electrostatic protection circuit (polysilicon diode) integrated in the chip manufactured by the present application (schematic view of top view);
it can be seen that the whole electrostatic protection circuit is placed in one large trench 5 (size 150-200 um), the bottom and the side are surrounded by the second silicon dioxide 6 grown by thermal oxidation process (i.e. isolation oxide layer, which has better voltage-withstanding property due to the growth by thermal oxidation process, and has larger thickness, thus having better isolation effect than the conventional technology, and is not easy to break down), and the polysilicon diode has a shape of square ring with central symmetry, and the PN junction area of the polysilicon diode is larger and electrostatic protection capability is stronger.
When the groove type semiconductor chip is an N-channel device, the corresponding section schematic diagram is 19, and the plane schematic diagram is 21;
when the trench semiconductor chip is a P-channel device, the corresponding cross-sectional view is 20 and the plan view is 22.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
1. the polysilicon diode formed by the application is positioned in the groove, the top of the polysilicon diode is basically level with the silicon plane, the problem of step height difference is completely eliminated, the process difficulty is reduced, and the integration level of the chip can be greatly improved.
2. The application adopts only one layer of polysilicon, thus realizing the polysilicon gate and the polysilicon diode, and having lower cost, but no process contradiction point related to the thickness of polysilicon in the traditional method.
3. Because the application adopts only one layer of polysilicon to realize the polysilicon gate and the polysilicon diode, the doping type of the polysilicon gate can only be ion implantation doping, and therefore, the square resistance of the formed polysilicon gate is slightly larger than that of the polysilicon doped in situ (doped at the same time of deposition), and the polysilicon gate is more suitable for the application fields with not particularly strict requirements on parasitic resistance of the gate but rather strict requirements on cost.
4. From practice, the inventor repeatedly researches and demonstrates that all the process steps and process parameters are skillfully designed and matched, so that the process steps and the physical structure are buckled, and the effect that the traditional method cannot form is finally generated.
While the application has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
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