CN116313803A - Manufacturing method of shielded gate trench type MOS device - Google Patents

Abstract

The invention provides a manufacturing method of a shielded gate trench type MOS device, wherein the forming process of a gate dielectric layer comprises the following steps: forming an inter-gate dielectric material layer in the trench, wherein the inter-gate dielectric material layer is positioned on the shielding gate structure and is provided with an opening; filling the openings with a flowable coating; and etching the inter-gate dielectric material layer and the flowable coating in the trench to form the inter-gate dielectric layer. When an inter-gate dielectric material layer is formed in the groove, an opening is reserved in the inter-gate dielectric material layer; and filling the opening with a flowable coating, so that when the inter-gate dielectric material layer in the groove and the flowable coating are etched to form the inter-gate dielectric layer, the inter-gate dielectric layer with uniform thickness and meeting the requirements can be obtained, and further the shielding gate and the polysilicon gate can be effectively isolated, and the gate source current (IGSS) is improved.

Description

Manufacturing method of shielded gate trench MOS device

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a shielded gate trench type MOS device.

Background technique

Trench MOS devices have become mainstream MOS devices because of their many advantages. Among them, the shield gate trench (Shield Gate Trench, SGT) type MOS device is the most advanced power MOSFET device technology at present, which can reduce the conduction loss and switching loss of the system, and improve the use efficiency of the system. The gate structure of the SGT MOS device includes a shielded gate and a polysilicon gate (Gate Poly). The polysilicon gate is used as the gate electrode. The shielded gate is usually also called the source polysilicon (Source Poly). They are all formed in the trench and oxidized through the gates. layer (Inter Po1y Oxide, IPO) insulation isolation.

Existing shielded gate trench MOS devices often have the problem of poor gate-source current (IGSS), which makes it difficult to meet the requirements of higher performance devices.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a shielded gate trench type MOS device, so as to solve the problem that the shielded gate trench type MOS device often has poor gate-source current (IGSS) in the prior art.

In order to solve the above technical problems, the present invention provides a method for manufacturing a shielded gate trench type MOS device, the method for manufacturing a shielded gate trench type MOS device includes:

providing a semiconductor substrate having a trench formed therein;

forming a shielding gate structure in the trench, the shielding gate structure comprising a first gate dielectric layer and a shielding gate located in the first gate dielectric layer;

forming an inter-gate dielectric layer in the trench, the inter-gate dielectric layer being located on the shielded gate structure; and,

forming a polysilicon gate structure in the trench, the polysilicon gate structure is located on the inter-gate dielectric layer, the polysilicon gate structure includes a second gate dielectric layer and a polysilicon gate located in the second gate dielectric layer;

Wherein, forming the inter-gate dielectric layer in the trench includes:

forming an inter-gate dielectric material layer in the trench, the inter-gate dielectric material layer is located on the shielded gate structure, and the inter-gate dielectric material layer has an opening;

filling the opening with a flowable coating; and,

The inter-gate dielectric material layer and the flowable coating layer in the trench are etched to form the inter-gate dielectric layer.

Optionally, in the manufacturing method of the shielded gate trench MOS device, the step of forming an inter-gate dielectric material layer in the trench includes:

The inter-gate dielectric material layer is formed in the trench by using a high-density plasma process, the inter-gate dielectric material layer covers the upper surface of the shield gate structure and the side surfaces of the trench, and extends to cover the The upper surface of the semiconductor substrate; the opening extends from the surface of the inter-gate dielectric material layer into the inter-gate dielectric material layer.

Optionally, in the manufacturing method of the shielded gate trench MOS device, the thickness of the intergate dielectric material layer covering the upper surface of the shielded gate structure is greater than or equal to the thickness of the intergate dielectric to be formed layer thickness.

Optionally, in the manufacturing method of the shielded gate trench MOS device, the step of filling the opening with a flowable coating includes:

The opening is filled with the flowable coating by a coating process, and the flowable coating also extends to cover the inter-gate dielectric material layer on the upper surface of the semiconductor substrate.

Optionally, in the manufacturing method of the shielded gate trench MOS device, after the step of filling the opening with a flowable coating, after the step of etching the inter-gate dielectric in the trench Before the step of forming the material layer and the flowable coating to form the inter-gate dielectric layer, the step of forming the inter-gate dielectric layer in the trench further includes:

The inter-gate dielectric material layer and the flowable coating layer located on the upper surface of the semiconductor substrate are removed by chemical mechanical polishing process.

Optionally, in the manufacturing method of the shielded gate trench MOS device, the material of the flowable coating is an anti-reflection layer.

Optionally, in the manufacturing method of the shielded gate trench MOS device, the etching of the inter-gate dielectric material layer and the flowable coating in the trench to form the inter-gate In the step of forming a dielectric layer, only the inter-gate dielectric material layer covering part of the thickness of the shielding gate structure is reserved as the inter-gate dielectric layer.

Optionally, in the method for manufacturing a shielded gate trench MOS device, after the shielded gate structure is formed in the trench, the aspect ratio of the remaining part of the trench is greater than or equal to 2.2:1 .

Optionally, in the manufacturing method of the shielded gate trench MOS device, the upper surface of the semiconductor substrate is covered with a dielectric layer.

Optionally, in the manufacturing method of the shielded gate trench type MOS device, the shielded gate structure is formed in the trench, the shielded gate structure includes a first gate dielectric layer and a In the step of shielding the grid in the gate dielectric layer, the upper surface of the first gate dielectric layer is flush with the upper surface of the shielding grid.

Shielded gate trench MOS devices in the prior art often have the problem of poor gate-source current (IGSS), especially low-voltage shielded gate trench MOS devices. This problem is particularly serious, which has long plagued the technology in the art personnel.

The inventor has thoroughly studied the shielded gate trench MOS device and its manufacturing method in the prior art, and found that: in shielded gate trench MOS devices, especially for low voltage shielded gate trench MOS devices, in order to reduce the unit The area on-resistance usually makes the size of the device as small as possible, correspondingly reducing the size of the trench, thereby increasing the aspect ratio of the trench; thus, when depositing the inter-gate dielectric material layer, There will be voids inside, and in the process of forming the inter-gate dielectric layer by etching the inter-gate dielectric material layer, over-etching will occur through the voids, so that the local thickness of the formed inter-gate dielectric layer does not meet the requirements , so that the shielded gate and the polysilicon gate cannot be effectively isolated, resulting in poor gate-source current (IGSS).

Based on this, the inventor proposed a method for manufacturing a shielded gate trench type MOS device, wherein the formation process of the inter-gate dielectric layer includes: forming an inter-gate dielectric material layer in the trench, and the inter-gate dielectric material layer is located at On the shielding gate structure, the inter-gate dielectric material layer has an opening; filling the opening with a flowable coating; and etching the inter-gate dielectric material layer and the flowable coating in the trench to form the inter-gate dielectric layer. In the manufacturing method of the shielded gate trench type MOS device provided by the present invention, when the inter-gate dielectric material layer is formed in the trench, an opening is left in the inter-gate dielectric material layer; The above-mentioned openings, thus, when forming the inter-gate dielectric layer by etching the inter-gate dielectric material layer and the flowable coating layer in the trench, a uniform thickness and satisfactory inter-gate gap can be obtained. The dielectric layer can effectively isolate the shielded gate and the polysilicon gate, thereby increasing the gate-source current (IGSS).

Description of drawings

FIG. 1 is a schematic flow chart of forming an inter-gate dielectric layer according to an embodiment of the present invention.

2 to 6 are schematic cross-sectional views of devices formed by performing the manufacturing method of the shielded gate trench type MOS device according to the embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100-semiconductor substrate; 102-trench; 104-dielectric layer; 106-first gate dielectric layer; 108-shielded gate; 110-shielded gate structure; 112-inter-gate dielectric material layer; 114-opening; Flow coating; 118-inter-gate dielectric layer; 120-polysilicon gate structure; 122-second gate dielectric layer; 124-polysilicon gate; h-depth; w-width.

Detailed ways

The manufacturing method of the shielded gate trench type MOS device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise defined in the application documents, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by those skilled in the art to which the present invention belongs. "First", "second" and similar words used in the description and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a" or "one" do not indicate a limitation of quantity, but mean that there is at least one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front", "rear", "lower" and/or "upper" are used for convenience of description only and are not intended to be limiting to a position or orientation in space. "Includes" or "comprises" and similar terms mean that the elements or items listed before "comprises" or "comprises" include the elements or items listed after "comprises" or "comprises" and their equivalents, and do not exclude other elements or objects. Words such as "connected" or "connected" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. As used in the present specification and appended claims, the singular forms "a", "the" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

Shielded gate trench MOS devices in the prior art often have the problem of poor gate-source current (IGSS), especially for low voltage shielded gate trench MOS devices, and this problem is particularly serious. After in-depth research, the inventor found that in shielded gate trench MOS devices, especially for low voltage shielded gate trench MOS devices, in order to reduce the on-resistance per unit area, the device size is usually made as small as possible. Correspondingly, the size of the trench will be reduced, thereby increasing the aspect ratio of the trench, and this will cause certain difficulties in filling the trench with the inter-gate dielectric material layer, so that when depositing the inter-gate dielectric material layer, There will be voids inside the inter-gate dielectric material layer, and during the process of forming the inter-gate dielectric layer by etching the inter-gate dielectric material layer, over-etching will occur through the voids, so that the formed inter-gate dielectric layer The local thickness does not meet the requirements, so that the shielded gate and the polysilicon gate cannot be effectively isolated, resulting in poor gate-source current (IGSS).

The core idea of the present invention is to provide a method for manufacturing a shielded gate trench type MOS device. The method for manufacturing a shielded gate trench type MOS device includes: providing a semiconductor substrate in which a trench is formed. forming a shielded gate structure in the trench, the shielded gate structure comprising a first gate dielectric layer and a shielded gate located in the first gate dielectric layer; forming an inter-gate dielectric layer in the trench, the The inter-gate dielectric layer is located on the shielding gate structure; and, a polysilicon gate structure is formed in the trench, the polysilicon gate structure is located on the inter-gate dielectric layer, and the polysilicon gate structure includes a second gate dielectric layer and the polysilicon gate located in the second gate dielectric layer.

As shown in FIG. 1, wherein, forming an inter-gate dielectric layer in the trench includes:

Step S10: forming an inter-gate dielectric material layer in the trench, the inter-gate dielectric material layer is located on the shielded gate structure, and the inter-gate dielectric material layer has an opening;

Step S11: filling the opening with a flowable coating; and,

Step S12: Etching the inter-gate dielectric material layer and the flowable coating in the trench to form the inter-gate dielectric layer.

Further, please refer to FIG. 2 to FIG. 6 , which are schematic cross-sectional views of devices formed by performing the manufacturing method of the shielded gate trench type MOS device according to the embodiment of the present invention.

As shown in FIG. 2, a semiconductor substrate 100 is provided, and the material of the semiconductor substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium or other III, V group compounds. In the embodiment of the application, the semiconductor substrate 100 is a silicon substrate.

Next, an etching process is performed on the semiconductor substrate 100 to form a trench 102 in the semiconductor substrate 100 . Specifically, a patterned photoresist layer (not shown in the figure) may be formed on the surface of the semiconductor substrate 100 first, and the patterned photoresist layer has one or more openings, and the openings expose Part of the surface of the semiconductor substrate 100 . Next, an etching process is performed on the exposed semiconductor substrate 100 to form one or more trenches 102 in the semiconductor substrate 100 . In the embodiment of the present application, a groove 102 is schematically shown. The trench 102 is a deep trench, wherein the aspect ratio of the trench 102 may be greater than or equal to 3:1, for example, the aspect ratio of the trench 102 may be 3:1, 4:1 or 5:1 etc. After the trench 102 is formed, the patterned photoresist layer is removed.

Preferably, before forming a patterned photoresist layer on the surface of the semiconductor substrate 100, a dielectric layer 104 may be formed on the surface of the semiconductor substrate 100, through which the semiconductor layer 104 is protected. the surface of the substrate 100. Wherein, the material of the dielectric layer 104 may specifically be silicon nitride, silicon oxide, organosiloxane, or titanium nitride. In the embodiment of the present application, the material of the dielectric layer 104 is preferably silicon nitride, and the dielectric layer 104 can protect the surface of the semiconductor substrate 100 and can also be used as a stop layer for subsequent processes to simplify the process and improve process reliability.

Please continue to refer to FIG. 2, in the embodiment of the present application, then, a first gate dielectric layer 106 is formed in the trench 102, and the first gate dielectric layer 106 covers the surface of the trench 102 and can be further extended. covering the surface of the semiconductor substrate 100 . Wherein, the material of the first gate dielectric layer 106 may be silicon oxide. Specifically, the first gate dielectric layer 106 may be formed by a thermal oxidation process, or the first gate dielectric layer 106 may be formed by a deposition process.

Next, a first polysilicon layer (not shown in the figure) is formed on the first gate dielectric layer 106 , and the first polysilicon layer fills the trench 102 . Wherein, the material of the first polysilicon layer can be doped polysilicon; it can also be undoped polysilicon, and for undoped polysilicon, further, the first polysilicon can be The layer performs an ion implantation process, and the implanted ions may be, for example, boron ions, indium ions, phosphorus ions, arsenic ions, etc., and an annealing process may be performed to activate the implanted ions. Next, the first polysilicon layer is etched back to form a shielding gate 108 to form a shielding gate structure 110 . Here, the shielding gate structure 110 includes the first gate dielectric layer 106 and the shielding gate 108 located in the first gate dielectric layer 106 .

In the embodiment of the present application, part of the first gate dielectric layer 106 in the trench 102 is also removed at the same time, so that the upper surface of the first gate dielectric layer 106 in the trench 102 and the The upper surface of the shielding grid 108 is flush with each other. That is, here, the first gate dielectric layer 106 located in the middle and upper part of the trench 102 is removed, thereby reducing the depth and width of the upper part of the trench 102 (that is, the remaining part of the trench 102) ratio, thereby facilitating the formation of the subsequent inter-gate dielectric layer.

After the shielding gate structure 110 is formed in the trench 102, preferably, the aspect ratio of the remaining part of the trench 102 (that is, the depth h:width w of the remaining part of the trench 102) is greater than or equal to 2.2:1, for example, the aspect ratio of the remaining part of the trench 102 is 2.5:1, 3:1 or 3.5:1, etc., thus, a low-voltage shielded gate trench MOS device can be formed to further satisfy the shielded gate Functional requirements of trench MOS devices.

Please continue to refer to FIG. 2 , an inter-gate dielectric material layer 112 is formed in the trench 102 , the inter-gate dielectric material layer 112 is located on the shielded gate structure 110 , and the inter-gate dielectric material layer 112 has an opening 114 . Specifically, the inter-gate dielectric material layer 112 is formed in the trench 102 by using a high-density plasma process (HDP), and the inter-gate dielectric material layer 112 covers the upper surface of the shielding gate structure 110 and the The side surfaces of the trench 102 also extend to cover the upper surface of the semiconductor substrate 100, where the inter-gate dielectric material layer 112 extends to cover the dielectric layer 104; the opening 114 extends from the inter-gate dielectric material layer The surface of the inter-gate dielectric material layer 112 extends into the inter-gate dielectric material layer 112 .

Wherein, the thickness of the inter-gate dielectric material layer 112 covering the upper surface of the shielding gate structure 110 is greater than or equal to the thickness of the subsequently formed inter-gate dielectric layer. Preferably, the thickness of the inter-gate dielectric material layer 112 covering the upper surface of the shielding gate structure 110 is greater than the thickness of the subsequently formed inter-gate dielectric layer, thereby ensuring that the subsequently formed inter-gate The thickness of the dielectric layer meets the needs of high-performance devices and achieves the purpose of increasing the gate-source current (IGSS); at the same time, it can also provide redundancy for the subsequent etching process, thereby simplifying process requirements and improving process reliability.

Next, as shown in FIG. 3 , a flowable coating 116 is filled in the opening 114 , and the flowable coating 116 fills up the opening 114 . Specifically, the flowable coating 116 can be filled in the opening 114 by using a coating process, and further, the flowable coating 116 also extends to cover the gate located on the upper surface of the semiconductor substrate 100 . interlayer dielectric material layer 112 . Here, by utilizing the flowability of the flowable coating 116, the opening 114 is fully filled with the flowable coating 116, so that the inter-gate dielectric layer can be formed in the subsequent etching process. In order to avoid the problem of over-etching caused by voids. Wherein, the material of the flowable coating 116 can be, for example, commercially available bottom anti-reflective coating (BARC) or top anti-reflective coating (TARC) with certain fluidity.

Please refer to FIG. 4 , in the embodiment of the present application, the inter-gate dielectric material layer 112 and the flowable coating layer 116 located on the upper surface of the semiconductor substrate 100 are firstly removed by a chemical mechanical polishing process. Here, the dielectric layer 104 can be used as a stop layer of the chemical mechanical polishing process, so as to not only protect the semiconductor substrate 100 but also facilitate the execution of the process.

Wherein, after removing the inter-gate dielectric material layer 112 and the flowable coating layer 116 located on the upper surface of the semiconductor substrate 100 by a chemical mechanical polishing process, the dielectric layer 104 can be further removed to expose the the upper surface of the semiconductor substrate 100. Specifically, the dielectric layer 104 can be removed by hot phosphoric acid chemical method.

As shown in FIG. 5 , next, the inter-gate dielectric material layer 112 and the flowable coating layer 116 in the trench 102 are etched to form the inter-gate dielectric layer 118 . Specifically, an etching process may be performed on the flowable coating layer 116 and the inter-gate dielectric material layer 112 in the trench 102 through a dry or wet etching process. Here, since the generation of voids in the trench 102 is avoided by the flowable coating 116, the quality of the etching process is ensured, and the inter-gate dielectric layer 118 with a uniform thickness can be formed. Further, it is also Increased gate-source current (IGSS). Here, all of the flowable coating layer 116 is removed by an etching process, and only the inter-gate dielectric material layer 112 covering a partial thickness of the shielding gate structure 110 remains as the inter-gate dielectric layer 118 .

Next, referring to FIG. 6, a polysilicon gate structure 120 is formed in the trench 102, the polysilicon gate structure 120 is located on the inter-gate dielectric layer 118, and the polysilicon gate structure 120 includes a second gate dielectric layer 122 and The polysilicon gate 124 located in the second gate dielectric layer 122 . Specifically, the second gate dielectric layer 122 may be formed in the trench 102 by an oxidation process or a deposition process, and then a second polysilicon layer is filled in the second gate dielectric layer 122 to form the polysilicon gate 124 , thereby forming the polysilicon gate structure 120 .

In summary, in the embodiment of the present application, when the inter-gate dielectric material layer is formed in the trench, an opening is left in the inter-gate dielectric material layer; and then the opening is filled with a flowable coating, thereby , when forming the inter-gate dielectric layer by etching the inter-gate dielectric material layer and the flowable coating layer in the trench, an inter-gate dielectric layer with uniform thickness and meeting requirements can be obtained, and then can Effectively isolates the shielded gate from the polysilicon gate, increasing the gate-to-source current (IGSS).

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (10)

1. A manufacturing method of a shielded gate trench type MOS device, characterized in that, the manufacturing method of the shielded gate trench type MOS device comprises: providing a semiconductor substrate having a trench formed therein; forming a shielding gate structure in the trench, the shielding gate structure comprising a first gate dielectric layer and a shielding gate located in the first gate dielectric layer; forming an inter-gate dielectric layer in the trench, the inter-gate dielectric layer being located on the shielded gate structure; and, forming a polysilicon gate structure in the trench, the polysilicon gate structure is located on the inter-gate dielectric layer, the polysilicon gate structure includes a second gate dielectric layer and a polysilicon gate located in the second gate dielectric layer; Wherein, forming the inter-gate dielectric layer in the trench includes: forming an inter-gate dielectric material layer in the trench, the inter-gate dielectric material layer is located on the shielded gate structure, and the inter-gate dielectric material layer has an opening; filling the opening with a flowable coating; and, The inter-gate dielectric material layer and the flowable coating layer in the trench are etched to form the inter-gate dielectric layer. 2. The method for manufacturing a shielded gate trench type MOS device as claimed in claim 1, wherein the step of forming an inter-gate dielectric material layer in the trench comprises: The inter-gate dielectric material layer is formed in the trench by using a high-density plasma process, the inter-gate dielectric material layer covers the upper surface of the shield gate structure and the side surfaces of the trench, and extends to cover the The upper surface of the semiconductor substrate; the opening extends from the surface of the inter-gate dielectric material layer into the inter-gate dielectric material layer. 3. The method for manufacturing a shielded gate trench type MOS device according to claim 2, wherein the thickness of the inter-gate dielectric material layer covering the upper surface of the shielded gate structure is greater than or equal to the thickness of the required layer to be formed. The thickness of the inter-gate dielectric layer. 4. The method for manufacturing a shielded gate trench MOS device as claimed in claim 2, wherein the step of filling the opening with a flowable coating comprises: The opening is filled with the flowable coating by a coating process, and the flowable coating also extends to cover the inter-gate dielectric material layer on the upper surface of the semiconductor substrate. 5. The manufacturing method of a shielded gate trench MOS device according to claim 4, characterized in that, after the step of filling the opening with a flowable coating, after the step of etching the trench, Before the step of forming the inter-gate dielectric material layer and the flowable coating to form the inter-gate dielectric layer, the step of forming the inter-gate dielectric layer in the trench further includes: The inter-gate dielectric material layer and the flowable coating layer located on the upper surface of the semiconductor substrate are removed by chemical mechanical polishing process. 6 . The method for manufacturing a shielded gate trench MOS device according to claim 1 , wherein the material of the flowable coating is an anti-reflection layer. 7. The method for manufacturing a shielded gate trench type MOS device according to any one of claims 1 to 5, characterized in that the etching the inter-gate dielectric material layer in the trench and the In the step of forming the inter-gate dielectric layer by flowable coating, only the inter-gate dielectric material layer covering a partial thickness of the shielding gate structure is reserved as the inter-gate dielectric layer. 8. The method for manufacturing a shielded gate trench MOS device according to any one of claims 1 to 5, characterized in that, after the shielded gate structure is formed in the trench, the remaining part of the trench The aspect ratio is greater than or equal to 2.2:1. 9 . The method for manufacturing a shielded gate trench MOS device according to claim 1 , wherein the upper surface of the semiconductor substrate is covered with a dielectric layer. 10. The method for manufacturing a shielded gate trench type MOS device according to any one of claims 1 to 5, wherein the shielded gate structure is formed in the trench, and the shielded gate structure comprises a first In the step of providing a gate dielectric layer and the shielding grid located in the first gate dielectric layer, the upper surface of the first gate dielectric layer is flush with the upper surface of the shielding grid.

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