CN116318080A - comparator circuit - Google Patents

Abstract

The invention discloses a comparator circuit, comprising: an input stage circuit, receiving a first input voltage and a second input voltage, for comparing the first input voltage with the second input voltage, and providing a comparison signal to the first node; an output stage circuit, connected to the first node, for generating an output voltage signal according to the potential of the first node; a current-limiting clamp circuit, connected to the output stage circuit, for When the output voltage signal is at a logic high level, the first quiescent current of the output stage circuit is limited to a preset current, thereby providing a comparator circuit with fast response and low power consumption.

Description

comparator circuit

technical field

The invention relates to the technical field of integrated circuits, in particular to a comparator circuit.

Background technique

A comparator circuit is a commonly used signal processing circuit that can compare an input voltage with a reference voltage and output the comparison result. The output result has two states of logic high level and logic low level. In automatic control and automatic measurement systems, comparator circuits are often used in limit alarms, analog-to-digital conversion, and the generation and change of various non-sine waves, so comparator circuits are widely used in communications, PC, consumer, automotive and industry and other fields.

In many application scenarios, there are certain requirements for the response speed of the comparator circuit. For example, in an analog-to-digital converter, the performance of the comparator circuit can determine the overall performance of the analog-to-digital converter. In the prior art, the method of increasing power consumption is mostly used to increase the response speed of the comparator circuit, which not only limits the application scenarios of the comparator circuit, but also increases the overall power consumption of the circuit or system.

Therefore, an improved comparator circuit is expected to solve the problem of incompatibility between fast response speed and low power consumption in the prior art.

Contents of the invention

In view of the above problems, an object of the present invention is to provide a comparator circuit with fast response and low power consumption.

According to an aspect of the present invention, a comparator circuit is provided, including: an input stage circuit receiving a first input voltage and a second input voltage for comparing the first input voltage with the second input voltage, and The comparison signal is provided to the first node; the output stage circuit is connected to the first node, and is used to generate an output voltage signal according to the potential of the first node; a current-limiting clamp circuit is connected to the output stage circuit, It is used for limiting the first quiescent current of the output stage circuit to a preset current when the output voltage signal is at logic high level.

Optionally, when the output voltage signal is at logic high level, the ratio of the preset current to the second quiescent current of the current limiting and clamping circuit is n.

Optionally, the input stage circuit includes: a first current source, the first end of the first current source is connected to a power supply voltage; a transconductance amplifier, a positive power supply end of the transconductance amplifier is connected to the first current source connected to the second terminal of the source, the two input terminals respectively receive the first input voltage and the second input voltage, and the output terminal provides a comparison signal related to the first input voltage and the second input voltage to the Describe the first node.

Optionally, the output stage circuit includes: a second current source, the first terminal of the second current source is connected to a power supply voltage; a first transistor is connected between the second current source and ground, and the A control terminal of the first transistor is connected to the first node, wherein a common node between the second current source and the first transistor is used to generate the output voltage signal.

Optionally, the current limiting and clamping circuit includes: a third current source, the first end of which is connected to the power supply voltage; a second transistor, connected to the second end of the third current source and the first between the nodes, the control terminal of the second transistor is connected to the bias voltage; and the third transistor is connected between the second terminal of the third current source and ground, the control terminal of the third transistor is connected to the The first node is connected.

Optionally, a ratio of the preset current to the second quiescent current is equal to a ratio of a transistor size of the first transistor to a transistor size of the third transistor.

Optionally, the second transistor is mainly used to clamp the potential of the first node to the gate-source voltage of the first transistor.

Optionally, the preset current can be changed by adjusting the size of the third current source and/or the ratio of the transistor size of the first transistor to the transistor size of the third transistor.

Optionally, the first transistor and the third transistor are selected from N-type field effect transistors, and the second transistor is selected from P-type field effect transistors.

To sum up, the comparator circuit of the embodiment of the present invention can increase the charging and discharging speed of the output terminal of the comparator circuit by adding the third current source, so that the output voltage signal of the comparator circuit can quickly respond to the change of the first input voltage and the second input voltage thereby flipping. Further, the first current source and the second transistor are added, so that the second transistor, the third transistor and the first current source form a current limiting loop, so that the ratio of the current flowing through the third transistor to the current flowing through the second transistor is n, the quiescent current of the final comparison circuit has nothing to do with the third current source, while improving the response speed of the comparator circuit, no additional power consumption is added, and a comparator circuit with fast response speed and low power consumption is realized.

Optionally, after the first transistor is turned on, the comparison signal is clamped near the gate-source voltage, and when the first input voltage is greater than the second input voltage, the level of the comparison signal starts to rise from the gate-source voltage of the third transistor, The flipping of the output voltage is made faster, and the response speed of the comparator circuit is further improved.

Description of drawings

Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above-mentioned and other objects, features and advantages of the present invention will be more clear, in the accompanying drawings:

Fig. 1 shows the circuit structure diagram according to the comparator circuit of prior art;

FIG. 2 shows a circuit structure diagram of a comparator circuit according to an embodiment of the present invention.

Detailed ways

Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

It should be understood that in the following description, "circuitry" may include single or multiple combined hardware circuits, programmable circuits, state machine circuits and/or elements capable of storing instructions for execution by programmable circuits. When an element or circuit is said to be "connected to" another element or is said to be "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements and the connection between elements can be be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, there are no intervening elements present.

Also, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The patent specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing.

In this application, the transistor may include one selected from a bipolar transistor or a field effect transistor. The first terminal and the second terminal of the transistor are the high potential terminal and the low potential terminal on the current path respectively, and the control terminal is used for receiving and controlling signal to turn the transistor on and off. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal and a control terminal. In the on state of the MOSFET, current flows from the first terminal to the second terminal. The first terminal, the second terminal and the control terminal of the P-type MOSFET are respectively the source, the drain and the gate, and the first terminal, the second terminal and the control terminal of the N-type MOSFET are respectively the drain, the source and the gate.

In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

FIG. 1 shows a circuit structure diagram of a comparator circuit according to the prior art. The comparator circuit 100 includes an input stage circuit 110 , a transistor Mp1 and an output stage circuit 130 .

The input stage circuit 110 receives the first input voltage Vin and the second input voltage Vref, is used for comparing the first input voltage Vin and the second input voltage Vref, and provides the comparison signal Scomp to the first node Q.

The output stage circuit 130 is connected to the first node Q, and generates an output voltage signal Vout according to the potential of the first node Q.

The transistor Mp1 clamps the level of the first node Q according to the level value of the output voltage signal Vout.

Specifically, the input stage circuit 110 includes a transconductance amplifier 111 and a first current source Ib1. The positive power supply terminal of the transconductance amplifier 111 is connected to the power supply voltage Vdd through the first current source Ib1, the negative power supply terminal is grounded, and the two input terminals respectively receive the first input signal Vin and the second input signal Vref, and the transconductance amplifier 111 is used for comparing the first input signal Vin and the second input signal Vref. An input signal Vin and a second input signal Vref are provided, and a comparison signal Scomp is provided to the first node Q.

The output stage circuit 130 includes a second current source Ib2 and a transistor Mn1 sequentially connected in series between a power supply voltage Vdd and ground. The intermediate node between the second current source Ib2 and the transistor Mn1 is the output terminal of the comparator circuit 100 , the control terminal of the transistor Mn1 is connected to the first node Q, and an output voltage signal Vout is generated according to the level of the first node Q.

In this embodiment, the comparator circuit 100 further includes a capacitor Cp, the first end of which is connected to the second end of the current source Ib2, and the second end is grounded.

The control terminal of the transistor Mp1 is connected to the bias voltage Vb, the first terminal is connected to the output terminal of the comparator circuit 100, and the second terminal is connected to the first node Q. When the output voltage Vout is greater than the preset voltage, the transistor Mp1 is turned on. , so that the comparison signal Scomp is clamped at the gate-source voltage Vgs1 of the transistor Mn1.

The prior art adopts the method of increasing the second current source Ib2 to speed up the charging and discharging rate, so that the output voltage Vout of the comparator circuit 100 can quickly reverse in response to the changes of the first input voltage Vin and the second input voltage Vref.

However, when the first input voltage Vin is greater than the second input voltage Vref and the output voltage Vout remains at a logic high level, the quiescent current Iq of the comparator circuit 100 = Ib1 + Ib2 . It can be seen that the quiescent current Iq of the comparator circuit 100 increases with the increase of the second current Ib2, and the increase of the second current Ib2 improves the response speed of the comparator circuit 100 while also increasing its quiescent power consumption, which limits the comparator The application scenarios of the circuit 100 increase the power consumption of the circuit or system to which the comparator circuit 100 is applied.

FIG. 2 shows a circuit structure diagram of a comparator circuit according to an embodiment of the present invention. The comparator circuit 200 includes an input stage circuit 210 , a current limiting and clamping circuit 220 and an output stage circuit 230 .

The input stage circuit 210 receives the first input voltage Vin and the second input voltage Vref for comparing the first input voltage Vin and the second input voltage Vref, and provides the comparison signal Scomp to the first node Q.

The output stage circuit 230 is connected to the first node Q, and is used for generating an output voltage signal Vout according to the potential of the first node Q.

The current-limiting clamp circuit 220 is connected to the output stage circuit 230 and the first node Q, and is used to limit the current of the output stage circuit 230 to ground, that is, the quiescent current Iq1, to a preset value when the output voltage signal Vout is at a logic high level. current. Wherein, when the output voltage signal Vout is logic high level, the ratio of the preset current to the quiescent current Iq2 is n, and the quiescent current Iq2 is the ground current of the current limiting and clamping circuit 220 .

Specifically, the input stage circuit 210 includes a transconductance amplifier 211 and a current source Ib1. The positive power supply terminal of the transconductance amplifier 211 is connected to the power supply voltage Vdd through the current source Ib1, the negative power supply terminal is grounded, and the two input terminals respectively receive the first input signal Vin and the second input signal Vref, and the transconductance amplifier 211 compares the first input signal Vin and the second input signal Vref, and provide the comparison signal Scomp to the first node Q.

The output stage circuit 230 includes a current source Ib2 and a transistor Mn1. The first end of the current source Ib2 is connected to the power supply voltage Vdd. The first terminal of the transistor Mn1 is connected to the second terminal of the current source Ib2 for generating the output voltage signal Vout, the second terminal is grounded, and the control terminal is connected to the first node Q.

In this embodiment, the comparator circuit 200 further includes a capacitor Cp, the first end of which is connected to the second end of the current source Ib2, and the second end is grounded.

The current-limiting clamp circuit 220 includes a current source Ib3 , a transistor Mp1 and a transistor Mn2 . The first end of the current source Ib3 is connected to the power voltage Vdd. The first end of the transistor Mn2 is connected to the second end of the current source Ib3, the second end is grounded, and the control end is connected to the first node Q. The first terminal of the transistor Mp1 is connected to the second terminal of the current source Ib3, the second terminal is connected to the first node Q, and the control terminal is connected to the bias voltage Vb.

Wherein, the transistor Mp1 is selected from a P-type field effect transistor, the transistor Mn1 and the transistor Mn2 are selected from an N-type field effect transistor, and the ratio of the transistor size of the transistor Mn1 to the transistor Mn2 is n, that is, the width-to-length ratio of the transistor Mn1 and the transistor Mn2 The ratio of width to length is n.

When the first input voltage Vin is greater than the second input voltage Vref and the output voltage signal Vout remains at a logic high level, the transconductance amplifier 211 absorbs a current of ΔV*gm from the first node Q to pull the voltage of the first node Q Low, the control terminal voltage of the transistor Mn1 and the transistor Mn2 decreases, and the gate-source voltage of the two decreases, so that the current flowing through the two also decreases. Wherein, ΔV represents the difference between the first input voltage Vin and the second input voltage Vref, and gm represents the gain of the transconductance amplifier 211 . At this time, the transistor Mn1, the transistor Mn2 and the current source Ib3 form a current limiting loop, and the ratio of the quiescent current Iq1 flowing through the transistor Mn1 to the quiescent current Iq2 flowing through the transistor Mn2 is equal to the ratio of the transistor sizes of the transistor Mn1 and the transistor Mn2, that is, Iq1 =n*Iq2. Then the quiescent current Iq=Ib1+Iq1+Ib3 of the comparator circuit 200, wherein Iq1=n*Iq2=n*(Ib3-ΔV*gm), the quiescent current Iq=Ib1+ (n+1)*Ib3-n*ΔV*gm. It can be seen that the quiescent current Iq of the comparator circuit 200 has nothing to do with the second current source Ib2. Although the current source Ib2 is increased in order to improve the response speed of the comparator circuit 200, the final quiescent current consumption of the comparator circuit 200 has nothing to do with the size of the current source Ib2. , the response speed of the comparator circuit 200 is improved without increasing the extra quiescent current consumption.

In a feasible embodiment, the transistor Mn1 and the transistor Mn2 adopt the same transistor size, that is, the quiescent current Iq1 is equal to the quiescent current Iq2, and finally the quiescent current Iq of the comparator circuit 200=Ib1+2*Ib3-ΔV*gm.

Optionally, when the transistor Mp1 is turned on, the potential of the first node Q is clamped at the gate-source voltage Vgs1 of the transistor Mn1, and when the comparison signal Scomp changes, the voltage of the first node Q does not need to rise from zero, further speeding up the comparison The response speed of the device circuit 200.

To sum up, the comparator circuit of the embodiment of the present invention can increase the charging and discharging speed of the output terminal of the comparator circuit by increasing the current source Ib2, so that the output voltage signal of the comparator circuit can quickly respond to changes in the first input voltage and the second input voltage, thereby Flip. Further, increase the current source Ib3 and the transistor Mn2, so that the transistor Mn1, the transistor Mn2 and the current source Ib3 form a current limiting loop, so that the ratio of the current flowing through the transistor Mn1 to the current flowing through the transistor Mn2 is n, and finally the static state of the comparison circuit The current has nothing to do with the current source Ib2, while improving the response speed of the comparator circuit, no additional power consumption is added, and a comparator circuit with fast response speed and low power consumption is realized.

Optionally, after the transistor Mp1 is turned on, the comparison signal is clamped near the gate-source voltage of the transistor Mn1, and when the first input voltage is greater than the second input voltage, the level of the comparison signal starts to rise from the gate-source voltage of the transistor Mn1 , so that the output voltage flips faster, and further improves the response speed of the comparator circuit.

It should be noted that those of ordinary skill in the art can understand that the words "during", "when" and "when" used herein related to circuit operation are not strict terms that represent actions that occur immediately when the start-up action starts, Rather, there may be some small but reasonable one or more delays between it and the reaction initiated by the start action, such as various transmission delays and the like. The words "about" or "substantially" are used herein to mean that the element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always minor deviations which make it difficult for the values or positions to be exactly as stated. It has been well established in the art that deviations of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) are reasonable deviations from the exact ideal goal described. When used in conjunction with signal state, the actual voltage value or logic state (such as "1" or "0") of the signal depends on whether positive or negative logic is used.

Embodiments according to the present invention are described above, and these embodiments do not exhaustively describe all details, nor limit the invention to only specific embodiments. Obviously many modifications and variations are possible in light of the above description. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modification on the basis of the present invention. The protection scope of the present invention shall be defined by the claims of the present invention and their equivalents.

Claims (9)

1. A comparator circuit comprising:

an input stage circuit receiving a first input voltage and a second input voltage, for comparing the first input voltage with the second input voltage and providing a comparison signal to a first node;

the output stage circuit is connected with the first node and is used for generating an output voltage signal according to the potential of the first node;

and the current-limiting clamp circuit is connected with the output stage circuit and is used for limiting the first quiescent current of the output stage circuit to a preset current when the output voltage signal is at a logic high level.

2. The comparator circuit of claim 1, wherein the ratio of the preset current to the second quiescent current of the current limiting clamp circuit is n when the output voltage signal is at a logic high level.

3. The comparator circuit of claim 1, wherein the input stage circuit comprises:

the first end of the first current source is connected with the power supply voltage;

and the positive power end of the transconductance amplifier is connected with the second end of the first current source, the two input ends respectively receive the first input voltage and the second input voltage, and the output end provides comparison signals related to the first input voltage and the second input voltage to the first node.

4. The comparator circuit of claim 2, wherein the output stage circuit comprises:

the first end of the second current source is connected with the power supply voltage;

a first transistor connected between the second current source and ground, a control terminal of the first transistor being connected to the first node,

wherein a common node between the second current source and the first transistor is used to generate the output voltage signal.

5. The comparator circuit of claim 4, wherein the current limiting clamp circuit comprises:

a third current source having a first end connected to the power supply voltage;

a second transistor connected between a second end of the third current source and the first node, a control end of the second transistor being connected to a bias voltage; and

and a third transistor connected between the second end of the third current source and ground, the control end of the third transistor being connected to the first node.

6. The comparator circuit of claim 5, wherein a ratio of the preset current to the second quiescent current is equal to a ratio of a transistor size of the first transistor to a transistor size of the third transistor.

7. The comparator circuit of claim 5, wherein the second transistor is primarily for clamping the potential of the first node to a gate-source voltage of the first transistor.

8. The comparator circuit of claim 5, the preset current being changeable by adjusting a size of the third current source and/or a ratio of a transistor size of the first transistor to a transistor size of the third transistor.

9. The comparator circuit of claim 5, wherein the first transistor and the third transistor are selected from an N-type field effect transistor and the second transistor is selected from a P-type field effect transistor.

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