CN116314279A - Terminal protection structure of power electronic chip - Google Patents

Abstract

The invention discloses a power electronic chip terminal protection structure, which comprises a first conductivity type substrate, a first conductivity type epitaxial layer drift region, a second conductivity type doped region, several grooves, and a second conductivity type junction protection structure. region, passivation layer, anode metal electrode, cathode metal electrode; after the second conductivity type doped region is divided by the groove, the second conductivity type doped region close to the active region of the chip and connected to each other constitutes the main junction region, Other regions of the second conductivity type doped region except the main junction region constitute the termination region; the present invention utilizes the trench structure of the termination region, which can be compatible with the process of epitaxially forming the second conductivity type doping region, thereby facilitating the formation of a deeper The second conductivity type region can be a terminal solution for trench devices and super junction devices, and can improve the radiation resistance of the devices.

Description

A power electronic chip terminal protection structure

technical field

The invention relates to the technical field of semiconductors, in particular to a power electronic chip terminal protection structure.

Background technique

If no special terminal design is carried out, usually the power electronic chip will break down first at the terminal before reaching the breakdown voltage of the primary cell. On the one hand, most terminals are cylindrical junctions or spherical junctions with a small radius of curvature, so the electric field strength in this region is much higher than the parallel planar junctions in the original cell region, resulting in a decrease in the breakdown voltage of the device. On the other hand, it is inevitable to introduce mobile ions and fixed charges into the terminal surface medium in the process of manufacturing, and the surface charges at these terminals will directly affect the withstand voltage characteristics of the device. Therefore, in order to increase the breakdown voltage of power electronic chips as much as possible, the terminal structure should be designed reasonably. Some commonly used terminal structures are: Field Limiting Ring (FLR), Field Plate (FP), Junction Terminal Extension (JTE), etc. Among them, the Field Limiting Ring is widely used in power electronic chips of various voltage levels due to its relatively simple design and manufacturing process. are widely used.

For N-channel MOSFETs, P-type doped epitaxy is a common method for making trench MOSFETs, super junction power chips, etc. It is also used in semiconductor devices with weak implantation and diffusion capabilities such as silicon carbide (SiC), which can form deep The P-type well region helps to improve chip reliability. However, the P-type region formed by epitaxy is difficult to directly form a basic field-limiting ring termination structure, so it is necessary to use a mesa structure or a trench structure to redesign the termination.

The total dose effect (TID), as a cumulative degradation effect, refers to the degradation of the parameter performance of the device as the irradiation time goes by. Common TID effects include threshold voltage drift and off-state leakage current increase. In particular, the charge trapping effect of the dielectric in the terminal region makes the high-voltage leakage of the chip in the off state not only affected by the decrease of the threshold voltage, but also affected by the leakage of the terminal interface. The research on total dose reinforcement mainly focuses on structural improvement, process adjustment, layout optimization, application of new materials and proposal of new three-dimensional structure, etc., and in total dose reinforcement, both active area reinforcement and terminal structure reinforcement must be taken into consideration. At present, the commonly used termination structures of SiC power devices are mainly field-limiting rings or junction termination extensions JTE or a combination of the two. The upper part of the termination area is usually covered with a dielectric such as silicon dioxide as a passivation layer. A simple diode terminal structure is shown in Figure 1. There is an epilayer (epilayer) on the substrate, and there are multiple P-type doped regions (P ⁺ ) near the surface of the epitaxial layer. The leftmost The P ⁺ region is the main junction, and the multiple P ⁺ regions on the right are field-limiting rings. In Fig. 1, the limiting rings are distributed with equal width and equidistant distance, and the width (w) and spacing (d) of the limiting rings are fixed values. The top of the main junction is covered with an anode metal electrode (anode), the top of the field limiting ring is a silicon dioxide dielectric (SiO ₂ ), and the lower surface of the substrate is also a cathode metal electrode (cathode). However, during the total dose irradiation process of this structure, the dielectric in the terminal region of the device traps charges, so that the high-voltage leakage of the chip in the off state is not only affected by the decrease of the threshold voltage, but also by the leakage of the terminal interface. Therefore, in addition to considering the reduction of the threshold voltage of the primary cell region, it is also necessary to optimize the structure of the terminal region when the total dose is irradiated.

Contents of the invention

Technical purpose: Aiming at the problems in the prior art, the present invention discloses a terminal protection structure for power electronic chips. Using the trench structure in the terminal area, it can be compatible with the process of epitaxially forming the doped region of the second conductivity type, thus facilitating the formation The deeper second conductivity type region can be used as a terminal solution for trench type devices and super junction devices, and can improve the radiation resistance of devices.

Technical solution: In order to achieve the above technical purpose, the present invention adopts the following technical solutions.

A power electronic chip terminal protection structure, comprising:

a first conductivity type substrate;

a first conductivity type epitaxial layer drift region formed on the first conductivity type substrate;

a second conductivity type doped region formed on the drift region of the first conductivity type epitaxial layer;

Several trenches that run through the doped region of the second conductivity type and extend into the drift region of the epitaxial layer of the first conductivity type; after the doped region of the second conductivity type is divided by the grooves, it is close to the chip active The doped regions of the second conductivity type connected to each other constitute the main junction region of the chip terminal protection structure, except for the main junction region, other regions of the second conductivity type doped region constitute the terminal region;

In the drift region of the epitaxial layer of the first conductivity type, a junction protection region of the second conductivity type is formed under the trench;

completely filling the trench and covering part of the main junction region, all or part of the passivation layer of the termination region;

An anode metal electrode covering all or part of the main junction region and part of the passivation layer;

A cathode metal electrode formed on the lower surface of the substrate of the first conductivity type.

Preferably, the longitudinal depth of the doped region of the second conductivity type is greater than 0.5 μm, and the doped region of the second conductivity type is uniformly doped or non-uniformly doped.

Preferably, the dihedral angle formed by the side wall of the groove and the bottom of the groove ranges from 90° to 105°, and the longitudinal depth of the groove is greater than that of the second conductive layer adjacent to the side wall. The vertical depth of the type doped region, and the difference between the two is not less than 0.2 μm.

Preferably, when the chip terminal protection structure has multiple grooves, the grooves close to the active region are wide and deep; the grooves far away from the active region are small in width and shallow in depth.

Preferably, the junction protection zone of the second conductivity type adopts multiple field limiting ring structures, a single junction terminal extension structure, multiple junction terminal extension structures, or a combination of junction terminal extension structures and field limitation ring structures.

Preferably, when the junction protection region of the second conductivity type adopts a plurality of field limiting ring structures, the field limiting rings are doped with the second conductivity type, and the junction depth of the field limiting rings ranges from 0.5 μm to 1.5 μm.

Preferably, when the junction protection region of the second conductivity type adopts a plurality of field limiting ring structures, a shallow trench is provided outside the outermost field limiting ring, and the shallow trench etches the doped region of the second conductivity type but does not penetrate , at this time, a junction-terminated extended JTE structure is formed outside the field-limiting ring.

Preferably, the distance difference between the upper surface of the junction protection region of the second conductivity type and the lower surface of the doped region of the second conductivity type ranges from 0.2 um to 2 um.

Beneficial effect:

(1) The present invention utilizes the trench structure of the terminal region, which is compatible with the process of epitaxially forming the doped region of the second conductivity type, thereby facilitating the formation of a deeper region of the second conductivity type, and can become a trench device and a super junction device Terminal scheme, and can improve the anti-radiation ability of the device;

(2) The terminal method of the present invention based on the trench and the field limiting ring increases the length of the near-surface path, makes the formation of the leakage path more difficult, and is beneficial to suppress the terminal leakage caused by the interface charge in the terminal area, especially the total dose radiation of the device. The problem of increased terminal leakage caused by lighting;

(3) By setting trenches with different line widths in the present invention, the loading effect of etching can be used in the etching process to achieve deep trenches near the active area and shallow trenches far away from the active area, which can be better Avoid the concentration of electric field, increase the process window and the terminal protection ability of the device;

(4) The present invention can be used in combination with the table top structure and the junction terminal expansion structure to further improve the protection effect.

Description of drawings

FIG. 1 is a schematic diagram of a traditional protection structure of a power electronic chip terminal based on a field limiting ring in the prior art;

Fig. 2 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 1;

Fig. 3 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 2;

Fig. 4 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 3;

Fig. 5 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 4;

Fig. 6 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 5;

Fig. 7 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 6;

Fig. 8 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 7;

Fig. 9 is a schematic diagram of the terminal protection structure of the power electronic chip in embodiment 8;

FIG. 10 is a schematic diagram of the terminal protection structure of the power electronic chip in Embodiment 9;

Fig. 11 is a simulation curve of breakdown characteristics of a traditional terminal structure of a 1200V SiC power chip and a terminal protection structure based on the present invention;

Figure 12 is a simulation diagram of potential distribution under the critical breakdown voltage of a traditional terminal structure of a 1200V SiC power chip;

Fig. 13 is a simulation diagram of the potential distribution of a 1200V SiC power chip based on the terminal protection structure of the present invention under the critical breakdown voltage;

Among them, 1. The substrate of the first conductivity type; 2. The drift region of the epitaxial layer of the first conductivity type; 3. The doped region of the second conductivity type; 4. The trench; 41. The main junction region; 42. The terminal region; 5. 6. Passivation layer; 7. Anode metal electrode; 8. Cathode metal electrode; 9. Shallow trench.

Detailed ways

A power electronic chip terminal protection structure of the present invention will be further explained and described below in conjunction with the drawings and embodiments.

Embodiment 1: As shown in Figure 2, a power electronic chip terminal protection structure, including:

a first conductivity type substrate 1;

The drift region 2 of the epitaxial layer of the first conductivity type formed on the substrate 1 of the first conductivity type; the substrate 1 of the first conductivity type and the drift region 2 of the epitaxial layer of the first conductivity type are made of silicon carbide material.

A second conductivity type doped region 3 formed on the drift region 2 of the first conductivity type epitaxial layer;

Several trenches 4 that run through the doped region 3 of the second conductivity type and extend into the epitaxial layer drift region 2 of the first conductivity type; after the doped region 3 of the second conductivity type is divided by the trenches 4 The doped regions of the second conductivity type that are close to the active region of the chip and connected to each other constitute the main junction region 41 of the chip terminal protection structure, except for the main junction region 41, other regions of the doped region of the second conductivity type constitute the terminal region 42;

In the drift region 2 of the epitaxial layer of the first conductivity type, a junction protection region 5 of the second conductivity type is formed under the trench 4;

completely filling the trench 4, and covering part of the main junction region 41, the passivation layer 6 of all or part of the termination region 42;

An anode metal electrode 7 covering all or part of the main junction region 41 and part of the passivation layer 6;

A cathode metal electrode 8 formed on the lower surface of the substrate 1 of the first conductivity type.

The substrate 1 of the first conductivity type and the drift region 2 of the epitaxial layer of the first conductivity type may be silicon materials, or wide bandgap semiconductor materials such as silicon carbide, gallium arsenide, silicon nitride, gallium oxide, and diamond.

The vertical depth of the doped region 3 of the second conductivity type is greater than 0.5 μm, the doped region 3 of the second conductivity type is uniformly doped or non-uniformly doped, and the average doping concentration range is 1E16cm ^-3 ~ 2E18cm ^-3 . Preferably, the longitudinal depth range of the doped region 3 of the second conductivity type is 1.5 μm to 4 μm, the doped region 3 of the second conductivity type is non-uniformly doped along the vertical direction, and the doping concentration is high close to the position above the structure, far away from Sites above the structure have low doping concentrations.

The upper surface of the junction protection region 5 of the second conductivity type is lower than the lower surface of the doped region 3 of the second conductivity type, and the difference distance is not less than 0.2 μm, and the specific range is 0.2 μm to 2 μm, which is used to realize the terminal Effective protection, significantly increased breakdown voltage.

The angle range of the dihedral angle formed by the side wall of the groove 4 and the bottom of the groove 4 is 90° to 105°, and the longitudinal depth of the groove 4 is greater than that of the second conductive layer adjacent to the side wall. The vertical depth of the type doped region 3, and the difference between the two is not less than 0.2 μm, which is used to achieve effective protection of the terminal and significantly increase the breakdown voltage. If the upper surface of the junction protection zone 5 of the second conductivity type is flush with the lower surface of the trench 4, that is, when the junction protection zone 5 of the second conductivity type is in contact with the trench 4, the longitudinal depth of the trench 4 is the same as that of the adjacent second junction protection zone. The difference between the longitudinal depths of the doped regions 3 of the conductivity type is not less than 0.2 μm. If the upper surface of the junction protection region 5 of the second conductivity type is higher than the lower surface of the trench 4, the longitudinal depth of the trench 4 is the same as that of the adjacent second The difference between the longitudinal depths of the conductivity-type doped regions 3 is larger.

When the chip terminal protection structure is multi-groove, the grooves 4 close to the active area are wide and deep; the grooves 4 away from the active area are small in width and shallow in depth.

In a preferred solution, the groove 4 is a plurality of grooves with the same size, and the distance between the grooves is not equal. The distance between the grooves near the main junction region 41 is relatively narrow, and the distance between the grooves at a position far away from the main junction region 41 is relatively narrow. Wider, the sidewall of the trench is perpendicular to the bottom, and the longitudinal depth of the trench 4 is greater than the longitudinal depth of the second conductivity type doped region 3 adjacent to its sidewall, and the difference between the two ranges from 0.5 μm to 4 μm.

The junction protection zone 5 of the second conductivity type may be a plurality of field limiting ring structures, a single junction terminal extension structure, a plurality of junction termination extension structures, or a combination of junction termination extension structures and field limitation ring structures, etc.

When the second conductivity type junction protection zone 5 adopts a plurality of field limiting ring structures, the field limiting ring is doped with the second conductivity type, the upper surface of the field limiting ring is flush with the bottom of the trench 4, and the field limiting ring is The ring junction depth is 0.5μm~1.5μm.

The junction protection region 5 of the second conductivity type may be directly connected to the trench 4 or may not be directly connected to the trench 4 .

The projection of the anode metal electrode 7 in the vertical direction covers part of the termination area 42 , and the coverage width ranges from 1 μm to 5 μm. The anode metal electrode 7 is a Ni/Al composite metal, and the total thickness of the metal is greater than 1 μm.

The cathode metal electrode 8 is a Ni/Ag composite metal, and the total thickness of the metal is greater than 0.5 μm.

The passivation layer 6 is SiO ₂ , or a composite structure of SiO ₂ and Si ₃ N ₄ , in some specific scenarios, the passivation layer 6 adopts a composite structure of SiO ₂ and Si ₃ N ₄ , and the thickness of SiO ₂ is 0.1 μm~1μm, Si ₃ N ₄ thickness is 0.5μm~1μm. In some other embodiments of the present invention, conductive doped polysilicon and the like may also be wrapped in the passivation layer 6 .

The overlapping width of the anode metal electrode 7 and the terminal region 42 in the vertical direction is no more than 5 μm.

In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

The present invention provides a power electronic chip terminal protection structure capable of resisting total dose radiation. Using the trench structure of the terminal area, it can be compatible with the process of epitaxially forming the second conductivity type doped area, so as to facilitate the formation of deeper The second conductivity type region can be a terminal solution for trench devices and super junction devices. In the present invention, trenches 4 are used to divide the second conductivity type doped region 3 to improve the radiation resistance of the device. The invention is applicable to semiconductor power devices, and can be extended to triodes, field effect transistors, IGBTs, etc., and cooperates with the original cell structure of radiation resistance, such as the device in patent CN2022108355406, which greatly improves the overall radiation resistance of the device. In addition, the termination method based on trenches and field-limiting rings increases the near-surface path length, making the formation of leakage paths more difficult, which is conducive to suppressing the terminal leakage caused by interface charges in the termination region, especially the total dose of the device. Increased terminal leakage problem. Further, by setting trenches with different line widths, the loading effect of etching can be used in the etching process to achieve deep trenches near the active area and shallow trenches away from the active area, which can better avoid electric field Focus on increasing the process window and the terminal protection capability of the device. The present invention can be used in combination with the table top structure and the junction terminal extension structure to further improve the protection effect.

Embodiment 2: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 3, is basically the same as Embodiment 1, the difference is that the upper surface of the second conductivity type junction protection area 5 is higher than the The bottom surface of the trench 4 is described above, and the difference is 0-0.2 μm.

Embodiment 3: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 4, is basically the same as Embodiment 2, the difference is that the side wall of the groove 4 is not perpendicular to the bottom, and the dihedral angle formed It is 91°~95°.

Embodiment 4: A power electronic chip terminal protection structure of this embodiment, as shown in FIG. 5 , is basically the same as Embodiment 1, except that the groove 4 is a single groove, forming a mesa structure.

Embodiment 5: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 6, is basically the same as Embodiment 4, except that the junction protection region 5 of the second conductivity type is uniformly doped in the horizontal direction The junction terminal protection structure.

Embodiment 6: A power electronic chip terminal protection structure of this embodiment, as shown in FIG. Area uniformly doped junction termination protection structure.

Embodiment 7: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 8, is basically the same as Embodiment 4, except that the junction protection region 5 of the second conductivity type is uniformly doped in the horizontal direction Composite termination protection structure with junction termination and multiple field limiting rings.

Embodiment 2 to Embodiment 7 fully illustrate that the structure of the present invention is compatible with conventional traditional terminal protection structures.

Embodiment 8: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 9, is basically the same as Embodiment 1, the difference is that the plurality of groove structures are: grooves close to the active region Wide and deep groove after etching; the groove away from the active area has small groove width and small groove depth after etching. Therefore, the electric field broadening under reverse bias can be further optimized, and the electric field concentration effect can be suppressed.

Embodiment 9: A power electronic chip terminal protection structure of this embodiment, as shown in Figure 10, is basically the same as Embodiment 8, the difference is that there is an additional shallow groove 9 outside the outermost field limiting ring, the shallow groove The groove 9 etches the doped region 3 of the second conductivity type but does not penetrate through it. At this time, a junction terminal extension JTE structure is formed outside the field limiting ring to further improve the terminal protection capability.

Figure 11 is a simulation comparison of breakdown characteristic simulation curves between the terminal structure for 1200V SiC devices based on the structure of the present invention and the terminal structure of traditional 1200V SiC devices. The terminal structure for SiC devices, for example, when applied in MOSFET devices, corresponds to Figure 1, the corresponding Anode corresponds to the source (Source), and Cathode corresponds to the drain (Drain). The abscissa is the withstand voltage in the blocking state, and the ordinate is the cathode current in the blocking state. It can be seen that the terminal structure proposed by the present invention has the same withstand voltage level as the traditional terminal structure. From the comparison of the potential distribution in Figure 12 and Figure 13, it can be seen that Potential is used to indicate the potential (voltage); Vacuum is vacuum, which is used for structure definition; Conductor and Aluminum are used to define electrodes; the terminal structure of the present invention has a uniform potential distribution, and the chip is reversed When blocking high voltage resistance, the main electric field is borne by each field limiting ring, and the work of voltage division and terminal protection is well completed.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also possible. It should be regarded as the protection scope of the present invention.

Claims (8)

1. A power electronics chip terminal protection architecture, comprising:

a first conductivity type substrate (1);

a first conductivity type epitaxial layer drift region (2) formed on the first conductivity type substrate (1);

a second conductivity type doped region (3) formed on the first conductivity type epitaxial layer drift region (2);

a plurality of trenches (4) extending through the second conductivity type doped region (3) and into the first conductivity type epitaxial layer drift region (2); after the second conductive type doped region (3) is divided by the groove (4), the second conductive type doped regions which are close to the chip active region and are mutually communicated form a main junction region (41) of the chip terminal protection structure, and other regions of the second conductive type doped region except the main junction region (41) form a terminal region (42);

a second conductivity type junction protection region (5) formed below the trench (4) within the first conductivity type epitaxial layer drift region (2);

a passivation layer (6) completely filling the trench (4) and covering part of the main junction region (41), all or part of the termination region (42);

-an anode metal electrode (7) covering all or part of said main junction region (41), part of said passivation layer (6);

and a cathode metal electrode (8) formed on the lower surface of the first conductivity type substrate (1).

2. The power electronic chip terminal protection structure according to claim 1, wherein: the longitudinal depth of the second conductive type doped region (3) is larger than 0.5 mu m, and the second conductive type doped region (3) is uniformly doped or non-uniformly doped.

3. The power electronic chip terminal protection structure according to claim 1, wherein: the angle range of the dihedral angle formed between the side wall of the groove (4) and the bottom of the groove (4) is 90-105 degrees, the longitudinal depth of the groove (4) is larger than the longitudinal depth of the second conductive type doped region (3) at the adjacent position of the side wall of the groove, and the difference value of the two is not smaller than 0.2 mu m.

4. The power electronic chip terminal protection structure according to claim 1, wherein: when the chip terminal protection structure is a multi-groove, the groove width of the groove (4) close to the active area is large, and the groove depth is deep; the grooves (4) far from the active area are small in groove width and shallow in depth.

5. The power electronic chip terminal protection structure according to claim 1, wherein: the second conductivity type junction protection region (5) adopts a plurality of field limiting ring structures, a single junction terminal extension structure, a plurality of junction terminal extension structures or a combination of the junction terminal extension structure and the field limiting ring structure.

6. The power electronic chip terminal protection structure according to claim 1, wherein: when the second conductive type junction protection region (5) adopts a plurality of field limiting ring structures, the field limiting rings are doped with the second conductive type, and the junction depth range of the field limiting rings is 0.5-1.5 mu m.

7. The power electronic chip terminal protection structure according to claim 1, wherein: when the second conduction type junction protection region (5) adopts a plurality of field limiting ring structures, shallow grooves (9) are formed outside the field limiting ring at the outermost side, the shallow grooves (9) etch the second conduction type doped region (3) but do not penetrate through the second conduction type doped region, and then a junction terminal extension JTE structure is formed outside the field limiting ring.

8. The power electronic chip terminal protection structure according to claim 1, wherein: the difference value of the distances between the upper surface of the second conduction type junction protection region (5) and the lower surface of the second conduction type doping region (3) is 0.2-2 um.

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