CN116301564A - Storage controller and flash memory chip - Google Patents

Abstract

The invention discloses a memory controller and a flash memory chip, wherein the memory controller comprises a controller, a control register group and an execution circuit, a main program, a writing algorithm subprogram, an erasing algorithm subprogram and a reading algorithm subprogram which are arranged in the controller based on an instruction set are triggered through user instructions, corresponding execution data can be generated, then the control register group can generate corresponding enabling data according to the execution data, and then the execution circuit can control the reading and erasing operation of a memory unit according to the enabling data; meanwhile, when the capacity is upgraded, namely the number of the storage units is increased, only the electrical connection relation between the execution circuit and the newly-added storage units is increased, and the capacity can be expanded by adjusting corresponding subroutines, so that the method is more convenient compared with the large-scale change of the whole special circuit.

Description

Storage controller and flash memory chip

technical field

The invention relates to the technical field of storage, in particular to a storage controller and a flash memory chip.

Background technique

In the traditional technical solution, the controller of the memory chip usually realizes the read, write and erase operations through a dedicated circuit, but the algorithm based on the dedicated circuit is fixed. If the algorithm needs to be changed, the corresponding dedicated circuit needs to be adjusted. Therefore, it is not easy to upgrade The read/write algorithm is not easy to upgrade the storage capacity.

It should be noted that the above introduction about the background technology is only for the purpose of clearly and completely understanding the technical solution of the present invention. Therefore, it cannot be considered that the above mentioned technical solutions are known to those skilled in the art just because they appear in the background technology of the present invention.

Contents of the invention

The invention provides a storage controller and a flash memory chip to alleviate the technical problem that the storage controller composed of a dedicated circuit is inconvenient to upgrade algorithm and upgrade capacity.

In a first aspect, the present invention provides a storage controller, which includes a controller, a control register group, and an execution circuit, and the controller is used to execute a main program based on an instruction set setting, a write algorithm subroutine, and an erase algorithm in response to a user instruction. The program and the reading algorithm subroutine are used to generate corresponding execution data; the control register group is electrically connected to the controller for generating corresponding enable data according to the execution data; the execution circuit is electrically connected to the control register group for The data can control the read, erase and write operations of the storage unit.

In some of the embodiments, the execution circuit includes a high voltage generator, a row and column decoder, a static memory, and a sense amplifier, and the high voltage generator is electrically connected to the control register group for generating corresponding operating voltages; the row and column decoder It is electrically connected with the control register group for generating corresponding operation addresses; the static memory is electrically connected with the controller and the control register group for storing data to be written; the sense amplifier is electrically connected with the control register group for reading data in the storage unit.

In some of these implementations, the control register set includes a read control register, a write control register, and an erase control register, and the read control register is electrically connected to the high voltage generator, row and column decoder, and sense amplifier for enabling high voltage generation The device, row and column decoder and sense amplifier perform the read operation of the storage unit; the write control register is electrically connected with the high voltage generator, the row and column decoder and the static memory, and is used to enable the high voltage generator, the row and column decoder and the The static memory executes the write operation of the storage unit; the erase control register is electrically connected with the high voltage generator and the row and column decoder, and is used to enable the high voltage generator and the row and column decoder to perform the erase operation of the storage unit.

In some of these implementations, the control register set includes an over-erased correction control register, the over-erased correction control register is electrically connected to the controller, and the over-erased correction control register is used to control the over-erased correction operation of at least one storage unit .

In some of these implementations, the instruction set includes transfer instructions and bit operation instructions, each transfer instruction includes a 6-bit operation code and an 8-bit instruction address; each bit operation instruction includes 6 1-bit opcode and 8-bit register bit selection data.

In some implementations, the 6-bit opcode includes a 3-bit main opcode and a 3-bit sub-opcode.

In some of these implementations, the user instruction includes a read operation instruction; in response to the read operation instruction, the controller enables the high voltage generator to generate the corresponding read voltage by reading the control register based on the read algorithm subroutine, and enables the row and column decoder to generate the corresponding read voltage. The corresponding read unit address and the enable sense amplifier read out the data stored in the read unit address.

In some of these implementations, the read operation instruction includes a read command code and a read address code; in response to the read command code, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register based on the read algorithm subroutine; in response to To read the address code, the controller enables the row and column decoder to generate the corresponding read unit address through the read control register based on the read algorithm subroutine; under the supply of the read voltage, the controller enables the sense amplifier to read through the read control register based on the read algorithm subroutine. Read the data stored in the cell address.

In some of these implementations, the storage controller also includes a serial interface and a data conversion module, the data conversion module is electrically connected to the output terminal of the sense amplifier and the serial interface, and the controller enables the data conversion module to convert the parallel output of the sense amplifier. The data is the corresponding serial data, and the serial data is output to the outside through the serial interface.

In some of these implementations, the user instruction includes a write operation instruction; in response to the write operation instruction, the controller enables the static memory to store the data to be written by writing the control register based on the write algorithm subroutine, and enables the high voltage generator to generate the corresponding The write voltage enables the row and column decoder to generate a corresponding write unit address, so as to dump the data to be written in the static memory to the corresponding storage unit.

In some of these implementations, the write operation instruction includes a write command code, a write address code, and data to be written; in response to the write command code, the controller enables the static memory to store the data to be written by writing the control register based on the write algorithm subroutine and enabling the high voltage generator to generate a corresponding write voltage; in response to the write address code, the controller enables the row and column decoder to generate a corresponding write unit address based on the write algorithm subroutine through the write control register.

In some of these implementations, the user instruction includes an erase operation instruction; in response to the erase operation instruction, the controller enables the high voltage generator to generate the corresponding erase voltage through the erase control register based on the erase algorithm subroutine, and enables the row and column decoder to generate The corresponding erase unit address is used to erase the storage unit corresponding to the erase unit address.

In some of these implementations, the wipe operation instruction includes a wipe command code and a wipe address code; in response to the wipe command code, the controller enables the high voltage generator to generate a corresponding wipe voltage through the wipe control register based on the wipe algorithm subroutine; in response to Erase address code, the controller enables the row and column decoder to generate the corresponding erase unit address through the erase control register based on the erase algorithm subroutine.

In some of these implementations, the erase algorithm subroutine also includes an over-erase correction subroutine, and in response to the erase operation instruction, the controller performs over-erase on the erased memory cells through the over-erase correction control register based on the erase algorithm subroutine. Eliminate calibration subroutines.

In a second aspect, the present invention provides a flash memory chip, which includes the storage controller in at least one embodiment above and at least one storage unit, and the at least one storage unit is electrically connected to the execution circuit.

The storage controller and the flash memory chip provided by the present invention can generate corresponding execution data by triggering the main program, the write algorithm subroutine, the erase algorithm subroutine and the read algorithm subroutine set in the controller based on the instruction set through user instructions, and then The control register group can generate corresponding enable data according to the execution data, and then the execution circuit can control the read/write operation of the storage unit according to the enable data. On this basis, the corresponding subroutine can be adjusted flexibly and conveniently according to the needs of use , and there is no need to change the hardware configuration; at the same time, when upgrading the capacity, that is, increasing the number of storage units, it is only necessary to increase the electrical connection between the execution circuit and the newly added storage units, and other adjustments can be made through the corresponding subroutines Realizing expansion, in this way, is more convenient than large-scale changes of the entire dedicated circuit, and also simplifies the design scheme and reduces various costs.

Description of drawings

The technical solutions and other beneficial effects of the present invention will be apparent through the detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a flash memory chip provided by an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of the read control register shown in FIG. 1 .

FIG. 3 is a schematic structural diagram of the write control register shown in FIG. 1 .

FIG. 4 is a schematic structural diagram of the wipe control register shown in FIG. 1 .

FIG. 5 is a schematic structural diagram of the over-erasure correction control register shown in FIG. 1 .

FIG. 6 is a schematic flow chart of the operation of the flash memory chip shown in FIG. 1 .

FIG. 7 is a schematic flowchart of the reading algorithm subroutine shown in FIG. 6 .

FIG. 8 is a schematic flowchart of the writing algorithm subroutine shown in FIG. 6 .

FIG. 9 is a schematic flowchart of the erasing algorithm subroutine shown in FIG. 6 .

FIG. 10 is a schematic flowchart of the over-erasure correction subroutine shown in FIG. 9 .

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

In view of the above-mentioned technical problems that the storage controller composed of a dedicated circuit is inconvenient to upgrade the algorithm and upgrade the capacity, this embodiment provides a flash memory chip, please refer to Fig. 1 to Fig. 10, as shown in Fig. 1, the flash memory The chip includes a storage controller 100 and at least one serial interface 101 , and the at least one serial interface 101 is electrically connected with the storage controller 100 . Wherein, the flash memory chip may be, but not limited to, a Nor flash chip, or other memory chips applicable to the present invention.

As shown in Figure 1 and Figure 6, in one of the embodiments, this embodiment provides a storage controller 100, the storage controller 100 includes a controller 110, a control register set 191 and an execution circuit 192, the controller 110 uses In response to user instructions, execute the main program based on the instruction set, the write algorithm subroutine S20, the erase algorithm subroutine S30 and the read algorithm subroutine S10, to generate corresponding execution data; the control register group 191 is electrically connected to the controller 110 connected to generate corresponding enable data according to the execution data; the execution circuit 192 is electrically connected to the control register group 191 and used to control the read, erase and write operations of the storage unit according to the enable data.

The execution data may be logic data or control timing, and the data type of the execution data is not limited here.

It can be understood that the storage controller 100 and the flash memory chip provided in this embodiment trigger the main program, the write algorithm subroutine S20, the erase algorithm subroutine S30 and the read algorithm set based on the instruction set in the controller 110 through user instructions. Program S10 can generate corresponding execution data, and then the control register group 191 can generate corresponding enable data according to the execution data, and then the execution circuit 192 can control the read/write operation of the storage unit according to the enable data, on this basis, The corresponding subroutines can be adjusted flexibly and conveniently according to the needs of use, without changing the hardware configuration; at the same time, when upgrading the capacity, that is, increasing the number of storage units, it is only necessary to increase the power of the execution circuit 192 and the newly added storage units. Sexual connection relationship, and others can be expanded by adjusting the corresponding subroutines. In this way, compared with large-scale changes of the entire dedicated circuit, it is more convenient, and it also simplifies the design scheme and reduces various costs.

Wherein, the execution circuit 192 includes a high-voltage generator 120, a row-column decoder 130, a static memory 140, and a sense amplifier 150. The high-voltage generator 120 is electrically connected to the control register set 191 for generating corresponding operating voltages; the row-column decoder Encoder 130 is electrically connected with control register group 191 for generating corresponding operating addresses; static memory 140 is electrically connected with controller 110 and control register group 191 for storing data to be written; sense amplifier 150 and control register The group 191 is electrically connected for reading data in the memory cells.

In one of the embodiments, the control register group 191 includes a read control register 160, a write control register 170 and an erase control register 180, and the read control register 160 is electrically connected to the high voltage generator 120, the row and column decoder 130 and the sense amplifier 150 , used to enable the high voltage generator 120, the row and column decoder 130 and the sense amplifier 150 to perform the read operation of the storage unit; the write control register 170 is electrically connected to the high voltage generator 120, the row and column decoder 130 and the static memory 140 , used to enable the high voltage generator 120, the row and column decoder 130 and the static memory 140 to perform the write operation of the storage unit; the erase control register 180 is electrically connected with the high voltage generator 120 and the row and column decoder 130, and is used to The high-voltage generator 120 and the row-column decoder 130 can execute the erase operation of the memory cell.

As shown in Figure 2, in one of the embodiments, the read control register 160 includes a read enable operation bit, a read voltage start operation bit, a read preparation end operation bit, a read preprocessing operation bit and a read unit control bit, and the read enable The operation bit is used to control whether to perform a read operation; the read voltage start operation bit is used to control whether to start the read voltage of at least one storage unit; the read preparation end operation bit is used to control whether to end the read preparation operation of at least one storage unit; read preprocessing The operation bit is used to control whether to perform a read preprocessing operation on at least one storage unit; the read unit control bit is used to control whether to perform a read operation on the storage unit.

For example, the capacity of the read control register 160 can be at least 5bits (bits), preferably usually 8bits (bits), the 0th bit can be the read enable operation bit M_RDr, when it is 1, it means that at least one storage unit is allowed read operation; when it is 0, it means that the read operation of at least one storage unit is prohibited. The first bit may be the read voltage start operation bit M_PUMPr, when it is 1, it means that the read voltage of at least one memory cell is allowed to be started; when it is 0, it means that the read voltage of at least one memory cell is disabled. The second bit can be the read preparation end operation bit M_DISCHr. When it is 1, it means that it is allowed to end the read preparation operation of at least one storage unit; when it is 0, it means that it is prohibited to end the read preparation operation of at least one storage unit. The third bit may be the read preprocessing operation bit M_PREr. When it is 1, it indicates that the read preprocessing operation of at least one storage unit is allowed; when it is 0, it indicates that the reading preprocessing operation of at least one storage unit is prohibited. The fourth bit may be the read unit control bit M_CHARGEr. When it is 1, it means that the memory unit is allowed to be read; when it is 0, it means that the memory unit is prohibited from being read. The 5th to 7th bits are temporarily reserved (Reserved). Optionally, the user can define functions for the 5th to 7th bits.

It can be understood that, based on this embodiment, a read operation on at least one storage unit can be implemented.

As shown in FIG. 3 , in one of the embodiments, the write control register 170 includes a write enable operation bit, a write voltage start operation bit, a write preparation end operation bit, a write preprocessing operation bit, a write unit control bit, a first programming State enabling bit, the second programming state enabling bit and the third programming state enabling bit, the write enabling operation bit is used to control whether to carry out the write operation of at least one memory cell; the write voltage start operation bit is used to control whether to start at least The write voltage of a storage unit; the write preparation end operation bit is used to control whether to end the write preparation operation of at least one storage unit; the write preprocessing operation bit is used to control whether to perform the write preprocessing operation of at least one storage unit; the write unit control bit It is used to control whether to write to the memory cell; the first programming state enabling bit is used to control whether to perform the first programming state; the second programming state enabling bit is used to control whether to perform the second programming state; the third programming state enables The enable bit is used to control whether to perform the third programming state.

For example, the capacity of the write control register 170 can be at least 8bits (bits), and the 0th bit can be the write enable operation bit P_RDr. When it is 1, it means that the write operation of at least one storage unit is allowed; when it is 0 , indicating that the write operation of at least one storage unit is prohibited. The first bit may be the write voltage activation operation bit P_PUMPr. When it is 1, it means that the write voltage of at least one memory cell is allowed to be activated; when it is 0, it means that the write voltage of at least one memory cell is prohibited from being activated. The second bit can be the write preparation end operation bit P_DISCHr. When it is 1, it means that the write preparation operation of at least one storage unit is allowed to end; when it is 0, it means that the write preparation operation of at least one storage unit is prohibited. The third bit may be the write preprocessing operation bit P_PREr. When it is 1, it indicates that the writing preprocessing operation of at least one storage unit is allowed; when it is 0, it indicates that the writing preprocessing operation of at least one storage unit is prohibited. The fourth bit may be the write unit control bit P_CHARGEr, when it is 1, it means that the storage unit is allowed to be written; when it is 0, it means that the storage unit is prohibited from being written. The fifth bit may be the first programming state enable bit P_ST2, when it is 1, it means that the first programming state is allowed; when it is 0, it means that the first programming state is prohibited. The sixth bit may be the second programming state enable bit P_ST1, when it is 1, it means that the second programming state is allowed; when it is 0, it means that the second programming state is prohibited. The seventh bit may be the third programming state enable bit P_ST0, when it is 1, it means that the third programming state is allowed; when it is 0, it means that the third programming state is prohibited.

It can be understood that, based on this embodiment, a write operation to at least one storage unit can be implemented.

As shown in Figure 4, in one of the embodiments, the wipe control register 180 includes the wipe enable operation bit, the wipe voltage start operation bit, the wipe preparation end operation bit, the wipe preprocessing operation bit, the wipe unit control bit, the first wipe Erase state enable bit, the second erase state enable bit and the third erase state enable bit, the erase enable operation bit is used to control whether to perform an erase operation; the erase voltage start operation bit is used to control whether to start at least one storage The erase voltage of the unit; the erase preparation end operation bit is used to control whether to end the erase preparation operation of at least one memory cell; the erase preprocessing operation bit is used to control whether to perform the erase preprocessing operation of at least one memory cell; the erase unit control bit is used for Control whether to perform an erase operation on the storage unit; the first erase state enable bit is used to control whether to perform the first erase state; the second erase state enable bit is used to control whether to perform the second erase state; the third erase state The erase state enable bit is used to control whether to perform the third erase state.

For example, the capacity of the wiping control register 180 can be at least 8bits (bits), and the 0th bit can be the wiping enable operation bit E_RDr. When it is 1, it means that the wiping operation of at least one storage unit is allowed; when it is 0 , indicating that the erasing operation of at least one memory cell is prohibited. The first bit can be the erasing voltage start operation bit E_PUMPr, when it is 1, it means that the erasing voltage of at least one memory cell is allowed to be started; when it is 0, it means that the erasing voltage of at least one memory cell is disabled. The second bit can be the erase preparation end operation bit E_DISCHr. When it is 1, it means that it is allowed to end the erase preparation operation of at least one storage unit; when it is 0, it means that it is forbidden to end the erase preparation operation of at least one storage unit. The third bit can be the erase pre-processing operation bit E_PREr, when it is 1, it means that the erase pre-processing operation of at least one storage unit is allowed; when it is 0, it means that the erasing pre-processing operation of at least one storage unit is prohibited. The fourth bit can be the erasing unit control bit E_CHARGEr. When it is 1, it indicates that the erasing operation on the storage unit is allowed; when it is 0, it indicates that the erasing operation on the storage unit is prohibited. The fifth bit may be the enable bit E_ST2 of the first erasing state. When it is 1, it means that the first erasing state is allowed; when it is 0, it means that the first erasing state is prohibited. The sixth bit may be the second erasing state enable bit E_ST1, when it is 1, it means that the second erasing state is allowed; when it is 0, it means that the second erasing state is prohibited. The seventh bit may be the third erasing state enabling bit E_ST0. When it is 1, it means that the third erasing state is allowed; when it is 0, it means that the third erasing state is prohibited.

It can be understood that, based on this embodiment, an erasing operation on at least one storage unit can be implemented.

As shown in Figure 5, in one of the embodiments, the over-erasing correction control register 190 includes an over-erasing correction enabling operation bit, an over-erasing correction voltage start operation bit, an over-erasing correction preparation end operation bit, an over-erasing correction In addition to correcting the preprocessing operation bit, over-erasing correction unit control bit, the first over-erasing correction state enabling bit, the second over-erasing correction state enabling bit, and the third over-erasing correction state enabling bit, over-erasing In addition to the correction enable operation bit is used to control whether to perform an erase correction operation; the over-erase correction voltage start operation bit is used to control whether to start the over-erase correction voltage of at least one memory cell; the over-erase correction preparation end operation bit is used It is used to control whether to end the over-erase correction preparation operation of at least one memory cell; the over-erase correction pre-processing operation bit is used to control whether to perform the over-erase correction pre-processing operation of at least one memory cell; the over-erase correction unit control bit is used It is used to control whether the memory cell has been erased and corrected; the first over-erased correction state enable bit is used to control whether the first over-erased correction state is performed; the second over-erased correction state enable bit is used to control whether The second over-erasure correction state is performed; the enable bit of the third over-erasure correction state is used to control whether to perform the third over-erasure correction state.

For example, the capacity of the over-erasing correction control register 190 can be at least 8bits (bits), and the 0th bit can enable the operation bit O_RDr for over-erasing correction, and when it is 1, it means that the over-erasing of at least one storage unit is allowed Except correction operation; when it is 0, it indicates that the over-erase correction operation of at least one memory cell is prohibited. The first bit can be the over-erasing correction voltage start operation bit O_PUMPr. When it is 1, it means that the over-erasing correction voltage of at least one memory cell is allowed to be started; Erase correction voltage. The 2nd bit can prepare the end operation bit O_DISCHr for over-erase correction, when it is 1, it means to allow the end of the over-erase correction preparation operation of at least one storage unit; when it is 0, it means to prohibit the end of at least one storage unit Prepare for operation by erasing calibration. The third bit can be the over-erasing correction pre-processing operation bit O_PREr, when it is 1, it means that the over-erasing correction pre-processing operation of at least one storage unit is allowed; when it is 0, it means that at least one storage unit is prohibited The over-erase correction preprocessing operation. The fourth bit can be the over-erasing correction unit control bit O_CHARGEr, when it is 1, it means that the over-erasing correction operation on the memory cell is allowed; when it is 0, it means that the memory cell is prohibited from performing an over-erasing correction operation. The 5th bit can be the first over-erasing correction state enable bit O_ST2, when it is 1, it means that the first over-erasing correction state is allowed; when it is 0, it means that the first over-erasing correction state is prohibited . The sixth bit can be the second over-erasing correction state enable bit O_ST1, when it is 1, it means that the second over-erasing correction state is allowed; when it is 0, it means that the second over-erasing correction state is prohibited . The 7th bit can be the third over-erasing correction state enabling bit O_ST0, when it is 1, it means that the third over-erasing correction state is allowed; when it is 0, it means that the third over-erasing correction state is prohibited .

It can be understood that, based on this embodiment, an over-erase correction operation for at least one storage unit can be implemented.

It should be noted that, in the above-mentioned embodiment, at least one serial interface 101 is electrically connected with the high voltage generator 120, the column decoder 130, the static memory 140 and the sense amplifier 150, so as to realize at least one serial interface 101 read and write operations.

Wherein, the storage controller 100 may further include a serial interface 101 and a data conversion module, and the data conversion module is electrically connected to the output terminal of the sense amplifier 150 , the serial interface 101 and the static memory 140 . The data conversion module is used for mutual conversion between serial data and parallel data. Under the enablement of the controller 110, the data conversion module can convert the serial data input by the serial interface 101 into corresponding parallel data, and then convert The parallel data is stored in the static memory 140; the data conversion module can also convert the parallel data output by the sense amplifier 150 into corresponding serial data, and then the serial interface 101 transmits the serial data to the outside. Based on this design, the storage controller 100 in this solution is compatible with existing serial peripheral interfaces, and can process data in parallel, making the whole process more efficient without making any changes to the peripherals.

Wherein, the data conversion module can be, but not limited to, disposed in the controller 110 , so that the occupied area of the storage controller 100 can be reduced. The data conversion module can also be set in the acceleration module 191, so that the serial-to-parallel conversion speed or efficiency can be improved.

Wherein, the serial interface 101 can be a serial peripheral interface (SPI, Serial Peripheral Interface), which is a high-speed, full-duplex, synchronous communication bus, and occupies only Four wires can save chip pins; the serial interface 101 can also be an IIC (Inter-Integrated Circuit Bus, integrated circuit bus) interface. The serial interface 101 may adopt a self-defined communication protocol or a standard communication protocol, which is not specifically limited here.

Wherein, the user instruction may include a read operation instruction, a write operation instruction and an erase operation instruction. The read operation instruction may include a read command code and a read address code. The write operation instruction includes a write command code, a write address code and data to be written. Erase operation instructions include erase command codes and erase address codes.

The read command code, write command code and wipe command code can be but not limited to 8bits, the read address code, write address code and wipe address code can be but not limited to 32bits, and the data to be written can be but not limited to one or more bytes.

Wherein, the controller 110 can also include a custom instruction set and a compiler, and the custom instruction set can include an unconditional jump instruction, a conditional jump instruction, a set instruction, a clear instruction, and a wait instruction, and the set instruction can be used To set one or more bits of a register, clear instructions can be used to clear one or more bits of a register. It can be understood that the above-mentioned main program, write algorithm subroutine S20 , erase algorithm subroutine S30 and read algorithm subroutine S10 can all be realized based on the self-defined instruction set. At the same time, the compiler can convert various types of instructions into corresponding machine codes. For example, assembly instructions can be converted into machine codes that can be recognized by the controller 110 to call the above-mentioned main program, write algorithm subroutine S20, erase algorithm Program S30 and the reading algorithm subroutine S10.

Wherein, the controller 110 may specifically be a micro-control chip, a central processing chip, or any one of a digital processing chip, an off-the-shelf programmable logic array, an off-the-shelf programmable logic device, and the like.

As shown in FIGS. 1 to 7 , in one embodiment, in response to the read operation instruction, the controller 110 enables the high voltage generator 120 to generate the corresponding read voltage by reading the control register 160 based on the read algorithm subroutine S10, enabling the The row-column decoder 130 can generate the corresponding read unit address and the sense amplifier 150 can be enabled to read the data stored in the read unit address.

Specifically, in response to the read command code, the controller 110 enables the high voltage generator 120 to generate a corresponding read voltage based on the read algorithm subroutine S10 through the read control register 160; in response to the read address code, the controller 110 generates the corresponding read voltage based on the read algorithm subroutine S10 enables the row and column decoder 130 to generate the corresponding read unit address by reading the control register 160; under the supply of the read voltage, the controller 110 enables the sense amplifier 150 to read the read unit address based on the read algorithm subroutine S10 by reading the control register 160 data stored in .

For example, as shown in Figure 7, the working process of the above-mentioned read algorithm subroutine S10 can be: the serial interface 101 receives the read operation instruction, and then starts the read operation process: then select the storage unit of the corresponding address, switch to The read operation of the storage unit; then perform data processing, that is, adjust the corresponding bit value of the read control register 160 through the corresponding instruction, and then enable the sense amplifier 150 to read the data in the storage unit to the controller 110; the corresponding instruction in the controller 110 Under the control, the parallel data is converted into serial data, and output to the outside through the serial interface 101 .

As shown in FIG. 1, FIG. 6 and FIG. 8, in one embodiment, in response to the write operation instruction, the controller 110 enables the static memory 140 to store the data to be written through the write control register 170 based on the write algorithm subroutine S20, The high voltage generator 120 is enabled to generate the corresponding write voltage, and the row and column decoder 130 is enabled to generate the corresponding write unit address, so as to transfer the data to be written in the static memory 140 to the corresponding serial interface 101 .

Specifically, in response to the write command code, the controller 110 enables the static memory 140 to store data to be written and enables the high voltage generator 120 to generate corresponding write voltages through the write control register 170 based on the write algorithm subroutine S20; For the address code, the controller 110 enables the row and column decoder 130 to generate the corresponding write unit address through the write control register 170 based on the write algorithm subroutine S20 .

For example, as shown in FIG. 8, the working process of the above-mentioned write algorithm subroutine S20 can be: the serial interface 101 receives the write operation command, and starts the write operation process: preparing data means preparing and starting the write voltage; The data in the storage unit is compared to obtain a comparison result; if the comparison result is that the data to be written has been stored in the storage unit, the writing operation ends. If the data to be written is not stored in the storage unit, then start and prepare the write voltage, and adjust the corresponding bit value of the write control register 170 by multiple instructions to control the high voltage generator 120 to start the charge pump to prepare for high voltage; Adjust the corresponding bit value of the write control register 170, write the first unit; start and prepare the write voltage again, adjust the corresponding bit value of the write control register 170 through multiple instructions, to control the high voltage generator 120 to start the charge pump to prepare High voltage; adjust the corresponding bit value of the write control register 170 through multiple instructions, and write to the second unit; then change the address of the write unit, and switch to the next storage unit for write operation through instructions.

It can be understood that, after the current write operation process ends, the controller 110 enters a waiting state until the serial interface 101 receives the next write operation instruction.

It should be noted that a write unit address can correspond to one or more units, for example, a write unit address can correspond to the first unit or the second unit, or a write unit address can also correspond to the first unit and the second unit at the same time. Second unit. Wherein, the storage space of the first unit or the second unit may be one bit or multiple bits, for example, it may be 16 bits, 32 bits, 64 bits, etc., and so on.

As shown in Fig. 1, Fig. 6 and Fig. 9, in one of the embodiments, in response to the wiping operation command, the controller 110 enables the high voltage generator 120 to generate the corresponding wiping control register 180 through the wiping control register 180 based on the wiping algorithm subroutine S30. The voltage enables the row-column decoder 130 to generate a corresponding erase unit address to erase the serial interface 101 corresponding to the erase unit address.

Specifically, in response to the wipe command code, the controller 110 enables the high voltage generator 120 to generate a corresponding wipe voltage through the wipe control register 180 based on the wipe algorithm subroutine S30; in response to the wipe address code, the controller 110 generates the corresponding wipe voltage based on the wipe algorithm subroutine S30 enables the row-column decoder 130 to generate a corresponding erase unit address through the erase control register 180 .

For example, as shown in Figure 9, the working process of the above-mentioned erasing algorithm subroutine S30 can be: the serial interface 101 receives the erasing operation instruction, and then starts the erasing operation process: first, adjust the corresponding bit of the write control register 170 by multiple instructions value, to realize the programming operation of the memory cell; then adjust the corresponding bit value of the erase control register 180 through multiple instructions to realize the erase operation of the memory cell; The instruction adjusts the corresponding bit value of the over-erasure correction control register 190 to implement the over-erasure correction operation on the storage unit.

It should be noted that, after the current erasing operation process ends, the controller 110 may enter a waiting state until the serial interface 101 receives the next erasing operation instruction.

Wherein, the working process of the over-erasing correction subroutine S31 can be as shown in Figure 10, specifically as follows:

First, start the over-erasure correction process; then set the start address of the over-erasure correction; then perform an over-erasure correction verification operation on the storage unit corresponding to the start address through instructions or programs, and obtain the verification operation result, and then complete through the instruction The comparison of the verification operation results; if the verification operation result is that no erasure has occurred, jump to the next address through the instruction, and judge whether the next address is the last address, and if so, end the over-erasure correction process ; If not, increase the address, and compare the corresponding verification operation results after adding the address, loop in turn, and directly increase to the last address. If the result of the verification operation is that over-erasing has occurred, adjust the corresponding bit value of the over-erased correction control register 190 through multiple instructions to program the corresponding storage bit. For example, bits 0 to 31 can be programmed sequentially, bits 32 to Program 63 bits, program 64 to 95 bits, and program 96 to 127 bits, etc., then discharge 0 to 127 bits these, and then jump to the compare step with the instruction.

Table 1-1

opcode(6bit) instruction address(8bit) opcode(6bit) bit-register(8bit)

Table 1-2

Table 1-3

In one embodiment, the above instruction set includes transfer instructions and bit manipulation instructions, wherein the transfer instructions may be control program transfer instructions, which may include unconditional transfer instructions and conditional transfer instructions. The bit operation instructions may include a set instruction and a clear instruction, the set instruction may be used to set one or more bits of the register, and the zero clear instruction may be used to clear one or more bits of the register. In this way, the code value on the corresponding bit in each register can be cleared or set. When there is a time interval between the execution of the transfer instruction and/or the bit operation instruction, the above-mentioned instruction set may properly configure a waiting instruction, and the waiting instruction is used to perform a waiting operation to bridge the above-mentioned time interval. Understandably, the waiting instruction is not necessary.

Specifically, in Table 1-1 as shown below, "opcode(6bit)" is used to indicate the 6-bit operation code in the control program transfer instruction or bit operation instruction, and "instruction address(8bit)" is used for Indicates the 8-bit instruction address in the control program transfer instruction, and "bit-register(8bit)" is used to indicate the 8-bit register bit selection data.

Among them, as shown in Table 1-2 and Table 1-3, the 6-bit opcode in Table 1-1 can also be divided into the 3-bit main opcode "opcode 3bit" and the 3-bit sub-opcode Opcode "sub-opcode 3bit". The "flagregister bit" in Table 1-2 can be specifically expressed as three combined bits corresponding to the third row to the tenth row in the second column of Table 1-3, which in turn correspond to different conditional jump instructions. The "address of the control register" in the fourth row in Table 1-2 can be specifically expressed as three combined bits corresponding to the eleventh to fourteenth rows in the second column in Table 1-3, and each combined bit A bit of a register can be identified and then set by the major opcode. The "address of the control register" in the fifth row in Table 1-2 can be specifically expressed as three combined bits corresponding to the fifteenth to eighteenth rows in the second column in Table 1-3, and each combined bit can be determined bit of a register, which is then cleared by the major opcode. In this way, the bit value of each register can be manipulated through the custom instruction set shown in Table 1-2 or Table 1-3, and then the read/write operation of the storage unit can be realized through the hardware logic circuit, and the storage can also be realized through the software algorithm. The read/write operation of the unit also provides convenience and possibility for the development of subsequent memory functions.

Since this patent only uses four control registers to control the subsequent read, write, erase, and over-erase correction operations, the hardware structure is simplified. At the same time, a simplified instruction set is used in conjunction with these four control registers. And bit operation instructions, and control program transfer instructions or bit operation instructions only use 6-bit opcodes to indicate the main operation of the memory, and also reduce the pressure on program operation.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

The storage controller and the flash memory chip provided by the embodiment of the present invention have been introduced in detail above. The principles and implementation methods of the present invention have been explained by using specific examples in this paper. The description of the above embodiments is only used to help understand the present invention. Technical solutions and their core ideas; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not The essence of the corresponding technical solutions deviates from the scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. A memory controller, comprising:

a controller for executing at least one of a main program, a writing algorithm subroutine, an erasing algorithm subroutine, and a reading algorithm subroutine set based on an instruction set in response to a user instruction to generate corresponding execution data;

the control register set is electrically connected with the controller and used for generating corresponding enabling data according to the execution data; and

and the execution circuit is electrically connected with the control register set and used for controlling the read-write operation of the storage unit according to the enabling data.

2. The memory controller of claim 1, wherein the execution circuit comprises:

the high voltage generator is electrically connected with the control register set and used for generating corresponding operation voltages;

the row-column decoder is electrically connected with the control register set and used for generating a corresponding operation address;

the static memory is electrically connected with the controller and the control register set and is used for storing data to be written; and

and the sense amplifier is electrically connected with the control register set and used for reading out the data in the memory unit.

3. The memory controller of claim 2, wherein the control register set comprises:

The read control register is electrically connected with the high voltage generator, the row-column decoder and the sense amplifier and is used for enabling the high voltage generator, the row-column decoder and the sense amplifier to execute the read operation of the memory unit;

the write control register is electrically connected with the high voltage generator, the row-column decoder and the static memory and is used for enabling the high voltage generator, the row-column decoder and the static memory to execute write operation of a storage unit; and

and the erasing control register is electrically connected with the high voltage generator and the row-column decoder and is used for enabling the high voltage generator and the row-column decoder to execute the erasing operation of the memory unit.

4. The memory controller of claim 3, wherein the set of control registers includes an over-erase correction control register electrically coupled to the controller, the over-erase correction control register to control over-erase correction operations of the at least one memory cell.

5. The memory controller of claim 1, wherein the instruction set includes a branch class instruction and a bit operation class instruction, each of the branch class instructions including a 6 bit opcode and an 8 bit instruction address; each of the bit operation class instructions includes a 6 bit opcode and 8 bit register bit select data.

6. The memory controller of claim 5, wherein the 6-bit opcode comprises a 3-bit main opcode and a 3-bit sub opcode.

7. The memory controller of claim 3, wherein the user instruction comprises a read operation instruction;

in response to the read operation instruction, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register, enables the row-column decoder to generate a corresponding read unit address, and enables the sense amplifier to read out data stored in the read unit address based on the read algorithm subroutine.

8. The memory controller of claim 7, wherein the read operation instruction comprises a read command code and a read address code;

in response to the read command code, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register based on the read algorithm subroutine;

in response to the read address code, the controller enables the rank decoder to generate a corresponding read cell address through the read control register based on the read algorithm subroutine;

The controller enables the sense amplifier to read out data stored in the read cell address through the read control register based on the read algorithm subroutine under the supply of the read voltage.

9. The memory controller of claim 2, further comprising a serial interface and a data conversion module, wherein the data conversion module is electrically connected to the output end of the sense amplifier and the serial interface, and the controller enables the data conversion module to convert parallel data output by the sense amplifier into corresponding serial data and output the serial data to the outside through the serial interface.

10. The memory controller of claim 3, wherein the user instruction comprises a write operation instruction;

in response to the write operation instruction, the controller enables the static memory to store data to be written through the write control register based on the write algorithm subroutine, enables the high voltage generator to generate corresponding write voltages, and enables the row-column decoder to generate corresponding write unit addresses so as to transfer the data to be written in the static memory to corresponding storage units.

11. The memory controller of claim 10, wherein the write operation instruction includes a write command code, a write address code, and the data to be written;

in response to the write command code, the controller enables the static memory to store data to be written and enables the high voltage generator to generate a corresponding write voltage through the write control register based on the write algorithm subroutine;

in response to the write address code, the controller enables the row and column decoder to generate a corresponding write unit address via the write control register based on the write algorithm subroutine.

12. The memory controller of claim 3, wherein the user instruction comprises a wipe operation instruction;

in response to the erase operation instruction, the controller enables the high voltage generator to generate a corresponding erase voltage through the erase control register based on the erase algorithm subroutine, and enables the row-column decoder to generate a corresponding erase unit address so as to erase a memory cell corresponding to the erase unit address.

13. The memory controller of claim 12, wherein the erase operation instruction includes an erase command code and an erase address code;

In response to the wipe command code, the controller enables the high voltage generator to generate a corresponding wipe voltage through the wipe control register based on the wipe algorithm subroutine;

in response to the erase address code, the controller enables the row and column decoder to generate a corresponding erase unit address through the erase control register based on the erase algorithm subroutine.

14. The memory controller of claim 4, wherein the erase algorithm subroutine further comprises an over-erase correction subroutine, the controller executing the over-erase correction subroutine on erased memory cells through the over-erase correction control register based on the erase algorithm subroutine in response to the erase operation instruction.

15. A flash memory chip, comprising:

the memory controller of any one of claims 1 to 14; and

and the at least one storage unit is electrically connected with the execution circuit.

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