CN116301292A - System on a chip, robot and operating method of the system on a chip - Google Patents

Abstract

The invention discloses a chip system, a robot and an operation method of the chip system, wherein the chip system comprises a CPU unit, a bus unit, an address remapping unit, a nonvolatile memory and a volatile memory; the CPU unit decides whether to run codes with the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state; the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in a first working state; the nonvolatile memory is used for directly running codes according to the target clock to realize low power consumption when the chip system is in the second working state. The chip system stores and operates codes through two different memories, and switches the operation storage mode through address remapping, so as to solve the problem of executing switching of codes under different working states.

Description

System on a chip, robot and operating method of the system on a chip

technical field

The invention relates to the technical field of power supplies, in particular to a chip system, a robot and an operation method of the chip system.

Background technique

For the SOC chip (System on Chip), different operating states will be set according to the needs of the work, and these different operating states include at least two states: operating state and standby state. When the SOC chip is in the running state, various modules are turned on, and the frequency of the system clock meets the requirements of the normal operation of the SOC chip; At this time, the overall power consumption of the SOC chip is much smaller than the overall power consumption in the running state, which plays a role in saving energy consumption. Entering a low-power standby state is relatively simple for a single-memory system, such as an MCU system. For more complex SOC systems, especially those with volatile memories such as external memory DDR, it is more difficult to implement, because if the DDR memory is not turned off in the low-power standby state, then the power Consumption is not low, can not effectively save energy consumption. Most of the programs of the SOC chip are in the DDR memory. If the DDR memory is turned off, the operation of most programs will be affected; if a special daemon program is made, it will run in the relatively small SRAM memory inside the SOC chip. In this way, two codes need to be maintained, one is the code running on the DDR memory when the SOC chip is working normally, and the other is the code running on the SRAM memory inside the SOC chip when the SOC chip is sleeping, which increases the development complexity.

Contents of the invention

In order to solve the above problems, the present invention provides a chip system, a robot and an operation method of the chip system. Concrete technical scheme of the present invention is as follows:

A system on a chip, the system on a chip comprising: a CPU unit, configured to determine whether to use a non-volatile memory or a volatile memory to run a code according to whether the chip system is in a first working state or a second working state; the volatile memory, Used to carry codes from the non-volatile memory to run when the chip system is in the first working state; the non-volatile memory is used to store the running code and run the code according to the target clock when the chip system is in the second working state The address remapping unit is used to switch the memory running code in the chip system and reset the address of the running code; wherein, the power consumption of the running code of the non-volatile memory is lower than that of the running code of the volatile memory, so The target clock mentioned above is the system clock when the chip system is in standby or sleep. The chip system stores and runs codes through two different memories, and switches the mode of running and storing through address remapping, so as to solve the problem of code execution switching under different working states; The power consumption of the running code of the non-volatile memory is lower than the power consumption of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the chip system can be reduced in the second working state. The power consumption is low, and the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient.

Further, the chip system further includes a bus unit, the CPU unit is connected to the address remapping unit and the external device through the bus unit, and the bus unit is used to transmit the electrical signal of the external device to the CPU unit or transmit the electrical signal of the CPU unit to the CPU unit. The electrical signal is transmitted to the address remapping unit. The CPU unit can receive and send information through the bus unit, which has a simple structure and effectively reduces the area of the chip system.

Further, when the chip system is switched from the first working state to the second working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit closes all the volatile memory, enable the non-volatile memory, and map the code initial running address of the non-volatile memory to the storage initial address of the code stored in the non-volatile memory, and then reduce the system The frequency of the clock enables the non-volatile memory to run codes according to the reduced frequency system clock to achieve low power consumption. Store the running code in the non-volatile memory, so that the running code will not be lost after the non-volatile memory is powered off, and switch the code address through the address mapping method, only one copy of the running code can realize the memory Switching to reduce the difficulty of developing and maintaining the running code. In the second working state, the code is run through the non-volatile memory with lower power consumption, thereby reducing the operating power consumption of the chip system in the second working state.

Further, when the chip system switches from the second working state to the first working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit enables all The volatile memory, mapping the initial running address of the code of the volatile memory to the storage initial address of the code stored in the non-volatile memory, so that the volatile memory is in the first working state in the chip system When, the code is carried from the non-volatile memory to run. When working normally, the volatile memory is used to carry codes from the non-volatile memory to run, so as to improve the response speed when the chip system is interrupted and the chip system works again.

A mobile robot includes the above chip system. The chip system possessed by the mobile robot stores and runs codes through two different memories, and switches the mode of running and storing through address remapping, so as to solve the problem of code execution switching under different working conditions; The power consumption of the running code of the non-volatile memory is lower than the power consumption of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the chip system can be reduced in the second working time. The power consumption of the state, and the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient. In the second working state, the code is run through the non-volatile memory with lower power consumption, thereby reducing the operating power consumption of the chip system in the second working state.

An operation method of a chip system, the operation method is used to make the above-mentioned chip system run, and the operation method includes the following steps: After the CPU receives a working state instruction through a bus unit, it judges whether the chip system performs working state switching; if When the chip system switches the working state, the CPU unit resets the address of the running code through the address remapping unit; if the chip system is switched to the first working state, the volatile memory starts The code is carried in the volatile memory to run; if the chip system is switched to the second working state, the non-volatile memory directly runs the code according to the target clock; wherein, the power consumption of the non-volatile memory running code The power consumption of running code is lower than that of the volatile memory, and the target clock is the system clock when the chip system is in standby or sleep. The chip system uses two different memories to store and run code, and through address remapping, switch the way of running and storing, so as to solve the problem of code execution switching under different working conditions; The power consumption of the running code of the volatile memory is lower than that of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the power consumption of the chip system in the second working state is reduced. Moreover, the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient.

Further, after the CPU unit receives the work state instruction through the bus unit, it judges whether the chip system switches the work state, including the following steps: after the chip system receives the work state instruction through the bus unit, it judges that the work state instruction is the first work state operation instruction or the second working state operation instruction; the chip system judges whether it needs to switch the working state according to the current working state and the working state instruction; if the chip system itself is currently in the first working state, then the After the chip system receives the second working state operation instruction, the chip system switches to the second working state; if the chip system itself is currently in the second working state, after the chip system receives the first working state operation instruction, The chip system switches to the first working state. The chip system determines whether its own working state needs to be switched according to the working state instruction, so that the chip system can quickly enter different working states, and has high practicability.

Further, when the chip system is switched from the first working state to the second working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit closes all the volatile memory, enable the non-volatile memory, and map the code initial running address of the non-volatile memory to the storage initial address of the code stored in the non-volatile memory, and then reduce the system The frequency of the clock enables the non-volatile memory to run code according to a system clock with a reduced frequency to achieve low power consumption, wherein the system clock with a reduced frequency is the system clock when the chip system is in standby or sleep. Store the running code in the non-volatile memory, so that the running code will not be lost after the non-volatile memory is powered off, and switch the code address through the address mapping method, only one copy of the running code can realize the memory Switching to reduce the difficulty of developing and maintaining the running code. In the second working state, the code is run through the non-volatile memory with lower power consumption, thereby reducing the operating power consumption of the chip system in the second working state.

Further, when the chip system switches from the second working state to the first working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit enables all The volatile memory, mapping the initial running address of the code of the volatile memory to the storage initial address of the code stored in the non-volatile memory, so that the volatile memory is in the first working state in the chip system When, the code is carried from the non-volatile memory to run. When working normally, the volatile memory is used to carry codes from the non-volatile memory to run, so as to improve the response speed when the chip system is interrupted and the chip system works again.

Further, the CPU unit judges whether the working state command is the first working state running command or the second working state running command, including the following steps: the CPU unit starts timing after receiving the information of the external device; If the CPU unit does not receive the information sent by the external device again within the specified time, the CPU unit judges that it has received the second working state operation command and enters the second working state; if within the set time, the CPU unit receives the external device again After the information is sent, the CPU unit resets the timing and restarts timing; if the CPU unit does not receive the second working state running command, the CPU unit judges that it has received the first working state running command. The periodic calculation method is used to enable the chip system to enter the second working state when it is not working, so as to reduce the operating power consumption of the chip system.

Further, when the CPU unit uses the volatile memory to run the code, it will detect whether the volatile memory is normal; if the volatile memory is normal, the volatile memory continues to run the code; if the volatile memory is not normal, Then the CPU unit issues an abnormal operation instruction, and switches the non-volatile memory to run the code. When an abnormality is detected in the memory where the code is running, switch to another normal memory to run the code to ensure that the chip system can work normally.

Further, when the CPU unit uses the non-volatile memory to run the code, it will detect whether the non-volatile memory is normal; if the non-volatile memory is normal, the non-volatile memory continues to run the code with low power consumption; If the volatile memory is abnormal, the CPU unit issues an abnormal operation command, wakes up the volatile memory, and then transfers the code from the non-volatile memory to the volatile memory, so that the volatile memory operates according to the target clock. When an abnormality is detected in the memory where the code is running, switch to another normal memory to run the code to ensure that the chip system can work normally.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of the operation flow of the chip system according to an embodiment of the present invention.

Implementation

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art would understand that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the embodiments.

In the description of this specification, reference to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" means that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

As used in this application, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, to mean "once determined" or "in response to the determination" or "once detected [the described condition or event] ]” or “in response to detection of [described condition or event]”.

For the SOC chip (System on Chip), different operating states will be set according to the needs of the work, and these different operating states include at least two states: operating state and standby state. When the SOC chip is in the running state, various modules are turned on, and the frequency of the system clock meets the requirements of the normal operation of the SOC chip; At this time, the overall power consumption of the SOC chip is much smaller than the overall power consumption in the running state, which plays a role in saving energy consumption. The first working state in this paper is the normal operation state of the chip system, the second working state is the standby state or sleep state of the chip system, the target clock is the system clock when the chip system is in standby or sleep, and the chip system is in the first working state The specific value of the frequency of the system clock in the second working state is determined by the operating frequency of the CPU unit in the first working state and the second working state. In the first working state, various modules are working, and the operating frequency of the CPU unit is higher High, the frequency of the system clock is also high, in the second working state, unnecessary modules are turned off, the working frequency of the CPU unit is low, and the frequency of the system clock is also relatively low.

As shown in Figure 1, a chip system includes a CPU unit (that is, the CPU in the figure), a bus unit (that is, the bus in the figure), an address remapping unit, a non-volatile memory, and a volatile memory , that is, the non-volatile memory is storage 1 in the figure, and the volatile memory is storage 2 in the figure, the CPU unit is connected to the address remapping unit through the bus unit, and the CPU unit is connected to the external device through the bus unit , the external device can be a computer, a mobile phone, a mobile robot, etc., which use smart chips; the address remapping unit is connected to the nonvolatile memory and the volatile memory respectively; the CPU unit is in the first The first working state or the second working state determines whether to use the non-volatile memory or the volatile memory to run the code; the volatile memory is used to read from the non-volatile memory when the chip system is in the first working state The non-volatile memory is used to run the code directly according to the target clock when the chip system is in the second working state to achieve low power consumption; the bus unit is used to transmit the electrical signal of the external device to the CPU unit or to transmit the electrical signal of the CPU unit to the address remapping unit; The code transfer address is set so that the volatile memory can transfer the code from the non-volatile memory to run after the chip system enters the first working state (address remapping: address mapping is one-to-one correspondence between addresses Meaning. Remapping is to redistribute this one-to-one relationship. Think of the memory as a black box with output and input ports, the input is the address, and the output is the data stored on the corresponding address. The storage unit of the data is generally byte. The storage unit of each byte corresponds to an address, when a legal address is input from the address bus of the memory, the data stored in the storage unit corresponding to the address will appear on the data bus); wherein, the non The power consumption of running codes in the volatile memory is lower than that of running codes in the volatile memory, and the target clock is a system clock when the chip system is in standby or sleep. The chip system stores and runs codes through two different memories, and switches the mode of running and storing through address remapping, so as to solve the problem of code execution switching under different working states; The power consumption of the running code of the non-volatile memory is lower than the power consumption of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the chip system can be reduced in the second working state. The power consumption is low, and the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient.

As one of the embodiments, the chip system further includes a bus unit, the CPU unit is connected to the address remapping unit and the external device through the bus unit, and the bus unit is used to transmit the electrical signal of the external device to the CPU unit or Transmits the electrical signal of the CPU unit to the address remapping unit. The CPU unit can receive and send information through the bus unit, which has a simple structure and effectively reduces the area of the chip system. After the CPU unit determines that the chip system switches the working state, it can send a corresponding enable signal to the memory through the bus unit to enable the corresponding memory. The CPU unit can receive and send information through the bus unit, which has a simple structure and effectively reduces the area of the chip system.

As one of the embodiments, when the chip system is switched from the first working state to the second working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit receives the enable signal Afterwards, close the volatile memory, enable the non-volatile memory, and map the code initial running address of the non-volatile memory to the storage initial address of the running code stored in the non-volatile memory , and then reduce the frequency of the system clock, so that the non-volatile memory runs codes according to the reduced frequency of the system clock to achieve low power consumption. Store the running code in the non-volatile memory, so that the running code will not be lost after the non-volatile memory is powered off, and switch the code address through the address mapping method, only one copy of the running code can realize the memory Switching to reduce the difficulty of developing and maintaining the running code.

As one of the embodiments, when the chip system switches from the second working state to the first working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit receives the enable signal Afterwards, the volatile memory is enabled, the code initial running address of the volatile memory is mapped to the storage initial address of the code stored in the non-volatile memory, so that the volatile memory is in the chip system In the first working state, the code is transferred from the non-volatile memory to run. When working normally, the volatile memory is used to carry codes from the non-volatile memory to run, so as to improve the response speed when the chip system is interrupted and the chip system works again.

The memory (Memory) is one of the most important functional units of the single-chip microcomputer. If there is a storage unit of information, it is necessary to assign a distinctive identifier to these units. This identifier is what we usually call an address code. For example, in the STM32 microcontroller (MCU) STM32F407, multiple types of Memory are integrated. The same type of Memory is a Memory Block (block 0 ~ block 7), each of which is assigned a continuous value, equal number of storage cells, The set of natural numbers expressed in hexadecimal is used as the address encoding of the Memory Block. The corresponding relationship between this natural number set and Memory Block is Memory Map (memory mapping), sometimes also called Address Map (address mapping). When working normally, the volatile memory is used to carry codes from the non-volatile memory to run, so as to improve the response speed when the chip system is interrupted and the chip system works again. In the second working state, in order to reduce the power consumption of the chip system, the volatile memory will be turned off, and the code and data stored in the volatile memory will be lost. In order to improve the response speed of the chip system, the first working state of the chip system will be , the code needs to be run through the volatile memory, so when the chip system enters the first working state from the second working state, it is necessary to establish between the code storage address of the nonvolatile memory and the code storage address of the volatile memory The mapping relationship corresponds the initial address of the running code in the volatile memory to the initial address of the running code stored in the non-volatile memory. When the chip system is working normally, the chip system accesses the initial address of the running code in the volatile memory. In fact, it is the code in the initial address of the running code that accesses the non-volatile memory. The code in the non-volatile memory is called by the volatile memory through the storage address corresponding to the code when the chip system is working normally, so as to carry the corresponding code. operation, so as to achieve the purpose of address mapping. The non-volatile memory will not lose data when it is powered off, so the running code is stored in the non-volatile memory. When the chip system enters the second working state from the first working state, the chip system turns off the volatile memory, reducing the system clock, and then make the code initial running address of the non-volatile memory and the storage initial address of the running code stored in the non-volatile memory to establish a mapping relationship, and then start running from the code initial running address of the non-volatile memory , non-volatile memory does not require code to be moved from volatile memory to run.

As one of the embodiments, the non-volatile memory is a Flash memory. Non-volatile memory (English: non-volatile memory, abbreviated as NVM) refers to a computer memory whose stored data does not disappear when the current is turned off. In non-volatile memory, according to whether the data in the memory can be rewritten to the standard at any time when using the computer, it can be divided into two categories of products, namely ROM and Flash memory. Flash memory (English: flash memory) is a form of electronic erasable programmable read-only memory that allows it to be erased or written multiple times during operation. This technology is mainly used for general data storage, as well as for exchanging and transmitting data between computers and other digital products, such as memory cards and USB flash drives.

As one of the embodiments, the volatile memory is DDR memory or SRAM memory. The full name of RAM (Random Access Memory) is Random Access Memory, which is equivalent to mobile storage on a PC and is used to store and save data. It can be read and written at any time, and RAM is usually used as a temporary storage medium for the operating system or other running programs (it can be called system memory). However, RAM cannot retain data when the power is turned off. If data needs to be saved, they must be written to a long-term storage (such as a hard disk). Because of this, RAM is sometimes called "variable memory." RAM memory can be further divided into static RAM (SRAM) and dynamic memory (DRAM). Due to its low price per unit capacity, DRAM is widely used as the main memory of the system. DDR=Double Data Rate double rate, DDR SDRAM=double rate synchronous dynamic random access memory, people are used to call it DDR, among them, SDRAM is the abbreviation of Synchronous Dynamic Random Access Memory, that is, synchronous dynamic random access memory. DDR SDRAM is the abbreviation of Double Data Rate SDRAM, which means double rate synchronous dynamic random access memory. DDR memory is developed on the basis of SDRAM memory and still uses the SDRAM production system. Therefore, for memory manufacturers, it is only necessary to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce cost.

A mobile robot includes the above chip system. The chip system possessed by the mobile robot stores and runs codes through two different memories, and switches the mode of running and storing through address remapping, so as to solve the problem of code execution switching under different working conditions; The power consumption of the running code of the non-volatile memory is lower than the power consumption of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the chip system can be reduced in the second working time. The power consumption of the state, and the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient. In the second working state, the code is run through the non-volatile memory with lower power consumption, thereby reducing the operating power consumption of the chip system in the second working state.

An operation method of a chip system, the operation method is used to make the above-mentioned chip system run, and the operation method includes the following steps: After the CPU receives a working state instruction through a bus unit, it judges whether the chip system performs working state switching; if When the chip system switches the working state, the CPU unit resets the address of the running code through the address remapping unit; if the chip system is switched to the first working state, the volatile memory starts The code is carried in the volatile memory to run; if the chip system is switched to the second working state, the non-volatile memory directly runs the code according to the target clock; wherein, the power consumption of the non-volatile memory running code The power consumption of running code is lower than that of the volatile memory, and the target clock is the system clock when the chip system is in standby or sleep. The chip system uses two different memories to store and run code, and through address remapping, switch the way of running and storing, so as to solve the problem of code execution switching under different working conditions; The power consumption of the running code of the volatile memory is lower than that of the running code of the volatile memory. By using the non-volatile memory to run the code in the target clock state, the power consumption of the chip system in the second working state is reduced. Moreover, the same running code can realize switching and running of different working states, the structure is simple, and the implementation is convenient.

As one of the embodiments, after the CPU unit receives the working state instruction through the bus unit, it judges whether the chip system switches the working state, including the following steps: after the chip system receives the working state instruction through the bus unit, it judges the working state instruction Is it the first working state operation instruction or the second working state operation instruction; the chip system judges whether it needs to switch the working state according to its current working state and the working state instruction; if the chip system itself is currently in the first working state state, after the chip system receives the second working state operation command, the chip system switches to the second working state; if the chip system itself is currently in the second working state, the chip system receives the first working state After the instruction is executed, the chip system switches to the first working state. The chip system determines whether its own working state needs to be switched according to the working state instruction, so that the chip system can quickly enter different working states, and has high practicability. After the CPU unit receives the operation instruction in the first working state through the bus unit, the CPU unit judges the current working state of the chip system; if the CPU unit judges that the chip system is currently in the first working state, the chip system does not switch the working state, Make the CPU unit continue to run the code through the volatile memory; if the CPU unit judges that the chip system is currently in the second working state, the chip system switches to the first working state, the CPU unit wakes up the chip system, and then makes the chip system After the volatile memory enters the first working state, the code is transferred from the non-volatile memory to run. After the CPU unit receives the second working state operation instruction through the bus unit, the CPU unit judges the current working state of the chip system; if the CPU unit judges that the chip system is currently in the first working state, the chip system switches to the second working state. state, the CPU unit is configured with an address remapping unit, so that the address remapping unit re-establishes the mapping relationship between the running address of the code and the storage address of the code, reduces the frequency of the system clock, closes the volatile memory, and makes the nonvolatile The non-volatile memory directly runs the code according to the target clock; if the CPU unit judges that the chip system is currently in the second working state, the chip system does not switch the working state, so that the CPU unit continues to directly run the code according to the target clock through the non-volatile memory to achieve low power consumption.

As one of the embodiments, when the chip system is switched from the first working state to the second working state, the CPU unit sends enable to the address remapping unit through the bus unit, and the address remapping unit receives the enable signal Afterwards, closing the volatile memory, enabling the non-volatile memory, and mapping the initial running address of the code of the non-volatile memory to the storage initial address of the code stored in the non-volatile memory, Then reduce the frequency of the clock of the system, so that the non-volatile memory runs the code according to the system clock after the frequency reduction to realize low power consumption standby, wherein the system clock after the frequency reduction is when the chip system is in standby or sleep system clock. Store the running code in the non-volatile memory, so that the running code will not be lost after the non-volatile memory is powered off, and switch the code address through the address mapping method, only one copy of the running code can realize the memory Switching to reduce the difficulty of developing and maintaining the running code. In the second working state, the code is run through the non-volatile memory with lower power consumption, thereby reducing the operating power consumption of the chip system in the second working state.

As one of the embodiments, when the chip system switches from the second working state to the first working state, the CPU unit sends an enable to the address remapping unit through the bus unit, and after the address remapping unit receives the enable signal, Enable the volatile memory, map the code initial running address of the volatile memory to the storage initial address of the code stored in the non-volatile memory, make the volatile memory in the first In the working state, the code is carried from the non-volatile memory to run. When working normally, the volatile memory is used to carry codes from the non-volatile memory to run, so as to improve the response speed when the chip system is interrupted and the chip system works again.

As one of the embodiments, the CPU unit judging whether the working state command is the first working state running command or the second working state running command includes the following steps: the CPU unit starts timing after receiving the information of the external device; If within the set time, the CPU unit does not receive the information sent by the external device again, the CPU unit judges that it has received the second working state operation command and enters the second working state; if within the set time, the CPU unit again After receiving the information sent by the external device, the CPU unit resets the timing and restarts the timing; if the CPU unit does not receive the second working state operation command, the CPU unit judges that it has received the first working state running command. The periodic calculation method is used to enable the chip system to enter the second working state when it is not working, so as to reduce the operating power consumption of the chip system.

As one of the embodiments, before the chip system works, it detects whether the non-volatile memory and the volatile memory are normal; if the non-volatile memory and the volatile memory are normal, the chip system works normally; If both the volatile memory and the volatile memory are abnormal, the system-on-a-chip will issue an abnormal operation command and stop working; if one of the non-volatile memory and the volatile memory is abnormal, the system-on-a-chip will issue an abnormal operation command and In both the first working state and the second working state, the code is run through the normal memory. The chip system detects the status of the memory before working to prevent problems in the memory and the chip system cannot work normally. Even if one memory is damaged, the system-on-a-chip can run in a different working state.

As one of the embodiments, when the CPU unit uses the volatile memory to run the code, it will detect whether the volatile memory is normal; if the volatile memory is normal, the volatile memory continues to run the code; If the memory is abnormal, the CPU unit will issue an abnormal operation command and switch the non-volatile memory to run the code. When an abnormality is detected in the memory where the code is running, switch to another normal memory to run the code to ensure that the chip system can work normally.

As one of the embodiments, when the CPU unit uses the non-volatile memory to run the code, it will detect whether the non-volatile memory is normal; if the non-volatile memory is normal, the non-volatile memory continues to operate with low power consumption code; if the non-volatile memory is abnormal, the CPU unit will issue an abnormal operation command, and wake up the volatile memory, and then transfer the code from the non-volatile memory to the volatile memory, so that the volatile memory will be clocked according to the target clock to run the code. When an abnormality is detected in the memory where the code is running, switch to another normal memory to run the code to ensure that the chip system can work normally.

Compared with the prior art, the beneficial effect of the present invention is that: the chip system described in this application uses two different memories to store and run codes, and through address remapping, the mode of running and storing can be switched to solve different working states. The following code execution switching problem; when an abnormality is detected in the memory that is running the code, switch to another normal memory to run the code to ensure the basic functions; on the target clock status line, the power consumption of the non-volatile memory to run the code The power consumption of running code is lower than that of volatile memory, which reduces the power consumption of the chip system running at low power consumption.

Apparently, the above-mentioned embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, and the technical solutions of the various embodiments can be combined with each other. In addition, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" appear in the embodiments, the directions indicated Or the positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. , and therefore cannot be construed as a limitation of the present invention. If terms such as "first", "second", and "third" appear in the embodiments, they are for the convenience of distinguishing related features, and cannot be understood as indicating or implying their relative importance, sequence or quantity of technical features.

In addition, in the description of the present invention, unless otherwise clearly stipulated and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense, for example, it can be a fixed connection or a detachable connection, or Integral connection; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and variants, the scope of the present invention is defined by the appended claims and their equivalents. changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (12)

1. A chip system, the chip system comprising:

the CPU unit is used for determining whether to run codes by the nonvolatile memory or the volatile memory according to whether the chip system is in the first working state or the second working state;

the volatile memory is used for carrying codes from the nonvolatile memory to run when the chip system is in the first working state;

a nonvolatile memory for storing the operation code and operating the code according to the target clock when the chip system is in the second working state;

An address remapping unit, configured to reset an address of an operating code when the system-on-chip switches the memory to operate the code;

the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy.

2. A chip system according to claim 1, characterized in that the chip system further comprises a bus unit, which is connected to the address remapping unit and the external device via the bus unit, the bus unit being arranged to transmit electrical signals of the external device to the CPU unit or to transmit electrical signals of the CPU unit to the address remapping unit.

3. The system on a chip of claim 2, wherein when the system on a chip is switched from the first operating state to the second operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, and the address remapping unit closes the volatile memory, enables the nonvolatile memory, maps a code initial operation address of the nonvolatile memory to a storage initial address of a code stored in the nonvolatile memory, and then reduces a frequency of a system clock, so that the nonvolatile memory operates the code according to the reduced frequency system clock.

4. The system on a chip of claim 2, wherein when the system on a chip is switched from the second operating state to the first operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, and the address remapping unit enables the volatile memory after receiving the enable signal, maps a code initial operation address of the volatile memory to a storage initial address of a code stored in the nonvolatile memory, and enables the volatile memory to operate by transferring the code from the nonvolatile memory when the system on a chip is in the first operating state.

5. A mobile robot, characterized in that it comprises a chip system according to any one of claims 1 to 4.

6. A method of operating a chip system, characterized in that the method of operating is for operating the chip system of any one of claims 1 to 4, said method of operating comprising the steps of:

after receiving the working state instruction through the bus unit, the CPU judges whether the chip system performs working state switching or not;

if the chip system is switched in working state, the CPU unit resets the address of the running code through the address remapping unit;

If the chip system is switched to a first working state, the volatile memory carries codes from the nonvolatile memory to operate;

if the chip system is switched to the second working state, the nonvolatile memory directly operates codes according to a target clock;

the power consumption of the nonvolatile memory operation code is lower than that of the volatile memory operation code, and the target clock is a system clock of the chip system in standby or dormancy.

7. The method according to claim 6, wherein the CPU unit determines whether the chip system performs the operation state switching after receiving the operation state instruction through the bus unit, comprising the steps of:

after the chip system receives the working state instruction through the bus unit, judging whether the working state instruction is a first working state operation instruction or a second working state operation instruction;

the chip system judges whether the chip system needs to switch the working state according to the current working state and the working state instruction;

if the chip system is in the first working state at present, the chip system is switched to the second working state after receiving the second working state operation instruction;

If the chip system is in the second working state at present, the chip system is switched to the first working state after receiving the operation instruction of the first working state.

8. The method according to claim 7, wherein when the chip system is switched from the first operating state to the second operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, the address remapping unit closes the volatile memory after receiving the enable signal, enables the nonvolatile memory, maps a code initial operation address of the nonvolatile memory to a storage initial address of a code stored in the nonvolatile memory, and then reduces a frequency of a system clock, so that the nonvolatile memory operates the code according to the reduced system clock, wherein the reduced system clock is a system clock of the chip system when the chip system is standby or dormant.

9. The method according to claim 7, wherein when the chip system is switched from the second operating state to the first operating state, the CPU unit sends an enable signal to the address remapping unit through the bus unit, and the address remapping unit starts the volatile memory after receiving the enable signal, maps the code initial operating address of the volatile memory to the storage initial address of the code stored in the nonvolatile memory, and makes the volatile memory carry the code from the nonvolatile memory to operate when the chip system is in the first operating state.

10. The method of claim 7, wherein the CPU unit determines whether the operation state instruction is a first operation state operation instruction or a second operation state operation instruction, comprising the steps of:

the CPU unit starts timing after receiving information of external equipment;

if the CPU unit does not receive the information sent by the external equipment again within the set time, the CPU unit judges that the CPU unit receives a second working state operation instruction and enters a second working state;

if the CPU unit receives the information sent by the external equipment again within the set time, the CPU unit clears the timing and restarts the timing;

and if the CPU unit does not receive the second working state operation instruction, the CPU unit judges that the CPU unit receives the first working state operation instruction.

11. The method according to claim 6, wherein the CPU unit detects whether the volatile memory is normal when running the code using the volatile memory;

if the volatile memory is normal, the volatile memory continues to run codes;

if the volatile memory is abnormal, the CPU unit sends out an abnormal working instruction and switches the nonvolatile memory to run codes.

12. The method according to claim 6, wherein the CPU unit detects whether the nonvolatile memory is normal when running the code using the nonvolatile memory;

if the nonvolatile memory is normal, the nonvolatile memory continues to run codes according to the target clock;

if the nonvolatile memory is abnormal, the CPU unit sends out an abnormal working instruction, wakes up the volatile memory, and then carries codes from the nonvolatile memory to the volatile memory so that the volatile memory operates according to a target clock.

Images