CN116301196A - Clock control circuit module, memory storage device and clock control method - Google Patents

Abstract

The invention provides a clock control circuit module, a memory storage device and a clock control method. The clock control circuit module is used for: generating a clock signal; receiving a first signal and the clock signal and sampling the first signal according to the clock signal to generate a first sampling signal and a second sampling signal; respectively obtaining first position information corresponding to a first transition point of a first target signal and second position information corresponding to a second transition point of a second target signal according to the first sampling signal and the second sampling signal; and evaluating a frequency offset state between the first signal and the clock signal according to the first position information and the second position information. Thus, the signal receiving quality of the signal receiving terminal can be improved.

Description

Clock control circuit module, memory storage device and clock control method

technical field

The invention relates to a clock control technology, in particular to a clock control circuit module, a memory storage device and a clock control method.

Background technique

Most signal receiving ends are equipped with a phase detector, which can be used to align the phase of the received data signal with the phase of the internal clock signal used to sample the data signal, thereby improving the sampling accuracy of the data signal Rate. However, as the transmission speed of the data signal becomes faster and faster, it becomes more and more difficult to align the phase of the data signal with the phase of the internal clock signal. In addition, once the frequency difference between the data signal and the internal clock signal is too large, the general phase detector cannot work smoothly. In order to improve the above-mentioned problems, some types of signal receivers are additionally equipped with a frequency detector to help reduce the frequency difference between the data signal and the internal clock signal.

Common frequency detectors include a frequency detector based on a reference clock signal (also called Clock FD) and a frequency detector based on a data signal (also called Data FD). The frequency detector based on the reference clock signal can track the frequency of the reference clock signal to correct the frequency of the internal clock signal, and then use the phase detector to align the phase of the received data signal with the phase of the internal clock signal. However, the use of this type of frequency detector still cannot solve the problem that the frequency of the data signal and the frequency of the reference clock signal are too large, which leads to the problem that the phase detector cannot work smoothly. On the other hand, the frequency detector based on the data signal can use a plurality of internal clock signals with different phases to sequentially sample the data signal and evaluate whether the frequency of the data signal is higher or lower than the frequency of the internal clock signal according to the sampling results. However, this type of frequency detector needs to use internal clock signals with various phases during operation, so it is not suitable for all types of signal receiving ends. All of the above-mentioned defects will lead to a decrease in the sampling accuracy of the data signal at the signal receiving end.

Contents of the invention

The invention provides a clock control circuit module, a memory storage device and a clock control method, which can improve the signal receiving quality of the signal receiving end.

An exemplary embodiment of the present invention provides a clock control circuit module, which includes a clock generation circuit, a sampling circuit and a control circuit. The clock generation circuit is used to generate a clock signal. The sampling circuit is used to sample the first signal according to the clock signal and generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, and the first sampling signal reflects a pair of the clock signal A first sampling result of a first target signal in the first signal, and the second sampling signal reflects a second sampling result of the clock signal on a second target signal in the first signal. The control circuit is connected to the clock generating circuit and the sampling circuit. The control circuit is used to: obtain the first position information corresponding to the first transition point of the first target signal and the position of the second target signal according to the first sampling signal and the second sampling signal respectively. second position information corresponding to a second transition point; and evaluating a frequency offset state between the first signal and the clock signal according to the first position information and the second position information.

In an exemplary embodiment of the present invention, the first position information reflects that the first transition point is located at a first position in the first sampling window of the clock signal, and the second position information reflects the A second transition point is located at a second location in a second sampling window of the clock signal.

In an exemplary embodiment of the present invention, the time length of the first sampling window is the same as the time length of the second sampling window.

In an exemplary embodiment of the present invention, the first position information includes a first count value, the second position information includes a second count value, and the control circuit according to the first position information and the second count value The operation of evaluating the state of the frequency offset between the first signal and the clock signal by position information includes: evaluating the The frequency offset state between the first signal and the clock signal.

In an exemplary embodiment of the invention, the difference is positively related to a frequency difference between the first signal and the clock signal.

In an exemplary embodiment of the present invention, the control circuit respectively obtains the first transition point corresponding to the first transition point of the first target signal according to the first sampling signal and the second sampling signal. The operation of the position information corresponding to the second transition point of the second target signal includes: continuously analyzing the sampling signal; in response to the sampling signal meeting a preset condition, determining detecting the first target signal in the first signal; in response to detecting the first target signal, obtaining the first position corresponding to the first transition point according to the first sampling result information; in response to the sampled signal meeting the preset condition again, it is determined that the second target signal in the first signal is detected; and in response to the detection of the second target signal, according to the The second sampling result obtains the second position information corresponding to the second transition point.

In an exemplary embodiment of the present invention, the control circuit is further configured to: control the clock generation circuit to adjust the frequency of the clock signal according to the frequency offset state.

In an exemplary embodiment of the present invention, the clock control circuit module is disposed in a memory storage device, and the first target signal and the second target signal are handshaked between the memory storage device and a host system stage received from the host system.

In an exemplary embodiment of the present invention, the control circuit includes a phase detector, a frequency detector and a low-pass filter. The low pass filter is connected to the phase detector, the frequency detector and the clock generation circuit. The phase detector is used for detecting a phase offset state between the first signal and the clock signal. The frequency detector is used for detecting the frequency offset state between the first signal and the clock signal. The low-pass filter is used for controlling the clock generation circuit to adjust the frequency of the clock signal according to a detection result of at least one of the phase detector and the frequency detector.

In an exemplary embodiment of the present invention, the frequency detector includes a delay line circuit, a target signal detector, a window mapper, an event memory and a decision circuit. The target signal detector is connected to the delay line circuit. The window mapper is connected to the delay line circuit and the target signal detector. The event memory is connected to the window mapper. The decision circuit is connected to the event memory. The delay line circuit is used for receiving the sampling signal. The target signal detector is used for detecting the first target signal and the second target signal in the first signal according to the sampled signal. The window mapper is configured to obtain the first position information in response to the first target signal and obtain the second position information in response to the second target signal. The event memory is used for storing the first location information and the second location information. The decision circuit is used to generate a control signal according to the first position information and the second position information, so as to control the low-pass filter to adjust the frequency of the clock signal.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, a memory control circuit unit, and a clock control circuit module. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The clock control circuit module is arranged in the connection interface unit. The clock control circuit module is used to: generate a clock signal; receive a first signal and the clock signal and sample the first signal according to the clock signal to generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, the first sampling signal reflects the first sampling result of the clock signal on the first target signal in the first signal, and the second sampling signal reflects the clock signal on the first sampling result The second sampling result of the second target signal in the first signal; respectively obtain the first position corresponding to the first transition point of the first target signal according to the first sampling signal and the second sampling signal information and second position information corresponding to a second transition point of the second target signal; and evaluating the distance between the first signal and the clock signal according to the first position information and the second position information frequency offset status.

In an exemplary embodiment of the present invention, the first position information includes a first count value, the second position information includes a second count value, and the clock control circuit module The operation of evaluating the state of the frequency offset between the first signal and the clock signal by the second position information includes: according to the difference between the first count value and the second count value, evaluating The frequency offset state between the first signal and the clock signal.

In an exemplary embodiment of the present invention, the clock control circuit module respectively obtains the corresponding values corresponding to the first transition point of the first target signal according to the first sampling signal and the second sampling signal. The operation of the second position information corresponding to the first position information and the second transition point of the second target signal includes: continuously analyzing the sampling signal; responding to the sampling signal meeting a preset condition , determine that the first target signal in the first signal is detected; in response to detecting the first target signal, obtain the first transition point corresponding to the first transition point according to the first sampling result position information; in response to the sampled signal meeting the preset condition again, it is determined that the second target signal in the first signal is detected; and in response to the detection of the second target signal, according to the The second sampling result obtains the second position information corresponding to the second transition point.

In an exemplary embodiment of the present invention, the clock control circuit module is further configured to: adjust the frequency of the clock signal according to the frequency offset state.

An exemplary embodiment of the present invention further provides a clock control method, which includes: generating a clock signal; receiving a first signal and the clock signal and sampling the first signal according to the clock signal to generate a sampling signal, wherein The sampling signal includes a first sampling signal and a second sampling signal, the first sampling signal reflects a first sampling result of the clock signal on the first target signal in the first signal, and the second sampling signal The signal reflects the second sampling result of the clock signal on the second target signal in the first signal; the first rotation of the first target signal is respectively obtained according to the first sampling signal and the second sampling signal first position information corresponding to a state point and second position information corresponding to a second transition point of the second target signal; and evaluating the first position information according to the first position information and the second position information The frequency offset state between the signal and the clock signal.

In an exemplary embodiment of the present invention, the first location information includes a first count value, the second location information includes a second count value, and the evaluation is based on the first location information and the second location information The step of said frequency offset state between said first signal and said clock signal includes evaluating said first signal and said second count value based on a difference between said first count value and said second count value. The frequency offset state between the clock signals.

In an exemplary embodiment of the present invention, the first position information and the first position information corresponding to the first transition point of the first target signal are respectively obtained according to the first sampling signal and the second sampling signal. The step of the second position information corresponding to the second transition point of the second target signal includes: continuously analyzing the sampling signal; in response to the sampling signal meeting a preset condition, determining that the The first target signal in the first signal; in response to detecting the first target signal, obtaining the first position information corresponding to the first transition point according to the first sampling result; in response The sampled signal meets the preset condition again, determining that the second target signal in the first signal is detected; and in response to detecting the second target signal, obtaining a corresponding signal according to the second sampling result The second position information at the second transition point.

In an exemplary embodiment of the present invention, the clock control method further includes: adjusting the frequency of the clock signal according to the frequency offset state.

In an exemplary embodiment of the present invention, the clock control method further includes: detecting a phase offset state between the first signal and the clock signal by a phase detector; detecting the first signal by a frequency detector a state of the frequency offset between a signal and the clock signal; and adjusting the frequency of the clock signal according to a detection result of at least one of the phase detector and the frequency detector.

In an exemplary embodiment of the present invention, the step of detecting, by the frequency detector, the state of the frequency offset between the first signal and the clock signal comprises: receiving the sampled signal; signal detection of the first target signal and the second target signal in the first signal; obtaining the first position information in response to the first target signal and obtaining in response to the second target signal the second location information; storing the first location information and the second location information; and generating a control signal according to the first location information and the second location information to adjust the clock signal frequency.

Based on the above, after receiving the first signal, the clock signal can be used to sample the first signal to generate the first sampling signal and the second sampling signal. In particular, the first sampled signal may reflect a first sampling result of the clock signal to a first target signal in the first signal, and the second sampled signal may reflect the clock signal to a second target signal in the first signal The second sampling result of . Then, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal can be separated according to the first sampling signal and the second sampling signal get. In addition, a frequency offset state between the first signal and the clock signal can be estimated based on the first location information and the second location information. Thus, the quality of signal reception at the signal receiving end can be improved.

Description of drawings

FIG. 1 is a schematic diagram of a clock control circuit module shown according to an exemplary embodiment of the present invention;

2 is a schematic diagram of sampling a first signal based on a plurality of sampling windows of a clock signal to generate a first sampling signal and a second sampling signal according to an exemplary embodiment of the present invention;

FIG. 3 is a schematic diagram of a clock control circuit module shown according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic diagram of a frequency detector shown according to an exemplary embodiment of the present invention;

5 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

Fig. 6 is a flowchart of a clock control method according to an exemplary embodiment of the present invention.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and description to refer to the same or like parts.

Several exemplary embodiments are proposed below to illustrate the present invention, but the present invention is not limited to the illustrated exemplary embodiments. Appropriate combinations are also allowed among exemplary embodiments. As used throughout this specification (including the claims), the term "attachment" may refer to any direct or indirect attachment means. For example, if it is described in the text that a first device is connected to a second device, it should be interpreted that the first device can be directly connected to the second device, or that the first device can be connected indirectly through other devices or some kind of connection means. Ground is connected to the second device. Additionally, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

FIG. 1 is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the clock control circuit module 10 includes a clock generation circuit 11 , a sampling circuit 12 and a control circuit 13 . The clock generating circuit 11 is used to generate a signal (also referred to as a clock signal) CLK. For example, the signal CLK can be generated by a voltage-controlled oscillator (VCO) in the clock generating circuit 11 or other types of oscillating circuits. Signal CLK may have a specific frequency.

The clock generation circuit 11 is connected to the sampling circuit 12 . The sampling circuit 12 is configured to receive a signal (also referred to as a first signal) S(1) and a signal CLK. For example, the signal S(1) is provided by an external device, and the signal CLK is provided by the clock generating circuit 11 . In addition, the signal S(1) also has a specific frequency. The frequency of the signal S(1) may be different from that of the signal CLK. For example, the frequency of the signal CLK may be higher than the frequency of the signal S(1).

The sampling circuit 12 can also be used to sample the signal S(1) according to the signal CLK and generate a sampled signal. For example, the sampling circuit 12 may sequentially sample the signal S(1) using the rising edge and/or the falling edge of the signal CLK to generate a sampled signal.

It should be noted that the sampled signal includes a signal (also referred to as a first sampled signal) SP(1) and a signal (also referred to as a second sampled signal) SP(2). The signal SP( 1 ) may reflect a sampling result (also called a first sampling result) of a specific signal (also called a first target signal) in the signal S( 1 ) by the signal CLK. The signal SP( 2 ) may reflect the sampling result (also called the second sampling result) of the signal CLK on another signal (also called the second target signal) in the signal S( 1 ). For example, the sampling circuit 12 can use the rising edge and/or falling edge of the signal CLK to sequentially sample the first target signal and the second target signal in the signal S(1), so as to generate the signals SP(1) and SP(2 ).

The control circuit 13 is connected to the clock generation circuit 11 and the sampling circuit 12 . The control circuit 13 is configured to receive the sampling signal (including the signals SP( 1 ) and SP( 2 )). The control circuit 13 can obtain the position information corresponding to the transition point (also referred to as the first transition point) of the first target signal (also referred to as The first location information) and the location information (also called second location information) corresponding to the transition point (also called the second transition point) of the second target signal. Then, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the first position information and the second position information. For example, the frequency offset state is related to the frequency difference between the signal S(1) and the signal CLK. Or, from another point of view, the frequency offset state may reflect or correspond to the frequency difference between the signal S(1) and the signal CLK.

In an exemplary embodiment, the sampling circuit 12 can sample the signal S(1) (including the first target signal and the second target signal) based on a plurality of sampling windows of the signal CLK and sequentially generate the signals SP(1) and SP(2). Therefore, the first position information may reflect that a transition point (namely the first transition point) of the first target signal is located at a specific position (also called a first sample window) of the signal CLK (also called first position). In addition, the second position information may reflect that a transition point of the second target signal (ie, the second transition point) is located at a specific position (also called the second sampling window) of the signal CLK in another sampling window (also called for the second position). The time length of the first sampling window is the same as the time length of the second sampling window.

In an exemplary embodiment, the first position information includes a count value (also referred to as a first count value), and the second position information includes another count value (also referred to as a second count value). The first count value corresponds to the first position. The second count value corresponds to the second position. The control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the difference between the first count value and the second count value. For example, the control circuit 13 may subtract the first count value from the second count value or subtract the second count value from the first count value to obtain the difference between the first count value and the second count value. Then, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the difference. For example, the difference may be directly related to the frequency difference between the signal S(1) and the signal CLK. For example, if the difference is larger, it means that the frequency difference between the signal S(1) and the signal CLK is larger.

In an exemplary embodiment, the control circuit 13 can continuously analyze the sampling signal generated by the sampling circuit 12 . For example, the control circuit 13 can determine whether the sampled signal meets a preset condition. In response to the sampled signal meeting the preset condition, the control circuit 13 may determine that the first target signal in the signal S(1) has been detected. In response to detecting the first target signal, the control circuit 13 may obtain first position information (eg, a first count value) corresponding to the transition point (ie, the first transition point) of the first target signal according to the first sampling result. Then, the control circuit 13 can continue to analyze the sampling signal generated by the sampling circuit 12 . In response to the sampled signal meeting the preset condition again, the control circuit 13 may determine that the second target signal in the signal S(1) has been detected. In response to detecting the second target signal, the control circuit 13 may obtain second position information (eg, a second count value) corresponding to the transition point (ie, the second transition point) of the second target signal according to the second sampling result. Then, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the first count value and the second count value.

In an exemplary embodiment, the control circuit 13 can determine whether there are a plurality of consecutive bits “1” (or “0”) in the sampling result corresponding to the sampling signal. In response to the presence of a plurality of consecutive bits "1" (or "0") in the sampling result, the control circuit 13 may determine that the sampling signal meets a preset condition. However, if there are no consecutive multiple bits “1” (or “0”) in the sampling result, the control circuit 13 may determine that the sampling signal does not meet the preset condition.

In an exemplary embodiment, the multiple consecutive bits "1" (or "0") may refer to a preset number of consecutive multiple bits "1" (or "0"). For example, the preset number may be 16, 32 or other numbers, which is not limited in the present invention. In addition, the consecutive multiple bits "1" (or "0") may be located in a single sampling window of the signal CLK or across multiple sampling windows of the signal CLK.

In an exemplary embodiment, the control circuit 13 can control the clock generation circuit 11 to adjust the frequency of the signal CLK according to the frequency offset state between the signal S( 1 ) and the signal CLK. For example, according to the frequency offset state, the control circuit 13 can generate a signal (also referred to as an adjustment signal) ADJ. The control circuit 13 can control the clock generation circuit 11 to adjust (eg increase or decrease) the frequency of the signal CLK through the signal ADJ. For example, assuming that the frequency offset state reflects that the frequency of the signal S(1) is higher than that of the signal CLK, the control circuit 13 can increase the frequency of the signal CLK through the signal ADJ to reduce the difference between the signal CLK and the signal S(1). the frequency difference between them. Alternatively, assuming that the frequency offset state reflects that the frequency of the signal S(1) is lower than the frequency of the signal CLK, the control circuit 13 can reduce the frequency of the signal CLK through the signal ADJ to reduce the difference between the signal CLK and the signal S(1). the frequency difference between them. Therefore, the frequency of the adjusted signal CLK can be closer to the frequency of the signal S(1), even completely the same as the frequency of the signal S(1). Compared with the unadjusted signal CLK, using the adjusted signal CLK to sample the data signal in the signal S(1) can effectively improve the sampling quality (eg sampling accuracy) of the data signal.

FIG. 2 is a schematic diagram of sampling a first signal based on a plurality of sampling windows of a clock signal to generate a first sampling signal and a second sampling signal according to an exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , it is assumed that the first target signal includes the signal ST(1) and the second target signal includes the signal ST(2). The signal ST(1) and the signal ST(2) can be carried in the signal S(1) in different time ranges. Signal ST(1) has the same frequency and/or waveform as signal ST(2). For example, in the signal S(1), the frequency of the signal ST(1) and the signal ST(2) may be lower than that of the rest of the signals, as shown in FIG. 2 . In addition, the frequency of the signal ST(1) and the signal ST(2) can be lower than the frequency of the signal CLK. In another exemplary embodiment, the signal ST(1) and the signal ST(2) can be a set of signals of a fixed pattern, for example, the signal ST(1) and the signal ST(2) can be respectively used to convey 16 or other numbers A sequence of consecutive 0/1s.

The sampling circuit 12 can sample the signal S(1) based on a plurality of consecutive sampling windows TW corresponding to the signal CLK. For example, in a certain sampling window TW, the signal CLK can be used to continuously sample the signal S(1) k times to obtain k sample values. k can be any integer greater than 1. The k sampling values can be reflected in the sampling window TW, and the signal S(1) is continuously sampled for k times by using the signal CLK.

In an exemplary embodiment, the signal SP(1) may reflect or present, in the sampling window TW(1) (ie, the first sampling window), the sampling result of the signal CLK on the signal ST(1) (ie, the first sampling result). For example, the signal SP(1) may reflect or show that in the sampling window TW(1), the sampling result of the signal CLK on the signal ST(1) includes n(1) consecutive bits "1" and m(1) consecutive "0" bits. In response to n(1) and/or m(1) being greater than a preset value (ie, the sampled signal meets a preset condition), the control circuit 13 may determine that the first target signal has been detected. In response to detecting the first target signal, the control circuit 13 can determine a count value (ie, the first count value) according to n(1) and/or m(1). For example, the first count value may be equal to n(1) or m(1). In particular, in the sampling window TW(1), the boundary positions of the n(1) consecutive bits "1" and m(1) consecutive bits "0" reflect the transition of the signal ST(1) The position of point TP(1) (ie the first transition point) (ie the first position). Or, from another point of view, the first count value may reflect the position of the transition point TP(1) of the signal ST(1) within the sampling window TW(1).

In an exemplary embodiment, the signal SP(2) may reflect or present, in the sampling window TW(2) (ie, the second sampling window), the sampling result of the signal CLK on the signal ST(2) (ie, the second sample result). For example, the signal SP(2) may reflect or show that in the sampling window TW(2), the sampling result of the signal CLK on the signal ST(2) includes n(2) consecutive bits "1" and m(2) consecutive "0" bits. In response to n(2) and/or m(2) being greater than the preset value (ie the sampled signal meets the preset condition again), the control circuit 13 may determine that the second target signal has been detected. In response to detecting the second target signal, the control circuit 13 can determine a count value (ie, the second count value) according to n(2) and/or m(2). For example, the second count value may be equal to n(2) or m(2). In particular, in the sampling window TW(2), the boundary positions of the n(2) consecutive bits "1" and m(2) consecutive bits "0" reflect the transition of the signal ST(2) The position of point TP(2) (ie the second transition point) (ie the second position). Or, from another point of view, the second count value may reflect the position of the transition point TP(2) of the signal ST(2) within the sampling window TW(2).

In an exemplary embodiment, the difference between n(1) and n(2) (that is, the difference between the first count value and the second count value) is positively related to the difference between the signal S(1) and the signal CLK the frequency difference between them. For example, a larger difference between n(1) and n(2) indicates a larger frequency difference between the signal S(1) and the signal CLK. Therefore, the control circuit 13 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the difference between n(1) and n(2). Then, the control circuit 13 can adjust the frequency of the signal CLK according to the frequency offset state. For example, assuming that n(1) is 4 and n(2) is 8, it means that the frequency of the signal CLK is higher than that of the signal S(1). Therefore, the control circuit 13 can instruct the clock generation circuit 11 to slightly reduce the frequency of the signal CLK. Alternatively, assuming that n(1) is 28 and n(2) is 6, it means that the frequency of the signal CLK is lower than that of the signal S(1). Therefore, the control circuit 13 can instruct the clock generation circuit 11 to slightly increase the frequency of the signal CLK. In addition, the adjustment range of the frequency of the signal CLK may also be positively related to the difference between n(1) and n(2) (ie the difference between the first count value and the second count value).

In an exemplary embodiment, the difference between m(1) and m(2) (ie, the difference between the first count value and the second count value) is also positively related to the signal S(1) and the signal CLK the frequency difference between them. For example, a larger difference between m(1) and m(2) indicates a larger frequency difference between the signal S(1) and the signal CLK. Therefore, the control circuit 13 can also evaluate the frequency offset state between the signal S(1) and the signal CLK according to the difference between m(1) and m(2). Then, the control circuit 13 can adjust the frequency of the signal CLK according to the frequency offset state.

FIG. 3 is a schematic diagram of a clock control circuit module according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , the clock control circuit module 30 includes a clock generation circuit 31 , an analog-to-digital converter (Analog-to-Digital Converter, ADC) 32 , a control circuit 33 and an equalizer 34 . The clock generation circuit 31 may include the clock generation circuit 11 of FIG. 1 . For example, the clock generating circuit 31 can be used to generate the signal CLK.

The analog-to-digital converter 32 is connected to the clock generation circuit 31 . The analog-to-digital converter 32 may include the sampling circuit 12 of FIG. 1 . For example, the analog-to-digital converter 32 can sample the signal S(1) according to the signal CLK and generate the signal S(2). The signal S(2) can reflect the sampling result of the signal S(1) by the signal CLK. For example, the signal S(2) may include the signal SP(1) (ie, the first target signal) and the signal SP(2) (ie, the second target signal) in FIG. 1 and/or FIG. 2 .

The control circuit 33 is connected to the analog-to-digital converter 32 and the clock generation circuit 31 . The control circuit 33 may include the control circuit 13 of FIG. 1 . The control circuit 33 can obtain the position information corresponding to the transition point of the first target signal (ie, the first transition point) and the transition point of the second target signal (ie, the first position information) according to the signal S(2). The position information corresponding to the second transition point (that is, the second position information). Then, the control circuit 33 can evaluate the frequency offset state between the signal S(1) and the signal CLK according to the first position information and the second position information. Then, the control circuit 33 can send the signal ADJ according to the frequency deviation state to instruct the clock generation circuit 31 to adjust the frequency of the signal CLK.

In an exemplary embodiment, the control circuit 33 includes a frequency detector 331 , a low-pass filter 332 and a phase detector 333 . The frequency detector 331 is connected to the analog-to-digital converter 32 . The frequency detector 331 can receive the signal S(2) and detect the frequency offset state between the signal S(1) and the signal CLK according to the signal S(2). For example, the frequency detector 331 can detect the state of the frequency offset between the signal S(1) and the signal CLK with reference to the description of the exemplary embodiments of FIG. 1 and FIG. 2 , and the description will not be repeated here.

The low pass filter 332 is connected to the frequency detector 331 and the phase detector 333 . The low-pass filter 332 can generate the signal ADJ according to the detection result of the frequency detector 331 to adjust the frequency of the signal CLK.

The phase detector 333 is connected to the analog-to-digital converter 32 and the low-pass filter 332 . The phase detector 333 can receive the signal S(2) and detect the phase shift state between the signal S(1) and the signal CLK according to the signal S(2). The phase offset state may reflect or correspond to the phase difference between the signal S(1) and the signal CLK. For example, the phase detector 333 can evaluate whether the phase of the signal S(1) leads or lags the phase of the signal CLK according to the continuous sampling results of the signal S(1) reflected by the signal CLK reflected by the signal S(2). The phase detector 333 may include any known phase detector, which will not be repeated here. Then, the low-pass filter 332 can generate the signal ADJ according to the detection result of the phase detector 333 to adjust the phase or frequency of the signal CLK.

In an exemplary embodiment, when the frequency and/or phase of the signal CLK is first calibrated, the control circuit 33 may first activate the frequency detector 331 to adjust the frequency of the signal CLK. For example, the starting frequency detector 331 may include turning on a signal path from the frequency detector 331 to the low-pass filter 332 and/or turning off a signal path from the phase detector 333 to the low-pass filter 332 . After starting the frequency detector 331, the control circuit 33 can detect the frequency offset state between the signal S(1) and the signal CLK through the frequency detector 331 and control the clock generation circuit 31 to adjust the signal CLK according to the frequency offset state. Frequency of. Therefore, when the frequency and/or phase of the signal CLK is first corrected, the control circuit 33 can give priority to reducing the frequency difference between the signal S(1) and the signal CLK.

After the frequency adjustment of the signal CLK is completed (eg, the frequency difference between the signal S(1) and the signal CLK is smaller than a preset value), the control circuit 33 can activate the phase detector 333 to adjust the phase of the signal CLK. For example, enabling the phase detector 333 may include turning on a signal path from the phase detector 333 to the low-pass filter 332 and/or turning off a signal path from the frequency detector 331 to the low-pass filter 332 . After starting the phase detector 333, the control circuit 33 can detect the phase offset state between the signal S(1) and the signal CLK through the phase detector 333 and control the clock generation circuit 31 to adjust the signal CLK according to the phase offset state. phase. Thus, the control circuit 33 can further reduce the phase difference between the signal S(1) and the signal CLK when the frequency correction of the signal CLK has been preliminarily completed.

An equalizer 34 is connected to the analog-to-digital converter 32 . The equalizer 34 can be used to compensate the output of the analog-to-digital converter 32 (ie, the signal S(2)). For example, the equalizer 34 may include a feed forward equalization (Feed Forward Equalization, FFE) equalizer and/or other types of equalizers.

In an exemplary embodiment, by sequentially adjusting the frequency and phase of the signal CLK, it is possible to effectively improve the conventional phase detector 333 that may be unable to perform due to the large phase difference or frequency difference between the signal S(1) and the signal CLK. Problems with normal functioning. In addition, during the operation of the frequency detector 331 , there is no need to introduce an additional reference clock signal or use a multi-phase signal CLK to sample the signal S(1), thereby effectively improving the versatility of the frequency detector 331 .

FIG. 4 is a schematic diagram of a frequency detector according to an exemplary embodiment of the present invention.

Referring to FIG. 3 and FIG. 4 , in an exemplary embodiment, the frequency detector 331 includes a delay line circuit 41 , a target signal detector 42 , a window mapper 43 , an event memory 44 and a decision circuit 45 . The delay line circuit 41 can be used to receive the signal S( 2 ) and provide the delayed signal S( 2 ) to the target signal detector 42 . The target signal detector 42 may analyze the delayed signal S(2) to detect whether the first target signal and/or the second target signal exist in the signal S(1). Taking FIG. 2 as an example, the target signal detector 42 can respectively detect the signals ST( 1 ) and ST( 2 ) according to the signals SP( 1 ) and SP( 2 ) meeting the preset conditions.

In an exemplary embodiment, in response to the presence of the first target signal in the signal S(1), the target signal detector 42 may notify the window mapper 43 to obtain the transition point of the first target signal (ie, the first transition point) The corresponding location information (that is, the first location information). For example, in response to the first notification from the target signal detector 42 , the window mapper 43 may store the first count value (ie, the first position information) in the event memory 44 . Later, in response to the target signal detector 42 determining that there is a second target signal in the signal S(1), the target signal detector 42 can notify the window mapper 43 again to obtain the transition point of the second target signal (ie, the second transition point state point) corresponding to the location information (that is, the second location information). For example, in response to the second notification from the target signal detector 42 , the window mapper 43 may store the second count value (ie, the second position information) in the event memory 44 .

In an exemplary embodiment, after storing the first count value (that is, the first position information) and the second count value (that is, the second position information) in the event memory 44 , the decision circuit 45 can according to the first count value in the event memory 44 The difference between a count value (ie, the first position information) and a second count value (ie, the second position information) generates a signal (also called a control signal) CT. The signal CT can be used to control the low-pass filter 332 in FIG. 3 to generate a corresponding signal ADJ to adjust the frequency of the signal CLK. In addition, other relevant operation details have been described in the foregoing exemplary embodiments, and will not be repeated here.

It should be noted that the internal structures of the clock control circuit module and the frequency detector shown in the exemplary embodiments of FIG. 1 , FIG. 3 and FIG. 4 are only examples, not intended to limit the present invention. That is, the connection relationship between the aforementioned clock control circuit module and each electronic circuit in the frequency detector can be adjusted according to practical requirements. In addition, the aforementioned clock control circuit module and frequency detector may also include other types of electronic circuits to provide additional functions, which is not limited by the present invention.

In an exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may be disposed in a memory storage device. Alternatively, in an exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may also be disposed in any type of electronic device, which is not limited by the present invention.

FIG. 5 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory storage device 50 includes a connection interface unit 501 , a memory control circuit unit 502 and a rewritable non-volatile memory module 503 . The aforementioned clock control circuit module 10 or 30 may be disposed in the memory storage device 50 .

The connection interface unit 501 is used to connect the memory storage device 50 to the host system 51 . The memory storage device 50 can communicate with the host system 51 through the connection interface unit 501 . In an exemplary embodiment, the connection interface unit 501 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 501 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (Universal Flash Storage , UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 501 can be packaged with the memory control circuit unit 502 in one chip, or the connection interface unit 501 can be arranged outside a chip including the memory control circuit unit 502 .

The memory control circuit unit 502 is connected to the connection interface unit 501 and the rewritable non-volatile memory module 503 . The memory control circuit unit 502 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 503 according to the instructions of the host system Works with Erase etc.

The rewritable non-volatile memory module 503 is used for storing data written by the host system 51 . The rewritable non-volatile memory module 503 may include a single-level storage unit (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a storage unit), a second-level Storage unit (MultiLevel Cell, MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a storage unit), triple level storage unit (Triple Level Cell, TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits in one storage unit), and a fourth-order storage unit (Quad Level Cell, QLC) NAND flash memory module (that is, a flash memory module that can store 4 bits in one storage unit) flash memory module), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 503 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage of the memory cell is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 503 has multiple storage states. Which storage state a memory cell belongs to can be determined by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

In an exemplary embodiment, the storage units of the rewritable non-volatile memory module 503 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, memory cells on the same word line can form one or more physical programming cells. If a memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a storage unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a storage unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit will be greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the programmatic unit.

In an exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming units are physical pages, these physical programming units may include data bit areas and redundancy (redundancy) bit areas. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. For example, the physical erasing unit is a physical block.

In an exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may be disposed in the connection interface unit 501 . Accordingly, the first signal (ie, signal S(1) of FIG. 1 or FIG. 3 ) may include a signal from the host system 51 . Alternatively, in an exemplary embodiment, the aforementioned clock control circuit module 10 or 30 may also be disposed in the memory control circuit unit 502 and/or the rewritable non-volatile memory module 503 .

In an exemplary embodiment, the first target signal and the second target signal in the first signal (ie, the signal S(1) in FIG. 1 or FIG. 3 ) are in the handshake phase between the memory storage device 50 and the host system 51 Received from host system 51. For example, when the connection between the memory storage device 50 and the host system 51 is just established or the connection between the memory storage device 50 and the host system 51 is unstable, the memory storage device 50 can enter the handshake phase with the host system 51 . In this handshake phase, the memory storage device 50 can perform a handshake operation with the host system 51 to perform interactive actions such as clock correction and/or voltage correction with the host system 51 .

In an exemplary embodiment, the first target signal and the second target signal are used to convey identification information about the communication standard between the memory storage device 50 and the host system 51 during the handshake phase, such as in the PCI Express standard EIEOSQ information. In addition, the first target signal and the second target signal may also include other signals with similar properties (that is, having the same signal pattern and being repeatedly transmitted in the first signal according to a specific rule), which is not limited by the present invention.

In an exemplary embodiment, after leaving the handshake phase, the first signal (ie, signal S(1) of FIG. 1 or FIG. 3 ) may carry a data signal from the host system 51 . For example, the data signal may carry data bits that the host system 51 intends to store into the memory storage device 50 . In an exemplary embodiment, by adjusting the signal CLK in FIG. 1 or FIG. 3 , the subsequent sampling quality of the data signal can be improved.

Fig. 6 is a flowchart of a clock control method according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in step S601, a clock signal is generated. In step S602, the first signal is sampled according to the clock signal to generate a first sampling signal and a second sampling signal. In step S603, the first position information corresponding to the first transition point of the first target signal and the second position information corresponding to the second transition point of the second target signal are respectively obtained according to the first sampling signal and the second sampling signal. location information. In step S604, a frequency offset state between the first signal and the clock signal is evaluated according to the first location information and the second location information.

However, each step in FIG. 6 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 6 can be implemented as multiple program codes or circuits, which is not limited in this case. In addition, the method in FIG. 6 can be used in combination with the above exemplary embodiments, or can be used alone, which is not limited in this case.

In summary, the clock control circuit module, memory storage device and clock control method provided by the embodiments of the present invention can sample the first signal without introducing an additional reference clock signal and without using multi-phase clock signals. Under the premise, effectively evaluate (and reduce) the frequency difference between the first signal and the clock signal. Thus, the signal receiving quality at the signal receiving end can be effectively improved.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (30)

1. A clock control circuit module, characterized in that, comprising: A clock generating circuit, used to generate a clock signal; The sampling circuit is used to sample the first signal according to the clock signal and generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, and the first sampling signal reflects the effect of the clock signal on the a first sampling result of a first target signal in the first signal, and the second sampling signal reflects a second sampling result of the clock signal on a second target signal in the first signal; and a control circuit connected to the clock generating circuit and the sampling circuit, Wherein said control circuit is used for: Obtaining the first position information corresponding to the first transition point of the first target signal and corresponding to the second transition point of the second target signal according to the first sampling signal and the second sampling signal respectively the second location information of ; and A frequency offset state between the first signal and the clock signal is evaluated based on the first location information and the second location information. 2. The clock control circuit module according to claim 1, wherein the first position information reflects that the first transition point is located at a first position in the first sampling window of the clock signal, and the second The position information reflects that the second transition point is located at a second position in the second sampling window of the clock signal. 3. The clock control circuit module according to claim 2, wherein the time length of the first sampling window is the same as the time length of the second sampling window. 4. The clock control circuit module according to claim 1, wherein the first position information includes a first count value, the second position information includes a second count value, and the control circuit according to the first position information and said second position information evaluating said frequency offset state between said first signal and said clock signal comprises: The state of the frequency offset between the first signal and the clock signal is evaluated based on a difference between the first count value and the second count value. 5. The clock control circuit module of claim 4, wherein the difference value is positively related to a frequency difference between the first signal and the clock signal. 6. The clock control circuit module according to claim 1, wherein the control circuit respectively obtains the first transition point of the first target signal according to the first sampling signal and the second sampling signal. The operation corresponding to the first position information and the second position information corresponding to the second transition point of the second target signal includes: continuously analyzing the sampled signal; determining that the first target signal in the first signals is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point according to the first sampling result in response to detecting the first target signal; determining that the second target signal in the first signal is detected in response to the sampled signal meeting the preset condition again; and In response to detecting the second target signal, the second position information corresponding to the second transition point is obtained according to the second sampling result. 7. The clock control circuit module according to claim 1, wherein the control circuit is also used for: controlling the clock generation circuit to adjust the frequency of the clock signal according to the frequency offset state. 8. The clock control circuit module according to claim 1, wherein the clock control circuit module is disposed in a memory storage device, and the first target signal and the second target signal are in the memory storage device and received from the host system during the handshake phase of the host system. 9. The clock control circuit module according to claim 1, wherein the control circuit comprises: phase detector; a frequency detector; and a low-pass filter connected to the phase detector, the frequency detector and the clock generation circuit, wherein the phase detector is used to detect a phase offset state between the first signal and the clock signal, the frequency detector is configured to detect the frequency offset state between the first signal and the clock signal, and The low-pass filter is used for controlling the clock generation circuit to adjust the frequency of the clock signal according to a detection result of at least one of the phase detector and the frequency detector. 10. The clock control circuit module according to claim 9, wherein said frequency detector comprises: delay line circuit; a target signal detector connected to the delay line circuit; a window mapper connected to the delay line circuit and the target signal detector; an event memory connected to said window mapper; and decision circuit, connected to the event memory, wherein the delay line circuit is used to receive the sampling signal, The target signal detector is configured to detect the first target signal and the second target signal in the first signal according to the sampled signal, the window mapper to obtain the first position information in response to the first target signal and to obtain the second position information in response to the second target signal, the event memory is used to store the first location information and the second location information, and The decision circuit is used to generate a control signal according to the first position information and the second position information, so as to control the low-pass filter to adjust the frequency of the clock signal. 11. A memory storage device, comprising: connecting the interface unit for connecting to the host system; Rewritable non-volatile memory module; a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module; and a clock control circuit module, set in the connection interface unit, Wherein the clock control circuit module is used for: generate a clock signal; receiving a first signal and the clock signal and sampling the first signal according to the clock signal to generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, and the first sampling signal Reflecting the first sampling result of the clock signal on the first target signal in the first signal, and the second sampling signal reflects the second sampling result of the clock signal on the second target signal in the first signal sampling results; Obtaining the first position information corresponding to the first transition point of the first target signal and corresponding to the second transition point of the second target signal according to the first sampling signal and the second sampling signal respectively the second location information of ; and A frequency offset state between the first signal and the clock signal is evaluated based on the first location information and the second location information. 12. The memory storage device of claim 11 , wherein the first location information reflects a first location of the first transition point in a first sampling window of the clock signal, and the second location The information reflects that the second transition point is located at a second position in a second sampling window of the clock signal. 13. The memory storage device of claim 12, wherein a temporal length of the first sampling window is the same as a temporal length of the second sampling window. 14. The memory storage device according to claim 11 , wherein the first location information includes a first count value, the second location information includes a second count value, and the clock control circuit module according to the first The location information and the second location information evaluating the frequency offset state between the first signal and the clock signal include: The state of the frequency offset between the first signal and the clock signal is evaluated based on a difference between the first count value and the second count value. 15. The memory storage device of claim 14, wherein the difference value is positively related to a frequency difference between the first signal and the clock signal. 16. The memory storage device according to claim 11, wherein the clock control circuit module respectively obtains the first transition point of the first target signal according to the first sampling signal and the second sampling signal The corresponding operation of the first position information and the second position information corresponding to the second transition point of the second target signal includes: continuously analyzing the sampled signal; determining that the first target signal in the first signals is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point according to the first sampling result in response to detecting the first target signal; determining that the second target signal in the first signal is detected in response to the sampled signal meeting the preset condition again; and In response to detecting the second target signal, the second position information corresponding to the second transition point is obtained according to the second sampling result. 17. The memory storage device according to claim 11, wherein the clock control circuit module is further used for: The frequency of the clock signal is adjusted according to the frequency offset state. 18. The memory storage device of claim 11 , wherein the first target signal and the second target signal are received from the host system during a handshake phase of the memory storage device with the host system . 19. The memory storage device of claim 11 , wherein the clock control circuit module comprises: phase detector; a frequency detector; and a low-pass filter connected to the phase detector and the frequency detector, wherein the phase detector is used to detect a phase offset state between the first signal and the clock signal, the frequency detector is configured to detect the frequency offset state between the first signal and the clock signal, and The low-pass filter is used for adjusting the frequency of the clock signal according to a detection result of at least one of the phase detector and the frequency detector. 20. The memory storage device of claim 19, wherein the frequency detector comprises: delay line circuit; a target signal detector connected to the delay line circuit; a window mapper connected to the delay line circuit and the target signal detector; an event memory connected to said window mapper; and decision circuit, connected to the event memory, wherein the delay line circuit is used to receive the first sampling signal and the second sampling signal, The target signal detector is configured to detect the first target signal and the second target signal in the first signal according to the sampled signal, the window mapper to obtain the first position information in response to the first target signal and to obtain the second position information in response to the second target signal, the event memory is used to store the first location information and the second location information, and The decision circuit is used to generate a control signal according to the first position information and the second position information, so as to control the low-pass filter to adjust the frequency of the clock signal. 21. A clock control method, characterized in that, comprising: generate a clock signal; receiving a first signal and the clock signal and sampling the first signal according to the clock signal to generate a sampling signal, wherein the sampling signal includes a first sampling signal and a second sampling signal, and the first sampling signal Reflecting the first sampling result of the clock signal on the first target signal in the first signal, and the second sampling signal reflects the second sampling result of the clock signal on the second target signal in the first signal sampling results; Obtaining the first position information corresponding to the first transition point of the first target signal and corresponding to the second transition point of the second target signal according to the first sampling signal and the second sampling signal respectively the second location information of ; and A frequency offset state between the first signal and the clock signal is evaluated based on the first location information and the second location information. 22. The clock control method according to claim 21, wherein the first position information reflects that the first transition point is located at a first position in the first sampling window of the clock signal, and the second position The information reflects that the second transition point is located at a second position in a second sampling window of the clock signal. 23. The clock control method according to claim 22, wherein the time length of the first sampling window is the same as the time length of the second sampling window. 24. The clock control method according to claim 21, wherein the first position information includes a first count value, the second position information includes a second count value, and according to the first position information and the second count value The step of evaluating said frequency offset state between said first signal and said clock signal comprising: The state of the frequency offset between the first signal and the clock signal is evaluated based on a difference between the first count value and the second count value. 25. The clock control method of claim 24, wherein the difference value is positively related to a frequency difference between the first signal and the clock signal. 26. The clock control method according to claim 21, wherein the first transition point corresponding to the first transition point of the first target signal is respectively obtained according to the first sampling signal and the second sampling signal. The step of a position information and the second position information corresponding to the second transition point of the second target signal includes: continuously analyzing the sampled signal; determining that the first target signal in the first signals is detected in response to the sampling signal meeting a preset condition; obtaining the first position information corresponding to the first transition point according to the first sampling result in response to detecting the first target signal; determining that the second target signal in the first signal is detected in response to the sampled signal meeting the preset condition again; and In response to detecting the second target signal, the second position information corresponding to the second transition point is obtained according to the second sampling result. 27. The clock control method according to claim 21, further comprising: The frequency of the clock signal is adjusted according to the frequency offset state. 28. The clock control method of claim 21, wherein the first target signal and the second target signal are received from the host system during a handshake phase of the memory storage device and the host system. 29. The clock control method according to claim 21, further comprising: detecting a phase offset state between the first signal and the clock signal by a phase detector; detecting the frequency offset state between the first signal and the clock signal by a frequency detector; and The frequency of the clock signal is adjusted according to a detection result of at least one of the phase detector and the frequency detector. 30. The clock control method according to claim 29, wherein the step of detecting, by the frequency detector, the state of the frequency offset between the first signal and the clock signal comprises: receiving the sampled signal; detecting the first target signal and the second target signal in the first signal according to the sampled signal; obtaining the first position information in response to the first target signal and obtaining the second position information in response to the second target signal; storing the first location information and the second location information; and A control signal is generated according to the first location information and the second location information to adjust the frequency of the clock signal.

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