CN116300546A - Circuit structure for realizing MCU low-power consumption power management and switching method thereof - Google Patents

Abstract

The present invention relates to a circuit structure for realizing low-power consumption power management of MCU, wherein said circuit structure includes: a first low-dropout linear voltage regulator unit (LDOA), which is used to receive an external digital logic unit (logic) to send Turn on the circuit to work after the high-level signal of the high level signal, and output a large current to make the circuit structure enter the high-performance mode; and the second low-dropout linear voltage regulator unit (LDOB), used to receive the external digital logic ) to start the circuit to work after sending the low-level signal, and output a low current so that the circuit structure enters an ultra-low power consumption mode. The invention also relates to a corresponding switching method. The circuit structure and switching method for realizing MCU low-power consumption power management of the present invention have a simple structure, fewer required circuit devices, save chip area, and the switching process is simple and easy to implement, which can effectively improve the chip yield.

Description

Circuit Structure and Switching Method for Realizing MCU Low Power Consumption Power Management

technical field

The invention relates to the field of electronic technology, in particular to the field of power management technology, in particular to a circuit structure and a switching method for realizing low-power consumption power management of an MCU.

Background technique

In the MCU (micro controller unit) design process, how to achieve high performance and low power consumption has always been a difficult point in the design, especially now that the scale of the MCU circuit is getting larger and larger, and the problem of power consumption of the MCU is becoming more prominent, and the design of low power consumption is even more difficult. It has become a hot and difficult point in MCU design. Realizing the low power consumption design of the MCU can not only greatly increase the battery life of the device in application scenarios powered by batteries, but also reduce the temperature of the MCU during operation and prolong the service life of the device.

In the existing MCU design, most of the low power consumption mode is used to reduce the power consumption current when the MCU sleeps, specifically, by switching the operating frequency of the MCU to the low frequency mode when the device has few or no tasks, and at the same time turning off some The digital module is used to reduce the power consumption current of the MCU during standby, but this method still has the defect of high power consumption, which cannot meet the higher ultra-low power consumption requirements, and the switching mode process is complicated, so it is urgent to find a method that can The circuit structure and switching method to realize the low power consumption power management of MCU.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, and provide a circuit structure and a switching method for realizing MCU low power consumption power management with simple structure and low power consumption.

In order to achieve the above object, the circuit structure and switching method thereof for realizing MCU low power consumption power management of the present invention are as follows:

This realizes the circuit structure of MCU low power consumption power management, and its main feature is that described circuit structure comprises:

The first low-dropout linear voltage stabilizing unit is used to start the circuit to work after receiving the high-level signal sent by the external digital logic unit, and output a large current so that the circuit structure enters a high-performance mode; and

The second low-dropout linear voltage stabilizing unit is used to start the circuit to work after receiving the low-level signal sent by the external digital logic unit, and output a low current so that the circuit structure enters an ultra-low power consumption mode;

And the output end of the first low-dropout linear voltage stabilizing unit and the output end of the second low-dropout linear voltage stabilizing unit are both connected to the digital circuit at the rear end, and are used for the small load of the digital circuit and/or The working state of heavy load is controlled and processed.

Preferably, it also includes a central processing unit, the central processing unit includes the external digital logic unit, wherein,

The first enable input terminal of the external digital logic unit is used to input a low power consumption mode signal;

The second enable input terminal of the external digital logic unit is used to input a linear voltage regulation signal;

The first enable output terminal of the external digital logic unit is used to input a first logic control signal to the second low dropout linear voltage stabilizing unit through the central processing unit;

The second enabling output terminal of the external digital logic unit is used to input a second logic control signal to the first low dropout linear voltage stabilizing unit through the central processing unit.

Preferably, the first low dropout linear voltage stabilizing unit specifically includes:

An operational amplifier, the first end of which is used to receive the first reference voltage output by the bandgap reference circuit;

The third PMOS field effect transistor, the gate of the third PMOS field effect transistor is connected to the output terminal of the operational amplifier, and the drain of the third PMOS field effect transistor is used to access the power supply voltage;

a first adjustable resistor and a second resistor;

The second resistor is connected between the second terminal of the operational amplifier and the source of the third PMOS field effect transistor;

The first adjustable resistor is connected between the second resistor and ground.

Preferably, the circuit structure is further provided with a control signal, and the control signal is used to set the resistance value of the first adjustable resistor.

Preferably, the second low dropout linear voltage stabilizing unit specifically includes:

The first PMOS field effect transistor, the gate of the first PMOS field effect transistor is used to access the first logic control signal, and the drain of the first PMOS field effect transistor is used to output a bias current ;

The second PMOS field effect transistor, the gate of the second PMOS field effect transistor is grounded, and the drain of the second PMOS field effect transistor is used to access the power supply voltage;

A second NMOS field effect transistor, the gate and drain of the second NMOS field effect transistor are connected to the source of the first PMOS field effect transistor;

A first NMOS field effect transistor, the gate and drain of the first NMOS field effect transistor are both connected to the source of the second NMOS field effect transistor; and

A third NMOS field effect transistor, the drain of the third NMOS field effect transistor is connected to the source of the second PMOS field effect transistor, and the gate of the third NMOS field effect transistor is connected to the source of the second PMOS field effect transistor. The gate of the second NMOS field effect transistor is connected to the drain, and the source of the third NMOS field effect transistor is connected between the third PMOS field effect transistor and the second resistor.

Preferably, the resistance value of the first adjustable resistor is adjusted through the control signal, so that the second low dropout linear voltage stabilizing unit outputs the required low power consumption voltage driving current.

The method of utilizing the above-mentioned circuit structure to realize the low-power switching of the dual LDO structure is characterized in that the method includes the following steps:

(1) The chip enters the first working cycle, and the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit and the second low-dropout linear voltage stabilizing unit perform circuit processing in this mode;

(2) Judging whether the micro-control unit has received the switch low-power mode command sent from the outside, if yes, then enter step (3), otherwise, continue to maintain the processing of step (1);

(3) the micro-control unit sends a switching low power consumption command;

(4) The chip enters the second working cycle, and the second low dropout linear voltage stabilizing unit enters an ultra-low power consumption mode according to the received low power consumption command, and executes circuit processing in this mode.

Preferably, the step (1) specifically includes the following steps:

(1.1) The micro control unit sets the low power consumption mode signal to an off state, and sets the linear voltage regulator signal to an on state;

(1.2) After being processed by the external digital logic unit, the first logic control signal outputs a low-level signal, and the second logic control signal outputs a high-level signal;

(1.3) The operational amplifier receives the high-level signal output by the second logic control signal, and the first low-dropout linear voltage stabilizing unit starts to work;

(1.4) The first PMOS field effect transistor receives the low-level signal output by the first logic control signal, and the second low-dropout linear regulator unit starts to work.

Preferably, said step (4) specifically includes the following steps:

(4.1) The second low dropout linear voltage stabilizing unit receives the low power consumption command sent by the micro control unit;

(4.2) The micro control unit sets the low power consumption command to a low level, and closes the large load circuit that does not maintain the basic function of the chip, and then enters the delay state;

(4.3) After the delay is over, the micro-control unit sets both the low-power mode signal and the linear voltage regulation signal to a conduction state;

(4.4) After being processed by the external digital logic unit, the first logic control signal outputs a low-level signal, and the second logic control signal outputs a low-level signal;

(4.5) After the operational amplifier receives the low-level signal output by the second logic control signal, the first low-dropout linear regulator unit closes the circuit;

(4.6) The first PMOS field effect transistor receives the low-level signal output by the first logic control signal, and the second low-dropout linear regulator unit continues to work.

Preferably, the driving current outputted by the first low dropout linear voltage stabilizing unit and the second low dropout linear voltage stabilizing unit is uA level, so as to realize that the circuit structure meets the requirement of ultra-low power consumption.

Adopting the circuit structure and switching method thereof for realizing MCU low power consumption power management of the present invention, when the operating frequency of the circuit is reduced and in the low power consumption mode, a low power consumption LDO structure is adopted to further reduce power consumption, and the low power consumption LDO structure Simple and easy to realize, the circuit structure adds few circuit components, no additional bias voltage is needed, only 5 MOS tubes are needed, and the integration into the chip greatly saves the chip area. The new low-power LDO structure can work simultaneously with the high-performance LDO without mutual influence. Compared with the existing technology, the switching process is simple and easy to implement, which can effectively improve the chip yield.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure for realizing low power consumption power management of an MCU according to the present invention.

FIG. 2 is a schematic diagram of a method for realizing low-power switching of a dual LDO structure according to the present invention.

FIG. 3 is a timing diagram of low power switching of the double LDO structure of the present invention.

reference sign

LDOA The first low dropout linear voltage regulator unit

LDOB second low dropout linear regulator unit

logic digital logic unit

CPU central processing unit

STANDBY_ENH low power mode signal

LDO15_PDN linear regulator signal

PDN first logic control signal

STANDBY Second logic control signal

AMP operational amplifier

BGR Bandgap Reference Circuit

VBG first reference voltage

VDDD50 supply voltage

mp1 The first PMOS field effect transistor

mp2 The second PMOS field effect transistor

mp3 The third PMOS field effect transistor

mn1 The first NMOS field effect transistor

mn2 The second NMOS field effect transistor

Native_mn3 The third NMOS field effect transistor

R1 first adjustable resistor

R2 second resistor

LDO15_TRIM<4:0> Control Signal

MCU micro control unit

ENZ Low Power Command

STANDBY_ENH low power mode signal

Detailed ways

In order to describe the technical content of the present invention more clearly, further description will be given below in conjunction with specific embodiments.

Before describing the embodiments according to the present invention in detail, it should be noted that in the following, relative terms such as first and second are only used to distinguish one entity or action from another entity or action, and do not necessarily require or Any actual such relationship or order between such entities or actions is implied. The terms "comprising", "comprising" or any other variant are intended to cover a non-exclusive inclusion whereby a process, method, article or apparatus comprising a set of elements includes not only those elements but also other elements not expressly listed elements, or elements inherent in such a process, method, article, or apparatus.

Please refer to shown in Fig. 1, this realizes the circuit structure of MCU low power consumption power management, wherein, described circuit structure comprises:

The first low-dropout linear regulator unit LDOA is used to start the circuit to work after receiving the high-level signal sent by the external digital logic unit logic, and output a large current so that the circuit structure enters a high-performance mode; and

The second low-dropout linear voltage stabilizing unit LDOB is used to start the circuit to work after receiving the low-level signal sent by the external digital logic unit logic, and output a low current so that the circuit structure enters an ultra-low power consumption mode;

And the output end of the first low-dropout linear voltage stabilizing unit LDOA and the output end of the second low-dropout linear voltage stabilizing unit LDOB are both connected to the digital circuit at the rear end, and are used for the small load of the digital circuit and / Or the working state of heavy load is controlled and processed.

As a preferred embodiment of the present invention, it also includes a central processing unit CPU, and the central processing unit CPU includes the external digital logic unit logic, wherein,

The first enable input terminal of the external digital logic unit logic is used to input the low power consumption mode signal STANDBY_ENH;

The second enable input terminal of the external digital logic unit logic is used to input the linear voltage regulation signal LDO15_PDN;

The first enabling output terminal of the external digital logic unit logic is used to input a first logic control signal PDN to the second low dropout linear voltage stabilizing unit LDOB through the central processing unit CPU;

The second enabling output terminal of the external digital logic unit logic is used to input a second logic control signal STANDBY to the first low dropout linear voltage stabilizing unit LDOA through the central processing unit CPU.

As a preferred embodiment of the present invention, the first low-dropout linear regulator unit LDOA specifically includes:

Operational amplifier AMP, the first end of the operational amplifier AMP is used to receive the first reference voltage VBG output by the bandgap reference circuit BGR;

The third PMOS field effect transistor mp3, the gate of the third PMOS field effect transistor mp3 is connected to the output terminal of the operational amplifier AMP, and the drain of the third PMOS field effect transistor mp3 is used to connect Input power supply voltage VDDD50;

a first adjustable resistor R1 and a second resistor R2;

The second resistor R2 is connected between the second end of the operational amplifier AMP and the source of the third PMOS field effect transistor mp3;

The first adjustable resistor R1 is connected between the second resistor R2 and ground.

In practical application, LDOA is composed of operational amplifier AMP, MOS tube mp3, resistors R2 and R1. R1 is an adjustable resistor. By setting LDO15_TRIM<4:0>, the resistor value can be set to change the output voltage of VDDD15. AMP can be turned on by the high level of the signal line STANDBY. In addition, the LDOA needs a bias voltage VBG, which is generally generated by the bandgap reference circuit BRG. The working principle of the LDOA in Figure 1 is that under the feedback of the operational amplifier AMP, Vp=VBG=V _bias , so the voltage at VDDD15 is:

VDDD15＝ _Vbias ×(R2+R1)/R1;

By adjusting the resistance of R2 and R1, the voltage of VDDD15 can be adjusted to 1.5V.

As a preferred embodiment of the present invention, the circuit structure is also provided with a control signal LDO15_TRIM<4:0>, and the control signal LDO15_TRIM<4:0> is used to set the resistance of the first adjustable resistor R1 value.

As a preferred embodiment of the present invention, the second low dropout linear voltage stabilization unit LDOB specifically includes:

The first PMOS field effect transistor mp1, the gate of the first PMOS field effect transistor mp1 is used to access the first logic control signal PDN, and the drain of the first PMOS field effect transistor mp1 is used for Output bias current IBIAS0;

The second PMOS field effect transistor mp2, the gate of the second PMOS field effect transistor mp2 is grounded, and the drain of the second PMOS field effect transistor mp2 is used to access the power supply voltage VDDD50;

A second NMOS field effect transistor mn2, the gate and drain of the second NMOS field effect transistor mn2 are both connected to the source of the first PMOS field effect transistor mp1;

a first NMOS field effect transistor mn1, the gate and drain of the first NMOS field effect transistor mn1 are both connected to the source of the second NMOS field effect transistor mn2; and

The third NMOS field effect transistor Native_mn3, the drain of the third NMOS field effect transistor Native_mn3 is connected to the source of the second PMOS field effect transistor mp2, the gate of the third NMOS field effect transistor Native_mn3 The pole is connected to the gate and drain of the second NMOS field effect transistor mn2, and the source of the third NMOS field effect transistor Native_mn3 is connected to the third PMOS field effect transistor mp3 and the second between resistor R2.

As a preferred embodiment of the present invention, the resistance value of the first adjustable resistor R1 is adjusted through the control signal LDO15_TRIM<4:0>, so that the second low dropout linear regulator unit LDOB outputs the required low power voltage drive current.

In practical application, LDOB is composed of two P-type MOS transistors mp1, mp2 and three N-type MOS transistors mn1, mn2, Native_mn3. A voltage of 1.5V is generated at Vp. The mn3 tube is a native tube, a normally open tube, and its source (V15) is also 1.5V. LDOB needs a bias current, which comes from a low-frequency oscillator. All MCU chips will have a low-frequency oscillator, and no additional bias circuit is required. Unlike the structure of LDOA, which requires an additional bandgap reference circuit. The circuit structure of LDOB is very simple, and the basic components (resistors, capacitors, MOS tubes) required are few, and when integrated into the chip, it will occupy a small area, which means lower cost. The 1.5V voltage drive current generated by this structure is only uA level, and the power consumption current of the whole circuit is also very small, meeting the ultra-low power consumption requirement.

The method for realizing low-power switching of a dual LDO structure by using the circuit structure described above, wherein the method includes the following steps:

(1) The chip enters the first working cycle, and the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit LDOA and the second low-dropout linear voltage stabilizing unit LDOB perform circuit processing in this mode;

(2) Judging whether the micro-control unit MCU receives the switch low-power mode command sent from the outside, if so, then enter step (3), otherwise, continue to maintain the processing of step (1);

(3) the micro control unit MCU sends a switch low power consumption command ENZ;

(4) The chip enters the second working cycle, and the second low dropout linear voltage stabilizing unit LDOB enters an ultra-low power consumption mode according to the received low power consumption command ENZ, and executes circuit processing in this mode.

As a preferred embodiment of the present invention, described step (1) specifically includes the following steps:

(1.1) The micro control unit MCU sets the low power consumption mode signal STANDBY_ENH to an off state, and sets the linear voltage regulator signal LDO15_PDN to an on state;

(1.2) After being processed by the external digital logic unit logic, the first logic control signal PDN outputs a low-level signal, and the second logic control signal STANDBY outputs a high-level signal;

(1.3) The operational amplifier AMP receives the high-level signal output by the second logic control signal STANDBY, and the first low-dropout linear regulator unit LDOA starts to work;

(1.4) The first PMOS field effect transistor mp1 receives the low-level signal output by the first logic control signal PDN, and the second low dropout linear regulator unit LDOB starts to work.

As a preferred embodiment of the present invention, described step (4) specifically includes the following steps:

(4.1) The second low dropout linear regulator unit LDOB receives the low power consumption command ENZ sent by the micro control unit MCU;

(4.2) The micro control unit MCU sets the low power consumption command ENZ to low level, and closes the large load circuit that does not maintain the basic function of the chip, and then enters the delay state;

(4.3) After the delay is over, the micro control unit MCU sets both the low power consumption mode signal STANDBY_ENH and the linear voltage regulator signal LDO15_PDN to a conduction state;

(4.4) After being processed by the external digital logic unit logic, the first logic control signal PDN outputs a low-level signal, and the second logic control signal STANDBY outputs a low-level signal;

(4.5) After the operational amplifier AMP receives the low-level signal output by the second logic control signal STANDBY, the first low-dropout linear regulator unit LDOA closes the circuit;

(4.6) The first PMOS field effect transistor mp1 receives the low-level signal output by the first logic control signal PDN, and the second low dropout linear regulator unit LDOB keeps working.

As a preferred embodiment of the present invention, the driving current output by the first low-dropout linear voltage stabilizing unit LDOA and the second low-dropout linear voltage stabilizing unit LDOB is uA level, so as to realize that the circuit structure meets ultra-low power consumption requirements.

In practical applications, when the MCU enters the first working cycle and the chip is in the high-performance mode, the digital circuit needs a large current. At this time, STANDBY_ENH=0, LDO15_PDN=1, after the digital unit logic processing, the PDN outputs a low level, and the STANDBY Output high level, after AMP receives high level, the circuit is turned on, LDOA starts to work, and outputs large current. mp1 is a P-type MOS tube, it will be turned on when it receives the low level of PDN, and the LDOB circuit will also start to work. Because the output current of LDOA is larger than that of LDOB, and the contribution of LDOB to the supply current of VDDD15 is very small, it can be considered that LDOB does not work at this time.

In practical applications, when the MCU enters the second working cycle and the chip is about to enter the ultra-low power consumption mode, the MCU issues a command ENZ to turn off the heavy load circuit that does not maintain the basic functions of the chip, and after a delay for a period of time (in order to ensure that the dual LDO The smooth switching of the structure, the delay time needs to be as long as possible), then the MCU will set STANDBY_ENH=1, LDO15_PDN=1, after the digital unit logic processing, the PDN outputs a low level, the STANDBY outputs a low level, and the AMP receives a low level level after the circuit is closed. Since LDOB is still at low level due to PDN, the circuit continues to work and outputs a small current to ensure low power consumption of the chip.

Please refer to Fig. 2, in a specific embodiment of the present invention, in the low power switching process, since the LDOB can only output uA level current, if the direct switching without considering the change of the load will cause VDDD15 to lose power, the chip Fail-Reset, so a switching sequence is required when switching from normal operation to low-power mode. When the MCU receives the command to switch the low-power mode, the MCU will first issue the low-power command ENZ, set ENZ to low level, and the large-load circuit module of the digital circuit will be turned off immediately, but the small-load circuit involved cannot be turned off immediately , it takes a delay time, after the MCU delays for a period of time, there are only some small load circuit modules in the digital circuit that maintain the chip's work, and only need a small current, then the MCU pulls STANDBY to low level, LDOA is turned off, and the MCU Enter low power mode.

It can be seen that in the technical solution, the LDOB works all the time in the normal operation and the low power consumption mode, so the whole switching process is very simple. When the MCU needs to resume its normal working mode, it only needs to turn on the LDOA first, and after a period of stabilization, the MCU turns on all the digital circuits.

Please refer to FIG. 3. In a specific embodiment of the present invention, the timing diagram of the low-power switching of the dual LDO structure is shown in FIG. 3:

When the circuit structure receives the low power consumption command ENZ issued by the MCU, it will be placed in a low-level state immediately, and then enter a delay state. During this process, the first logic control signal PDN always maintains a low power state. The flat state, that is, the second low dropout linear regulator unit LDOB is in the working state no matter in the normal working mode or the low power consumption mode; and the second logic control signal STANDBY after the same delay time, Then switch from the original high level state to the low level state, that is, the current circuit enters the low power consumption mode, and the first low dropout linear voltage stabilizing unit LDOA stops working.

In particular, it should be noted that under the dual LDO structure, the switch between the two LDO structures needs to be switched after the circuit has been in low power consumption mode and stabilized. Before turning off the LDOA, it is necessary to turn off the modules with large power consumption in the digital circuit, and turn off the LDOA after the digital circuit is in sleep mode and stabilized. Therefore, it is necessary to make some requirements on the switching timing of the two LDOs.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments or portions of code comprising one or more executable instructions for implementing specific logical functions or steps of the process , and the scope of preferred embodiments of the invention includes alternative implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order depending on the functions involved, which shall It is understood by those skilled in the art to which the embodiments of the present invention pertain.

It should be understood that various parts of the present invention can be realized by hardware, software, firmware or their combination. In the above-described embodiments, various steps or methods may be implemented by software or firmware stored in a memory and executed by a suitable instruction execution device.

Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above-mentioned embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, and the program can be executed when executed , including one or a combination of the steps of the method embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, each unit may exist separately physically, or two or more units may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. If the integrated modules are realized in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like.

In the description of this specification, descriptions referring to the terms "an embodiment", "some embodiments", "example", "specific example", or "embodiment" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention, those skilled in the art can make the above-mentioned The embodiments are subject to changes, modifications, substitutions and variations.

Adopting the circuit structure and switching method thereof for realizing MCU low power consumption power management of the present invention, when the operating frequency of the circuit is reduced and in the low power consumption mode, a low power consumption LDO structure is adopted to further reduce power consumption, and the low power consumption LDO structure Simple and easy to realize, the circuit structure adds few circuit components, no additional bias voltage is needed, only 5 MOS tubes are needed, and the integration into the chip greatly saves the chip area. The new low-power LDO structure can work simultaneously with the high-performance LDO without mutual influence. Compared with the existing technology, the switching process is simple and easy to implement, which can effectively improve the chip yield.

In this specification, the invention has been described with reference to specific embodiments thereof. However, it is obvious that various modifications and changes can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims (10)

1. The circuit structure for realizing MCU low-power consumption power management is characterized by comprising:

the first low dropout linear voltage regulator unit (LDOA) is used for starting a circuit to work after receiving a high-level signal sent by an external digital logic unit (logic) and outputting a large current to enable the circuit structure to enter a high-performance mode; and

the second low dropout linear voltage regulator unit (LDOB) is used for starting a circuit to work after receiving a low-level signal sent by an external digital logic unit (logic) and outputting low current to enable the circuit structure to enter an ultra-low power consumption mode;

the output end of the first low dropout linear voltage stabilizing unit (LDOA) and the output end of the second low dropout linear voltage stabilizing unit (LDOB) are connected with a digital circuit at the rear end, and the digital circuit is used for controlling and processing the working state of a small load and/or a large load of the digital circuit.

2. The circuit structure for implementing MCU low power consumption power management of claim 1, further comprising a Central Processing Unit (CPU) including said external digital logic unit (logic), wherein,

the first enabling input end of the external digital logic unit (logic) is used for inputting a low power consumption mode signal (STANDBY_ENH);

the second enabling input end of the external digital logic unit (logic) is used for inputting a linear voltage stabilizing signal (LDO15_PDN);

the first enabling output end of the external digital logic unit (logic) is used for inputting a first logic control signal (PDN) to the second low dropout linear voltage stabilizing unit (LDOB) through the Central Processing Unit (CPU);

the second enable output end of the external digital logic unit (logic) is used for inputting a second logic control Signal (STANDBY) to the first low dropout linear voltage regulator unit (LDOA) through the Central Processing Unit (CPU).

3. The circuit structure for implementing MCU low power consumption power management as defined in claim 2, wherein said first low dropout linear regulator unit (LDOA) comprises:

an operational Amplifier (AMP), a first terminal of the operational Amplifier (AMP) being configured to receive a first reference Voltage (VBG) output by the bandgap reference circuit (BGR);

the grid electrode of the third PMOS field effect transistor (mp 3) is connected with the output end of the operational Amplifier (AMP), and the drain electrode of the third PMOS field effect transistor (mp 3) is used for being connected with a power supply voltage (VDDD 50);

a first adjustable resistor (R1) and a second resistor (R2);

the second resistor (R2) is arranged between the second end of the operational Amplifier (AMP) and the source electrode of the third PMOS field effect transistor (mp 3); the first adjustable resistor (R1) is arranged between the second resistor (R2) and the ground.

4. A circuit arrangement for implementing MCU low power consumption power management as defined in claim 3, further provided with a control signal (ldO15_TRIM <4:0 >), said control signal (ldO15_TRIM <4:0 >) being used to set the resistance of said first adjustable resistor (R1).

5. The circuit structure for implementing low power consumption power management of MCU as defined in claim 4, wherein said second low dropout linear regulator unit (LDOB) comprises:

the first PMOS field effect transistor (mp 1), the grid electrode of the first PMOS field effect transistor (mp 1) is used for being connected with the first logic control signal (PDN), and the drain electrode of the first PMOS field effect transistor (mp 1) is used for outputting bias current (IBIAS 0);

the grid electrode of the second PMOS field effect tube (mp 2) is grounded, and the drain electrode of the second PMOS field effect tube (mp 2) is used for being connected with a power supply voltage (VDDD 50);

the grid electrode and the drain electrode of the second NMOS field effect tube (mn 2) are connected with the source electrode of the first PMOS field effect tube (mp 1);

the grid electrode and the drain electrode of the first NMOS field effect tube (mn 1) are connected with the source electrode of the second NMOS field effect tube (mn 2); and

the drain electrode of the third NMOS field effect tube (native_mn3) is connected with the source electrode of the second PMOS field effect tube (mp 2), the grid electrode of the third NMOS field effect tube (native_mn3) is connected with the grid electrode of the second NMOS field effect tube (mn 2) and the drain electrode, and the source electrode of the third NMOS field effect tube (native_mn3) is arranged between the third PMOS field effect tube (mp 3) and the second resistor (R2).

6. The circuit structure for implementing low power consumption power management of MCU according to claim 5, wherein the resistance value of the first adjustable resistor (R1) is adjusted by the control signal (ldo15_trim <4:0 >) so that the second low dropout linear regulator unit (LDOB) outputs the required low power consumption voltage driving current.

7. A method for implementing low power switching of a dual LDO structure by using the circuit structure of any of claims 1 to 6, comprising the steps of:

(1) The chip enters a first working period, the circuit structure is in a high-performance mode, and the first low-dropout linear voltage stabilizing unit (LDOA) and the second low-dropout linear voltage stabilizing unit (LDOB) execute circuit processing in the mode;

(2) Judging whether a Micro Control Unit (MCU) receives an externally transmitted command for switching the low power consumption mode, if so, entering a step (3), otherwise, continuing to maintain the processing of the step (1);

(3) The Micro Control Unit (MCU) sends out a switching low power consumption command (ENZ);

(4) The chip enters a second working period, and the second low dropout linear voltage regulator unit (LDOB) enters an ultra-low power consumption mode according to a received low power consumption command (ENZ) and executes circuit processing under the mode.

8. The method for implementing low power switching of dual LDO structure as set forth in claim 7, wherein said step (1) comprises the steps of:

(1.1) the Micro Control Unit (MCU) sets the low power mode signal (standby_enh) to an off state and sets the linear voltage stabilizing signal (ldos15_pdn) to an on state;

(1.2) after processing by said external digital logic unit (logic), said first logic control signal (PDN) outputting a low level signal and said second logic control Signal (STANDBY) outputting a high level signal;

(1.3) said operational Amplifier (AMP) receiving a high level signal output by said second logic control Signal (STANDBY), said first low dropout linear regulator unit (LDOA) starting operation;

the first PMOS field-effect transistor (mp 1) of (1.4) receives the low-level signal output by the first logic control signal (PDN), and the second low dropout linear voltage regulator unit (LDOB) starts to operate.

9. The method for implementing low power switching of dual LDO structure as set forth in claim 8, wherein said step (4) comprises the steps of:

the second low dropout linear regulator unit (LDOB) described in (4.1) receives the low power consumption command (ENZ) sent by the Micro Control Unit (MCU);

(4.2) said Micro Control Unit (MCU) setting said low power command (ENZ) to low level and turning off the heavy load circuit which does not maintain the basic function of the chip, and then entering a delay state;

(4.3) after the delay is finished, the Micro Control Unit (MCU) sets the low power consumption mode signal (STANDBY_ENH) and the linear voltage stabilizing signal (LDO15_PDN) to be in a conducting state;

(4.4) after said external digital logic unit (logic) processing, said first logic control signal (PDN) outputting a low level signal and said second logic control Signal (STANDBY) outputting a low level signal;

after the operational Amplifier (AMP) receives the low level signal output by the second logic control Signal (STANDBY), the first low dropout linear regulator unit (LDOA) turns off the circuit;

the first PMOS field-effect transistor (mp 1) of (4.6) receives the low-level signal output by the first logic control signal (PDN), and the second low dropout linear voltage regulator unit (LDOB) continues to maintain the operating state.

10. The method of claim 7, wherein the driving currents output by the first low dropout linear voltage regulator (LDOA) and the second low dropout linear voltage regulator (LDOB) are of uA level, so as to achieve that the circuit structure meets the requirement of ultra low power consumption.

Images