CN116306405B

CN116306405B - Modeling method and system for state grammar module in RTL, storage medium and electronic equipment

Info

Publication number: CN116306405B
Application number: CN202310162116.4A
Authority: CN
Inventors: 张曦; 孙小霞; 张云飞
Original assignee: Shanghai Sierxin Technology Co ltd
Current assignee: Shanghai Sierxin Technology Co ltd
Priority date: 2023-02-23
Filing date: 2023-02-23
Publication date: 2025-07-15
Anticipated expiration: 2043-02-23
Also published as: CN116306405A

Abstract

The present disclosure relates to a modeling method, a modeling system, a storage medium and an electronic device for a state grammar module in RTL. The modeling method for a state grammar module in RTL analyzes and obtains the state grammar module in each Module module in the RTL file layer by layer; analyzes the interconnection relationship of the state grammar module in the Module module to obtain the input and output ports corresponding to the state grammar module; remodels the state grammar module according to the interconnection relationship and the driving direction to obtain the Module module that meets the hardware description language standard; reconstructs the Module module into a logic expression module and instantiates it to the internal position of the Module module where the state grammar module is located; adds input and output ports to the logic expression module according to the interconnection relationship of the state grammar module in the Module module, and the internal wire network connected to the input and output ports, and obtains a model file of the main hierarchical tree structure containing only the Module module and the logic expression module, which can improve the processing efficiency and correctness of the EDA software.

Description

Modeling method and system for state grammar module in RTL, storage medium and electronic equipment

Technical Field

The invention belongs to the technical field of automatic design of electronic design, and particularly relates to a modeling method and system for a state grammar module in RTL, a storage medium and electronic equipment.

Background

With the continuous development of the digital integrated circuit design field, the design mode and the design method of the digital integrated circuit design field gradually represent diversity, meanwhile, the demand for EDA (electronic design automation) software is gradually increasing, as the hardware description language is designed into a hierarchical design mode and the design mode is gradually enriched, more state grammar modules, such as ALWAYS STATEMENT block modules, are introduced besides keywords, such as modules (main level expression modules used for describing the hardware design), instance (logic expression modules used for describing the internal nested inclusion relation of the modules), ports (interface descriptions used for representing the external input and output of the modules), wires (descriptions used for representing the internal logic signal transmission of the modules) and the like, and are used for asynchronous management of logic based on clocks in the hardware design description, so the more complex digital integrated circuit design is more frequently used, and various nesting modes facing different grammars exist in the Always Module, but when the state grammar Module is processed by the current EDA tool, whether facing digital integrated circuit synthesis or digital integrated circuit simulation, the RTL level hardware description language design is reduced to a gate level description or directly mapped to a netlist structure by a thinning mode, but cannot be directly processed at the RTL level hardware description language level, the main reason is that when the state grammar Module is processed by the traditional method, the special state grammar Module cannot be directly processed in the RTL level description, the RTL level Module needs to be processed after being packaged into another expression mode by thinning or mapping the RTL level Module to the netlist, resulting in inefficiency of the process.

Disclosure of Invention

The invention overcomes one of the defects in the prior art, and provides a modeling method, a system, a storage medium and electronic equipment for a state grammar Module in RTL (real time digital hierarchy), which can accurately model the state grammar Module (STATEMENT BLOCK) in RTL-level hardware description language design as a Module and instantiate the Module to an accurate position in the design, thereby improving the processing efficiency and accuracy of EDA software.

According to an aspect of the disclosure, a modeling method for a state grammar module in RTL is provided, the method comprising:

Analyzing and acquiring a state grammar Module in each Module in the RTL file layer by layer;

analyzing the interconnection relation of the state grammar Module in the Module to obtain input and output ports corresponding to the state grammar Module;

The state grammar Module is modeled again according to the interconnection relation and the driving direction, and a Module which accords with the hardware description language standard is obtained;

Reconstructing a Module which accords with the hardware description language standard into a logic expression Module, and instantiating the logic expression Module to the internal position of the Module where the state grammar Module is located;

and adding an input port, an output port and an internal network connected with the input port and the output port to the logic expression Module according to the interconnection relation of the state grammar Module in the Module to obtain a model file of a main hierarchical tree structure only comprising the Module and the logic expression Module.

In one possible implementation, the analyzing and obtaining the state grammar Module in each Module in the RTL file layer by layer includes:

analyzing the grammar tree memory structure in the RTL file by using an analyzer;

Performing layer-by-layer analysis from each Module of the grammar tree memory structure in an iterative traversal mode to obtain pointers pointing to each Module;

acquiring the content of each Module according to the pointer of each Module;

And when judging that the content of the Module is the state grammar Module, acquiring a pointer pointing to the state grammar Module and the structure of the state grammar Module.

In one possible implementation manner, analyzing the interconnection relation of the state grammar Module in the Module to obtain the input and output ports corresponding to the state grammar Module includes:

Analyzing the interconnection signal of the state grammar Module in the Module, and tracing the driving direction of the interconnection signal;

Obtaining the interconnection relation between the state grammar Module and other modules in the Module according to the driving direction;

And acquiring the input and output ports corresponding to the state grammar module according to the interconnection relation.

In one possible implementation, tracing back the driving direction of the interconnection signal includes:

and tracing the input and output of the interconnection signal according to the interconnection signal of the state grammar module to obtain the driving direction of the interconnection signal.

In one possible implementation, a syntax tree memory structure is used to store the logical relationships, logic levels, and syntax expressions of the hardware integrated circuit design in the RTL file.

In one possible implementation, performing layer-by-layer analysis from each Module of the syntax tree memory structure in an iterative traversal manner to obtain pointers to each Module, including:

Starting from each Module of the grammar tree memory structure in an iterative traversal mode, and analyzing leaf nodes of each node of the grammar tree memory structure layer by taking each logic expression Module as a branch;

Reconstructing a new hierarchical tree according to the leaf node of each node, and obtaining a pointer pointing to each Module according to the hierarchical tree.

In one possible implementation, the Module conforming to the hardware description language standard is reconstructed into a logic expression Module, which includes:

and adding, subtracting, multiplying, dividing, AND, OR and NOT analyzing the logic symbol of the Module conforming to the hardware description language standard, and reconstructing the Module into a logic expression Module.

According to another aspect of the present disclosure, a modeling system for a state grammar module in RTL is presented, the system comprising:

The traversal Module is used for analyzing and acquiring the state grammar Module in each Module in the RTL file layer by layer;

The analysis Module is used for analyzing the interconnection relation of the state grammar Module in the Module to obtain input and output ports corresponding to the state grammar Module;

The reconstruction Module is used for re-modeling the state grammar Module according to the interconnection relation and the driving direction to obtain a Module conforming to the hardware description language standard;

The reconstruction Module is used for reconstructing the Module which accords with the hardware description language standard into a logic expression Module and instantiating the logic expression Module to the internal position of the Module where the state grammar Module is positioned;

And the output Module is used for adding input and output ports to the logic expression Module according to the interconnection relation of the state grammar Module in the Module and an internal network connected with the input and output ports to output a model file of a main hierarchical tree structure only comprising the Module and the logic expression Module.

According to another aspect of the present disclosure, a storage medium is presented, on which a computer program is stored, which program, when being executed by a processor, implements a method as described above.

According to another aspect of the present disclosure, an electronic device is presented comprising a processor and a memory storing a computer program, the processor being configured to implement the method as described above when the computer program is run.

The modeling method for the state grammar Module in the RTL comprises the steps of analyzing and obtaining the state grammar Module in each Module in the RTL file layer by layer, analyzing the interconnection relation of the state grammar Module in the Module to obtain the input port and the output port corresponding to the state grammar Module, re-modeling the state grammar Module according to the interconnection relation and the driving direction to obtain the Module conforming to the hardware description language standard, reconstructing the Module conforming to the hardware description language standard into a logic expression Module, instantiating the logic expression Module to the internal position of the Module where the state grammar Module is located, adding the input port and the output port to the logic expression Module according to the interconnection relation of the state grammar Module in the Module, and obtaining the model file of the main hierarchical tree structure only comprising the Module and the logic expression Module. The state grammar Module (STATEMENT BLOCK) in the RTL-level hardware description language design can be correctly modeled as a Module and instantiated to the correct position in the design, so that the processing efficiency and the correctness of EDA software are improved.

Additional optional features and technical effects of embodiments of the invention are described in part below and in part will be apparent from reading the disclosure herein.

Drawings

Embodiments of the present invention will hereinafter be described in conjunction with the appended drawings, wherein like or similar reference numerals denote like or similar elements, and wherein:

FIG. 1 illustrates a flow chart of a modeling method for a state grammar module in RTL according to one embodiment of the disclosure;

FIG. 2 illustrates a data structure schematic of a hierarchical tree according to an embodiment of the present disclosure;

FIG. 3 illustrates an parsing schematic of a state grammar module according to one embodiment of the disclosure;

FIG. 4 illustrates a sentence grammar schematic of a state grammar module in accordance with one embodiment of the disclosure;

FIG. 5 illustrates a schematic diagram of a modeling system for a state grammar module in RTL according to one embodiment of the disclosure;

fig. 6 shows a schematic diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. The exemplary embodiments of the present invention and the descriptions thereof are used herein to explain the present invention, but are not intended to limit the invention.

The term "comprising" and variations thereof as used herein means open ended, i.e., "including but not limited to. The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment. The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

Additionally, the steps illustrated in the flowcharts of the figures may be performed in a computer, such as a set of computer executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.

FIG. 1 illustrates a flow chart of a modeling method for a state grammar module in RTL according to one embodiment of the disclosure. As shown in fig. 1, the method may include:

And S1, analyzing and acquiring a state grammar Module in each Module in the RTL file layer by layer.

Wherein the RTL (REGISTER TRANSFER LEVEL ) file may describe the HDL level of a circuit by describing the logical function from register to register. The RTL file is mainly a hardware description language design file, and mainly used hardware description languages are Verilog and System Verilog. Each Module under the whole hierarchical design can be analyzed layer by layer according to the hierarchical design structure of the hardware description languages Verilog and System Verilog, and a state grammar Module (STATEMENT BLOCK) corresponding to each main hierarchical expression Module (Module) is obtained.

In an example, the layer-by-layer analysis and retrieval of the state syntax Module (STATEMENT BLOCK) in each Module in the RTL file may include:

And analyzing the grammar tree memory structure in the RTL file by using an analyzer, and storing the grammar tree memory structure into the memory of the computer. The grammar tree memory structure is used for storing logic relation, logic level and grammar expression of hardware integrated circuit design in the RTL file.

And performing layer-by-layer analysis from each Module of the grammar tree memory structure in an iterative traversal mode to obtain pointers pointing to each Module.

In one example, the steps may be to utilize an iterative traversal method to start from each Module of the syntax tree memory structure, take each logic expression Module (Instance) as a branch, analyze leaf nodes of each node of the syntax tree memory structure layer by layer respectively using a recursive traversal method, process the syntax tree memory structure stored in the memory of the computer while traversing, reconstruct a new hierarchical structure tree (HIERARCHY TREE) according to the leaf nodes of each node of the syntax tree memory structure, and obtain pointers to each Module according to the hierarchical structure tree. Design correctness is ensured by constructing a data structure of the hierarchical structure tree (HIERARCHY TREE).

FIG. 2 illustrates a data structure schematic of a hierarchical tree according to an embodiment of the present disclosure.

As shown in FIG. 2, the hierarchical tree (HIERARCHY TREE) data structure mainly has a Module pointer, an Instance pointer, a Module Item pointer, a Parent pointer, and a child pointer. The device comprises a Module pointer, an Instance pointer, a Parent pointer, a callback function pointer, a pointer and a callback algorithm pointer, wherein the Module pointer is used for pointing to a current Module, the Instance pointer is used for pointing to an Instance contained in the current Module, the Module Item pointer is used for pointing to a Block structure except for the current Module, the Parent pointer is used for pointing to a Parent level Module of the current Module, and the child pointer is used for pointing to an Instance contained in the current Module, and the callback function pointer is used for executing a callback algorithm in the traversal process. The data structure using the hierarchical tree (HIERARCHY TREE) may be used as a data base for subsequent grammar processing operations.

And when judging that the content of the Module is a state grammar Module, acquiring a pointer pointing to the state grammar Module and a structure of the state grammar Module.

For example, as shown in fig. 2, the pointer of each Module in the whole hierarchical design is obtained by a recursive traversal manner, so as to obtain the contents (Module Item) of all the main hierarchy expression modules in the modules pointed by the pointer of the Module, and by judging the contents (Module Item) of the main hierarchy expression modules, if the contents (Module Item) of the main hierarchy expression Module pointed by the current Module pointer are the state grammar modules (STATEMENT BLOCK), all the state grammar Module (STATEMENT BLOCK) pointers and structures under the main hierarchy expression modules are obtained.

Through the step, a state grammar Module (STATEMENT BLOCK) corresponding to each main hierarchy expression Module under the whole hierarchy design can be obtained.

And S2, analyzing the interconnection relation of the state grammar Module in the Module to obtain the input and output ports corresponding to the state grammar Module.

In one example, this step may include analyzing the interconnect signal of the state grammar Module within the Module and tracing back the driving direction of the interconnect signal. For example, the driving direction of the interconnection signal can be obtained by tracing the input and output of the interconnection signal according to the interconnection signal of the state grammar module. And acquiring the input and output ports corresponding to the state grammar Module according to the interconnection relation.

For example, for different state grammar modules (STATEMENT BLOCK), the composition grammar of the state grammar Module (STATEMENT BLOCK) and the interconnection signal used by the current grammar block in the parent Module thereof are analyzed, and the driving direction of the interconnection signal is traced, so that the interconnection relation between the interior of the Module where the state grammar Module (STATEMENT BLOCK) is located and other modules is obtained, and further, the corresponding input and output ports are extracted, and meanwhile, special grammars such as complex expressions, check sentences, state machine sentences, interface body sentences, class sentences, register type wire network structures and the like are processed.

And step S3, re-modeling the state grammar Module according to the interconnection relation and the driving direction to obtain a Module conforming to the hardware description language standard.

For example, the analyzed state grammar Module (STATEMENT BLOCK) obtained in step S2 is re-modeled, and the state grammar Module (STATEMENT BLOCK) is a reasonable Module meeting the Verilog grammar definition, i.e., a Module meeting the IEEE standard for defining the Verilog grammar without violating the grammar semantics and grammar standard.

And S4, reconstructing the Module which accords with the hardware description language standard into a logic expression Module, and instantiating the logic expression Module to the internal position of the Module where the state grammar Module is located. The Module can be reconstructed into a logic expression Module by adding, subtracting, multiplying, dividing, and, or not analyzing the logic symbol of the Module conforming to the hardware description language standard.

And S5, adding input and output ports and an internal network connected with the input and output ports to the logic expression Module according to the interconnection relation of the state grammar Module in the Module to obtain a model file of a main hierarchical tree structure only comprising the Module and the logic expression Module.

For example, as shown in FIG. 2, the type of the state grammar module (STATEMENT BLOCK) is parsed, and the type multi-sequential logic grammar module (ALWAYS STATEMENT) of the parse state grammar module (STATEMENT BLOCK) is also the continuous assignment grammar module (ASSIGN STATEMENT). Then, the interconnection relation of the state grammar Module (STATEMENT BLOCK) is further analyzed, the input-output interconnection of the state grammar Module (STATEMENT BLOCK) is determined, and the network interconnection relation inside the parent-level main hierarchy expression Module where the current state grammar Module (STATEMENT BLOCK) is located is expressed according to the network interconnection relation. The interconnection relationship is mainly that a Module pointer pointed in a data structure of a hierarchical structure tree (HIERARCHY TREE) shown in fig. 2 is traversed to obtain a Net interconnection relationship in a current Module, input, output and the like, a specific logic expression in a current state grammar Module (STATEMENT BLOCK) is analyzed, and an input/output signal in the current state grammar Module (STATEMENT BLOCK) is obtained by carrying out addition, subtraction, multiplication, division, AND, or non-equal split analysis on a logic symbol. And re-creating a Module conforming to the hardware description language standard according to the interconnection relation of the state grammar Module (STATEMENT BLOCK) and the input/output signal, adding the input/output signal to the Module conforming to the hardware description language standard, copying the original state grammar Module (STATEMENT BLOCK) into the Module conforming to the hardware description language standard, further checking the interconnection relation, and ensuring the correctness of the currently constructed Module conforming to the hardware description language standard. Meanwhile, the Module conforming to the hardware description language standard is instantiated as a new logic expression Module (Instance) to the underside of the original state grammar Module (STATEMENT BLOCK).

In analyzing the state grammar module (STATEMENT BLOCK), various grammars may exist, such as a multi-timing logic grammar module (Always block), a continuous assignment grammar module (Assign block), an initialization module (Initial block), a Function module (Function block), a system Function module (System Function block), a type enumeration module (Typedef enum block), and the like.

The following takes a state grammar Module in Module a as an example to describe a modeling method for a state grammar Module in RTL in the present disclosure.

Fig. 3 shows an parsing diagram of a state grammar module according to an embodiment of the present disclosure, and fig. 4 shows a sentence grammar diagram of the state grammar module according to an embodiment of the present disclosure.

As shown in fig. 3, first, a pointer of a Module a is obtained through a hierarchical tree (HIERARCHY TREE) data structure, by analyzing the content (Module Item) of the main hierarchy expression Module pointed to by the pointer of the Module a, when the content (Module Item) of the current main hierarchy expression Module is judged to be a state grammar Module (STATEMENT BLOCK), all state grammar modules (STATEMENT BLOCK) can be obtained by judging the pointer of the state grammar Module (STATEMENT BLOCK), and at the same time, the grammar type of the state grammar Module (STATEMENT BLOCK) statement block and expression information in the grammar statement block are further analyzed, and the specific content is shown in fig. 4.

The interconnection information in the current state grammar module (STATEMENT BLOCK), i.e., the input and output in each expression, is obtained by analyzing the expression information in the grammar statement block. The method comprises the steps of constructing a new Module which accords with the hardware description language standard, adding the input and output of a state grammar Module (STATEMENT BLOCK) obtained in the process at the port of the Module which accords with the hardware description language standard as the port, and finally re-instantiating the Module which accords with the hardware description language standard to the internal position of the Module where the state grammar Module (STATEMENT BLOCK) is located, so that no other grammar logic blocks except a logic expression statement block (Instance) are arranged in the Module A.

According to the modeling method for the state grammar Module in RTL, the RTL-level hardware description language of the original input is modeled through the state grammar Module (STATEMENT BLOCK), so that the hierarchical structure of the original input design is more reasonable, namely, the whole design is composed from top to bottom to be a basic Module, instance Module, port, wire, state sentence Module and the like, and the hierarchical structure of the original design is not directly reflected, so that when the method is used for segmentation in follow-up, only the logic expression Module (Instance) is needed to be considered to be segmented, the complex state grammar Module is not needed to be considered, and the operational convenience is further provided, meanwhile, the execution efficiency in simulation is effectively improved, and meanwhile, the method is designed after modeling the state grammar Module (STATEMENT BLOCK) is completed, and is convenient when the method is used for secondary development, for example, the method is used for greatly improving the efficiency and reducing the occupied memory and the processing complexity when the method is used for abstract structure of the hypergraph or tree structure, so that the processing efficiency and the accuracy of EDA software are improved.

The following are system embodiments of the present application that may be used to perform method embodiments of the present application. For details not disclosed in the system embodiments of the present application, please refer to the method embodiments of the present application.

FIG. 5 illustrates a schematic diagram of a modeling system for a state grammar module in RTL according to one embodiment of the disclosure, as shown in FIG. 5, the system may include:

The traversal Module 501 is configured to analyze and obtain, layer by layer, a state grammar Module in each Module in the RTL file;

The analysis Module 502 is configured to analyze an interconnection relationship of the state grammar Module in the Module, and obtain input and output ports corresponding to the state grammar Module;

a reconstruction Module 503, configured to re-model the state grammar Module according to the interconnection relationship and the driving direction, to obtain a Module that accords with the hardware description language standard;

A reconstruction Module 504, configured to reconstruct a Module that meets the hardware description language standard into a logic expression Module, and instantiate the logic expression Module to an internal location of the Module where the state grammar Module is located;

and the output Module 505 is used for adding input and output ports to the logic expression Module according to the interconnection relation of the state grammar Module in the Module, and an internal network connected with the input and output ports, and outputting a model file of a main hierarchical tree structure only comprising the Module and the logic expression Module.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.

In an embodiment of the invention, an electronic device is provided, including a processor and a memory storing a computer program, the processor being configured to perform the method of optimizing the area power consumption of any of the VLSI circuits of the embodiment of the invention when the computer program is run.

Fig. 6 shows a schematic diagram of an electronic device 1000 that may implement or implement embodiments of the present invention, and in some embodiments may include more or fewer electronic devices than shown. In some embodiments, it may be implemented with a single or multiple electronic devices. In some embodiments, implementation may be with cloud or distributed electronic devices.

Fig. 6 is a schematic structural diagram of an electronic device 10 according to an embodiment of the present application. As shown in fig. 6, the electronic device 1000 includes a processor 1001 that can perform various appropriate operations and processes according to programs and/or data stored in a Read Only Memory (ROM) 1002 or programs and/or data loaded from a storage portion 1008 into a Random Access Memory (RAM) 1003. The processor 1001 may be a multi-core processor, or may include a plurality of processors. In some embodiments, the processor 1001 may include a general-purpose main processor and one or more special coprocessors, such as a Central Processing Unit (CPU), a Graphics Processor (GPU), a neural Network Processor (NPU), a Digital Signal Processor (DSP), and so forth. In the RAM 1003, various programs and data necessary for the operation of the electronic apparatus 1000 are also stored. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

The processor and the memory are used together to execute a program stored in the memory, which when executed by a computer is capable of implementing the methods, steps or functions described in the above embodiments.

Connected to the I/O interface 1005 are an input section 1006 including a keyboard, a mouse, a touch screen, etc., an output section 1007 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc., a storage section 1008 including a hard disk, etc., and a communication section 1009 including a network interface card such as a LAN card, a modem, etc. The communication section 1009 performs communication processing via a network such as the internet. The drive 1010 is also connected to the I/O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in the drive 1010, so that a computer program read out therefrom is installed as needed in the storage section 1008. Only some of the components are schematically illustrated in fig. 6, which does not mean that the computer system 1000 includes only the components illustrated in fig. 6.

The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer or its associated components. The computer may be, for example, a mobile terminal, a smart phone, a personal computer, a laptop computer, a car-mounted human-computer interaction device, a personal digital assistant, a media player, a navigation device, a game console, a tablet, a wearable device, a smart television, an internet of things system, a smart home, an industrial computer, a server, or a combination thereof.

Although not shown, in an embodiment of the present invention, there is provided a storage medium storing a computer program configured to, when executed, perform any of the file difference-based compiling methods of the embodiment of the present invention.

Storage media in embodiments of the invention include both permanent and non-permanent, removable and non-removable items that may be used to implement information storage by any method or technology. Examples of storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, read only compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium which can be used to store information that can be accessed by a computing device.

Methods, programs, systems, apparatus, etc. in accordance with embodiments of the invention may be implemented or realized in single or multiple networked computers, or in distributed computing environments. In the present description embodiments, tasks may be performed by remote processing devices that are linked through a communications network in such a distributed computing environment.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Thus, it will be apparent to those skilled in the art that the functional modules/units or controllers and associated method steps set forth in the above embodiments may be implemented in software, hardware, and a combination of software/hardware.

The acts of the methods, procedures, or steps described in accordance with the embodiments of the present invention do not have to be performed in a specific order and still achieve desirable results unless explicitly stated. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Various embodiments of the invention are described herein, but for brevity, description of each embodiment is not exhaustive and features or parts of the same or similar between each embodiment may be omitted. Herein, "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that it is applicable to at least one embodiment or example, but not all embodiments, according to the present invention. The above terms are not necessarily meant to refer to the same embodiment or example. Those skilled in the art may combine and combine the features of the different embodiments or examples described in this specification and of the different embodiments or examples without contradiction.

The exemplary systems and methods of the present invention have been particularly shown and described with reference to the foregoing embodiments, which are merely examples of the best modes for carrying out the systems and methods. It will be appreciated by those skilled in the art that various changes may be made to the embodiments of the systems and methods described herein in practicing the systems and/or methods without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A modeling method for a state grammar module in RTL, characterized in that the method comprises:

Analyze and obtain the state syntax module in each module in the RTL file layer by layer;

Analyze the interconnection relationship of the state grammar module in the Module module to obtain the input and output ports corresponding to the state grammar module;

Remodel the state grammar module according to the interconnection relationship and the driving direction to obtain a Module module that complies with the hardware description language standard;

Reconstruct the Module module that complies with the hardware description language standard into a logic expression module, and instantiate the logic expression module to the internal position of the Module module where the state grammar module is located;

According to the interconnection relationship of the state grammar module within the Module module, input and output ports and an internal wire network connected to the input and output ports are added to the logic expression module to obtain a model file of the main hierarchical tree structure that only contains the Module module and the logic expression module.

2. The modeling method according to claim 1, characterized in that the layer-by-layer analysis and acquisition of the state syntax module in each module in the RTL file comprises:

Parsing the syntax tree memory structure in the RTL file using a parser;

Use iterative traversal to analyze each module layer by layer in the syntax tree memory structure and obtain a pointer to each module;

Get the content of each Module module according to the pointer of each Module module;

When it is determined that the content of the Module is a state grammar module, a pointer to the state grammar module and a structure of the state grammar module are obtained.

3. The modeling method according to claim 1 is characterized in that the interconnection relationship of the state grammar module in the Module module is analyzed to obtain the input and output ports corresponding to the state grammar module, including:

Analyze the interconnection signal of the state grammar module in the Module module, and trace the driving direction of the interconnection signal;

Obtain the interconnection relationship between the state grammar module and other modules in the Module module according to the driving direction;

The input and output ports corresponding to the state grammar module are obtained according to the interconnection relationship.

4. The modeling method according to claim 3, characterized in that tracing back the driving direction of the interconnection signal comprises:

According to the interconnection signal of the state grammar module, the input and output of the interconnection signal are traced back to obtain the driving direction of the interconnection signal.

5. The modeling method according to claim 2 is characterized in that the syntax tree memory structure is used to store the logical relationships, logical levels and syntax expressions of the hardware integrated circuit design in the RTL file.

6. The modeling method according to claim 5 is characterized in that each Module module of the syntax tree memory structure is analyzed layer by layer in an iterative traversal manner to obtain a pointer to each Module module, including:

Using an iterative traversal method, starting from each Module module of the syntax tree memory structure, taking each logical expression module as a branch, and analyzing the leaf nodes of each node of the syntax tree memory structure layer by layer;

A new hierarchical structure tree is reconstructed according to the leaf nodes of each node, and a pointer to each Module module is obtained according to the hierarchical structure tree.

7. The modeling method according to claim 6, characterized in that the module conforming to the hardware description language standard is reconstructed into a logic expression module, comprising:

The logic symbols of the Module module that conforms to the hardware description language standard are analyzed by addition, subtraction, multiplication, division, AND, OR, and NOT, and the Module module is reconstructed into a logic expression module.

8. A modeling system for a state grammar module in RTL, characterized in that the system comprises:

Traversing modules, used to analyze and obtain the state syntax modules in each module in the RTL file layer by layer;

An analysis module, used for analyzing the interconnection relationship of the state grammar module within the Module module, and obtaining the input and output ports corresponding to the state grammar module;

A reconstruction module, used for remodeling the state grammar module according to the interconnection relationship and the driving direction to obtain a Module module that complies with the hardware description language standard;

A reconstruction module, used for reconstructing the Module module conforming to the hardware description language standard into a logic expression module, and instantiating the logic expression module to the internal position of the Module module where the state grammar module is located;

The output module is used to add input and output ports and internal wire networks connected to the input and output ports to the logic expression module according to the interconnection relationship between the state grammar module in the Module module, and output a model file containing only the main hierarchical tree structure of the Module module and the logic expression module.

9. A storage medium having a computer program stored thereon, wherein the program implements the method according to any one of claims 1 to 7 when executed by a processor.

10. An electronic device, comprising: a processor and a memory storing a computer program, wherein the processor is configured to implement any one of the methods of claims 1-7 when running the computer program.