CN116298801A - Chip testing device, method, electronic equipment and storage medium - Google Patents

Abstract

The application discloses chip testing device, method, electronic equipment and storage medium belongs to chip testing technical field for solve a machine and only test a chip once, consuming time is longer, the lower problem of efficiency, the device includes: a plurality of test modules, each of the test modules comprising: the test seat is used for installing a target chip to be tested, and the peripheral, the memory and the power supply control circuit are matched with the target chip; the interface conversion module comprises a first interface which is in communication connection with the computer and a plurality of serial ports which correspond to the plurality of test modules, and each serial port is correspondingly connected with one test module; the interface conversion module receives a test instruction sent by the computer in a state of being connected with the computer, sends the test instruction to the test module, executes the test instruction by a target chip arranged on the test module and generates a test result, and the test result is fed back to the computer through the interface conversion module.

Description

Chip testing device, method, electronic equipment and storage medium

technical field

The application belongs to the technical field of chip testing, and in particular relates to a chip testing device, method, electronic equipment and storage medium.

Background technique

In the application process of the chip, it is usually necessary to test its function to determine whether it is put into use, including system-level testing. Generally, the chip is installed on the test motherboard, the memory and peripherals are configured, an operating system is started, and then the software is used. Toaster test, record results and compare.

In the prior art, manual testing is generally used, and one machine only tests one chip at a time. In the case of a fixed number of chip tests, if you want to improve the test efficiency, you need to add test machines for system-level testing, which will cause consumption Long time, low efficiency and high cost.

Contents of the invention

Embodiments of the present application provide a chip testing device, method, electronic equipment, and storage medium, which can solve the problems that a machine only tests one chip at a time, which takes a long time, has low efficiency, and is expensive.

In the first aspect, the embodiment of the present application provides a chip testing device, which includes a plurality of test modules, each of which includes: a test socket for installing a target chip to be tested, an outer shell matching the target chip Design, memory and power supply control circuit; an interface conversion module, including a first interface connected to the computer for communication, and a plurality of serial ports corresponding to the plurality of test modules, each of the serial ports is correspondingly connected to one of the test modules; When the interface conversion module is connected to the computer, it receives the test instruction sent by the computer, sends the test instruction to the test module, and executes the test instruction by the target chip installed on the test module and A test result is generated, and the test module feeds back the test result to the computer through the interface conversion module.

In the second aspect, the embodiment of the present application provides a chip testing method, which is applied to the chip testing device as described in the first aspect, including receiving the test instruction sent by the computer through the interface conversion module, and sending the test instruction to the corresponding a test module; execute the test instruction and generate a test result through the target chip installed on the test module; feed back the test result to the computer through the interface conversion module through the test module.

In a third aspect, an embodiment of the present application provides an electronic device, a processor; and a memory arranged to store computer-executable instructions, the executable instructions configured to be executed by the processor, and the executable instructions include It is used to execute the method as described in the second aspect.

In a fourth aspect, an embodiment of the present application provides a readable storage medium, wherein the storage medium is used to store computer-executable instructions, and the computer-executable instructions cause a computer to perform the method described in the second aspect .

In the fifth aspect, the embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions, so as to implement the second aspect the method described.

The chip test device provided in the embodiment of the present application includes a plurality of test modules, and each test module includes a test socket installed with a target chip to be tested, a peripheral device matched with the target chip, a memory and a power supply control circuit, the device It also includes an interface conversion module, the interface conversion module includes a first interface connected with the computer for communication, and a plurality of serial ports corresponding to a plurality of test modules, and each serial port is correspondingly connected to a test module. When the interface conversion module is connected to the computer, it receives the test instructions sent by the computer and sends the test instructions to each test module, wherein the computer is connected to the first interface of the conversion module, and the first interface is connected to multiple test modules through the serial port. And send instructions to each test module through the serial port, and one computer can correspond to multiple test modules. Then the target chip installed on the test module executes the test instructions and generates test results. The test module feeds back the test results to the computer through the interface conversion module, wherein the test instructions are executed by the chip installed on the test module, and the test results are fed back to the computer. The computer can complete the test of the chip. It can be seen that through the chip test device, one computer can test multiple chips, which solves the problem that a machine only tests one chip at a time, which takes a long time, has low efficiency and high cost. question.

Description of drawings

Fig. 1 is a schematic flow chart of a method provided by the embodiment of the present application;

Fig. 2 is a flow chart of a chip testing method according to the present application;

Fig. 3 is a schematic flow diagram of a scene of a chip testing method according to the present application;

4 is a schematic structural diagram of a chip testing device provided in an embodiment of the present application;

Fig. 5 is a schematic diagram of a hardware structure of a device according to the present application.

Detailed ways

The embodiments of the present application provide a chip testing device and method, which are used to solve the problems that a machine only tests one chip at a time, which takes a long time, has low efficiency and high cost.

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first", "second" and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific sequence or sequence. It should be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application can be practiced in sequences other than those illustrated or described herein, and that references to "first," "second," etc. distinguish Objects are generally of one type, and the number of objects is not limited. For example, there may be one or more first objects. In addition, "and/or" in the specification and claims means at least one of the connected objects, and the character "/" generally means that the related objects are an "or" relationship.

After the chip is mass-produced, it will generally go through several testing stages: wafer testing-packaging stage-testing and packaging. After passing several tests, the chip can be shipped to customers. In the process of chip testing, because packaging chips also has overhead, in order to save costs as much as possible, a part of the test may be carried out before chip packaging to eliminate some broken chips. After testing before packaging, The test after packaging is also essential, but for companies or products with relatively high requirements, after the package test is passed, system-level testing is required to test whether the functions of specific modules are normal. After several tests pass, the chip It can be shipped to customers. This application introduces in detail the system-level testing of packaged chips.

A chip testing device, method, electronic equipment, and storage medium provided in the embodiments of the present application will be described in detail below through specific embodiments and application scenarios with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a chip testing device provided by an embodiment of the present invention, and the device includes a plurality of testing modules 13 and an interface conversion module 12 .

Wherein, each test module 13 includes a test socket 132 installed with a target chip 131 to be tested, a peripheral device 134 matching the target chip 131 , a memory 135 and a power control circuit.

The test module has slots such as a test socket Socket132, peripherals 134, a memory 135 and a power control circuit for testing the chip installed on the test socket Socket132. The following description takes the test module as an example of a Site module, where Site means a location, for example, 4Site is the location of 4 test chips, which can also be simply understood as 4 test modules.

The test socket Socket 132 matched with the target chip 131 is a slot for holding the target chip 131 , and its main function is to connect the chip with a printed circuit board (PCB). The test socket 132 is fixed on the PCB, and the target chip 131 is placed in the test socket 132. There is a corresponding cover on the test socket 132, so that the target chip 131 can work normally without being directly soldered on the PCB. The target chip 131 is a chip to be tested, and the chip may be of the same batch type or not of the same type.

The Site module also includes peripheral hardware 134, memory 135 and power control circuit matched with the target chip 131, wherein the peripheral hardware 134 can include multiple types, and the functions of different types of chips are different, and the peripheral hardware 134 is also different, for example, It can be set as the control circuit, read-write circuit, and program memory rom for making the chip run; the memory 135 is used to store or cache the program of the system level test, such as double-rate synchronous dynamic random access memory (Double Data Rate, DDR), embedded Embedded Multi Media Card (EMMC), flash memory FLASH, etc.; the power control circuit is used to control the entire circuit of the Site module 13.

By arranging multiple Site modules 13 , multiple target chips 131 can be matched, so that multiple target chips can be detected at one time in the subsequent testing process.

Wherein, the interface conversion module 12 includes a first interface communicating with a computer, and a plurality of serial ports 121 corresponding to a plurality of Site modules 13, and each serial port is correspondingly connected to a site module 13.

Specifically, the first interface connected to the computer for communication, for example, a Universal Serial Bus hub (Universal Serial Bus-HUB, USB-HUB), a kind of interface that can expand a Universal Serial Bus (Universal Serial Bus, USB) to multiple, and can enable simultaneous use of these interfaces on the device.

A plurality of serial ports 121 corresponding to a plurality of Site modules 13, including a Universal Asynchronous Receiver/Transmitter (UART), is used to control a chip 131 of a computer and a serial device, that is, to connect the computer and to connect the computer to the serial device. The target chips 131 of the device communicate with each other, and transmit the instructions issued by the computer to the target chip 131, or feed back the information of the target chip 131 to the computer.

In summary, the computer is connected to the first interface, the first interface is connected to the serial port 121, and the serial port 121 is connected to the Site module 13, so that the Site module 13 is communicatively connected to the computer, and the instructions of the computer can be converted to the target chip 131 on the Site module 13, that is, the computer Communicate with the target chip 131 under test through the USB-to-UART121 chip.

Interface conversion module 12 is under the state that is connected with computer, receives the test instruction that computer sends, and test instruction is sent to test module 13, carries out test instruction and generates test result by the target chip 131 that is installed on test module 13, and test module 13 The test result is fed back to the computer through the interface conversion module 12.

The first interface in the interface conversion module 12 is connected with the computer, and is connected with a plurality of serial ports 121 at the same time, and each serial port 121 is correspondingly connected with the Site module 13, and when the computer issues a test order, each Site module 13 can receive the test order, Because target chip 131 is installed on this Site module 13, target chip 131 can carry out test instruction automatically, and generate test result, computer can read the test information of target chip 131 by UART121, and Site module 13 is fed back test result to computer .

The target chip 131 executes the test instruction and generates the test result, including that the target chip 131 carries and runs the test program from the program in the internal memory 135 of the Site module 13 in the process of performing the test, and starts to test each peripheral 134 Conduct the test and record the test results, which include pass and fail.

The chip testing device 1 in the embodiment of the present application includes a plurality of test modules 13, that is, a plurality of Site modules 13, and each Site module includes a test socket 132 for installing a target chip 131 to be tested, matched with the target chip 131 Peripheral hardware 134, memory 135 and power control circuit, also comprise interface conversion module 12, and this interface conversion module 12 comprises the first interface that is connected with computer communication, and a plurality of serial ports 121 corresponding with a plurality of Site modules 13, each The serial port 121 is correspondingly connected to one site module 13 . Interface conversion module 12 is under the state that is connected with computer, receives the test instruction that computer sends, and test instruction is sent to each Site module 13, and wherein, computer connects the first interface of conversion module, and first interface connects a plurality of by serial port 121 Site module 13, and send instructions to each Site module 13 through the serial port 121, and one computer can correspond to multiple Site modules 13. Then the target chip 131 installed on the Site module 13 carries out the test instruction and generates the test result, and the Site module 13 feeds back the test result to the computer through the interface conversion module 12, wherein the target chip 131 on the site carries out the test instruction, and the test result The result is fed back to the computer, and the test of the target chip 131 can be completed. It can be seen that through the chip testing device 1, one computer can test multiple chips, which solves the problem that a machine only tests one chip at a time, which takes a long time and is relatively efficient. Low and high cost issues.

In an implementation manner, the chip testing device includes:

The test module 13 receives the instruction to obtain the test module identification sent by the computer through the serial port 121 ; the test module 13 sends the test module identification to the computer through the interface conversion module 12 .

Specifically, the test module identification is also the Site identification, and the instruction of the test module identification is the instruction of the Site identification, and the instruction includes that the computer sends the order of "obtaining the Site number" to the serial port 121 of each Site module 13 respectively, and the Site identification is the Site number, Among them, the Site number can be numbered through the pull-down combination of the general-purpose input and output GPIO (General-purpose input/output, GPIO). Feedback uploading, at this time the Site module 13 can upload the Site logo to the computer through the serial port 121.

In this embodiment, the computer sends the "acquire site number" command to the serial port 121 of each Site module 13 through the USB to serial port 121 chip, and the target chip 131 to be tested will feed back the current corresponding site through the Site module 13 and the corresponding serial port 121. number, the computer can receive the Site ID fed back by the Site module 13. The computer obtains the Site identification, and when n target chips 131 are tested simultaneously, each target chip 131 in the test socket 132 has a unique Site number, so that the robot arm grabs the target chip 131 after the subsequent test, and performs a test on the target chip 131. Classification operation, for example, after the target chip 131 in the Site module 13 finishes testing, the target chip 131 types in a plurality of Site modules 13 tested simultaneously are different, and the test results of the target chip 131 in different Site modules 13 are different, corresponding Therefore, acquiring the corresponding Site ID of the Site module 13 is convenient for distinguishing different chips in each Site module 13, which can improve efficiency and save time during the classification operation.

In an implementation manner, the chip testing device includes:

The test module 13 receives the instruction to obtain the identification of the target chip 131 sent by the computer through the serial port 121 corresponding to the test module 13; the test module 13 sends the corresponding identification of the target chip 131 to the computer through the interface conversion module 12.

Wherein, the instruction of the target chip 131 identification refers to that the computer transfers the serial port chip through the first interface, and sends respectively to the serial port 121 of each Site module 13 the command to obtain the chip ID (Chip Identification, Chip ID), and the ChipID is the chip identification , the target chip 131 to be tested has been burnt into the one-time programmable memory efuse before leaving the factory. After completion, the test will be carried out, and the information of the chip will be written into efuse. Therefore, the identification is unique and cannot be changed. Specifically, the test result can be queried through the upper computer of the computer, wherein the Chip ID of the chip is bound to the test result, so that the unique correspondence between the tested target chip 131 and the test result can be realized.

In this embodiment, the Site module 13 receives the instruction sent by the computer to obtain the target chip 131 identification, and the target chip 131 obtains the chip identification of the target chip 131 from efuse, and the Site module 13 sends the target chip 131 identification through the interface conversion module 12 to computer. The target chip 131 identification records the unique information of each chip, and then the test result of the target chip 131 can be uniquely corresponding to the target chip 131, which is convenient for subsequent tracing of each chip. For example, when the computer checks the target chip 131 test As a result, a problem arises, the identification of the corresponding target chip 131 can be found, and then the corresponding target chip 131 can be found, and it is also convenient to classify the passed and unqualified target chips 131 .

In an implementation manner, the test instruction of the chip testing device includes two situations:

When the test instructions are executed in parallel, multiple test modules 13 receive the test instructions executed in parallel, and feed back the generated test results to the computer through the interface conversion module 12 .

The test instruction of parallel execution comprises that when computer sends test instruction to Site module 13, this test instruction is to obtain the test result of target chip 131 to be tested in each Site module 13, so each target chip 131 executes test instruction simultaneously, namely The test program is run, and at the same time, the test results of the target chips 131 in each Site module 13 are fed back to the computer through the first interface and the serial port 121 in the interface conversion module 12 .

It should be noted that, during the testing process of the target chip 131, several target chips 131 can simultaneously execute test instructions and feed back the test results to the computer. The target chips 131 in 13 are tested one by one, and the test results are fed back to the computer. In the process of executing the test command, the target chip 131 can be placed in each corresponding Site module 13 for the same type of chip, and its corresponding peripherals 134 are also the same. Optionally, each Site module 13 can also be If the target chips 131 are of different types, the corresponding peripherals 134 are not exactly the same. At the same time, the test program will also be different from the previous target chips 131 of the same type.

The target chips 131 in the plurality of Site modules 13 execute parallel test instructions, which can complete simultaneous testing of multiple chips, thereby improving test efficiency and output.

or,

When the test instructions are executed in a preset sequence, the multiple test modules 13 receive the test instructions one by one in a preset sequence, and feed back the generated test results to the computer through the interface conversion module 12 .

The test instructions executed in a preset order, including the instructions received by each Site module 13, are in order, and the order is unchanged, and a test result can be completed after the test instructions are executed in order. Specifically, when you want to test In the case of task A, the execution of task A needs to be divided into three steps, namely A1, A2, and A3, and the steps are sequential and irreversible, that is, the execution process of A2 needs the execution result of A1, and the execution process of A3 needs As a result of the execution of A2, the three steps work together, then the target chip 131 in the first Site module 13 corresponds to execute A1, the target chip 131 in the second Site module 13 corresponds to execute A2, and the third Site module The target chip 131 in 13 corresponds to execute A3, and the test result of task A is completed only after A3 is finally executed, and the test result of the target chip 131 in the third Site module 13 is fed back to the computer through the interface conversion module 12.

The test instructions executed by the target chips 131 in the plurality of Site modules 13 in a preset order can test each task in order to complete the overall test result of the task, without the need to test a chip with a single function, and then here Based on testing another function of the chip. By setting up the cooperative work of the target chip 131, the test results of the target task can be directly fed back to the computer, and there is no need to test the chip with the same function, and then test the chip with another function, and finally combine the chips with the two functions , to get the target task, this sequential test can combine and test the chips with various functions of the task in order, and finally get the test result, through the above-mentioned chips participating in the test together, it can be known in advance whether the various functional chips exist in the testing stage In the case of unsuccessful function matching or matching errors, and when a product containing chips with the above-mentioned multiple functions is generated, all chips in a product can be tested directly, thereby improving test efficiency.

In this embodiment, the test command sent by the computer can be a test command executed in parallel or a test command executed in a preset order. When the target chip 131 executes the test command in parallel, it can simultaneously test chips with the same function. When the target chips 131 execute the test instructions in a preset order, the target chips 131 in each Site module 13 work together to complete a test task. Both methods can improve the test efficiency. It is not necessary to test only one chip at a time. A computer can test multiple chips at the same time. The Site module 13 receives instructions from the computer and feeds back the test results to the computer, all of which are automatically completed by the system , does not require too much manual operation, which obviously improves the efficiency.

In one implementation, the chip testing device also includes: a single-chip microcomputer module 11,

The single-chip microcomputer module 11 is connected to a computer through a serial port 121, receives a power-on command issued by the computer to the single-chip microcomputer module 11, and controls multiple test modules 13 to power on according to the power-on command.

The single-chip microcomputer module 11 includes but is not limited to the single-chip microcomputer STM32, and the computer sends a power-on command to the STM32 through the serial port 121 in the interface conversion module 12, and the STM32 powers on the Site module 13, that is, after the STM32 receives the "start" test command sent by the computer , the STM32 controls the power control circuit in the Site module 13 to power on the target chip to be tested.

It should be noted that before the computer sends commands, STM32 must first perform system initialization, and then wait for the computer to send commands. The Site module 13 sends the test results performed by the target chip 131 to the computer. After the computer receives the test results, it displays the test results and sends a power-off command to the STM32 through the serial port 121. The STM32 receives the "end" test command sent by the computer. Afterwards, the STM32 controls the power supply control circuit of the target chip 131 to power off the target chip 131 .

In this embodiment, the single-chip microcomputer module 11 can control the start and end of the test by controlling the power control circuit of the target chip 131 to be tested, and then controlling the power on and off of the Site module 13 .

In an implementation manner, the chip testing device further includes: a chip mounting module 41,

The chip implementation module 41 is used to remove the target chip 131 on the target site module 13 according to the test end command after the target test module 13 receives the test end command, and install the next target to be tested on the target site module 13 Chip 131.

In this embodiment, the chip-mounting module 15 is, for example, a manipulator. When the Site module 13 executes the target chip 131 to complete the test command and then feeds back the test result, and the Site module 13 receives the end of the test command and powers off, then , the chip execution module 15 can automatically remove the target chip 131 on the site module 13, and place the next target chip 131 to be tested on the test socket 132 to wait for testing. Before the computer sends the start test command, the manipulator will also Put n chips to be tested in n test sockets 132 corresponding to n site modules 13. This process does not require manual operation, and the chip execution module 41 can automatically execute the target chip 131 in the test socket 132 in the Site module 13. Pick and place saves time, reduces labor costs, and avoids errors caused by human factors.

In summary, in the embodiment of the present application, the chip testing device 1 includes a plurality of Site modules 13 and an interface conversion module 12, and the interface conversion module 12 receives the test command sent by the computer and sends the test command in the state of being connected to the computer. To each Site module 13, wherein, the computer is connected to the first interface of the interface conversion module 12, the first interface connects a plurality of Site modules 13 and the single-chip microcomputer module 11 through the serial port 121, and the computer sends instructions to each Site module 13 through the serial port 121, One computer can correspond to a plurality of Site modules 13 . The single-chip microcomputer module 11 can power on and off the Site module 13. After the single-chip microcomputer module 11 powers on the Site module 13, the computer obtains the Site identification of the Site module 13 through the serial port 121, and obtains the target chip identification in the corresponding Site module 13 through the Site identification. , then the target chip 131 installed on the Site module 13 carries out the test instruction and generates the test result, and the Site module 13 feeds back the test result to the computer through the interface conversion module 12, wherein the target chip 131 automatically executes the test by the Site module 13 instructions, and the test results are automatically fed back to the computer, and the chip test can be completed. It can be seen that through the chip test device 1, automatic testing can be performed, and at the same time, one computer can test multiple chips without adding too many computers for system testing. The number of units is reduced, and the cost is reduced, which solves the problem that one machine only tests one chip at a time, which takes a long time, has low efficiency and high cost.

Fig. 2 shows the flow chart of a kind of chip test method provided by one embodiment of the present invention, and this method is applied to as above-mentioned chip test device, comprises the following steps:

S202, receiving the test instruction sent by the computer through the interface conversion module 12, and sending the test instruction to the corresponding test module 13.

The interface conversion module 12 can be connected to a computer, and send the test command of the computer to each test module, that is, the Site module 13 , so that one computer can be connected to multiple Site modules 13 .

S204, execute the test instruction through the target chip 131 installed on the test module 13 and generate a test result.

Each Site module 13 is equipped with a target chip 131, according to the computer in step S202 can issue instructions to each Site module 13 through the interface conversion module 12, wherein the target chip 131 on the Site module 13 can be executed according to the test instruction , and generate test results. Specifically, the computer needs to obtain the Site identification corresponding to the Site module 13, and then obtain the chip identification corresponding to the target chip 131 in each Site module 13. After obtaining the identification, the target chip 131 executes the test command and generates the test result.

S206, the test result is fed back to the computer through the interface conversion module 12 through the test module 13 .

According to the test result in S204, each Site module 13 can feed back the test result to the computer through the interface conversion module 12.

In this embodiment, a computer can connect a plurality of Site modules 13 through the interface conversion module 12, and can send test instructions to corresponding Site modules 13 at the same time, and the target chip in the Site module 13 executes the test according to the test instructions, and the The test result is fed back to the computer, and the test program operation and test result upload in the multi-Site module 13 can be realized without human intervention, and automatic upload can be realized. Testing at the same time solves the problem that one machine only tests one chip at a time, which takes a long time, has low efficiency and high cost.

In an implementation manner, the test instructions in the chip test method include:

The computer automatically generates test instructions according to preset chip test rules according to the target chips 131 installed on the multiple test modules 13 .

The computer can automatically generate test instructions according to the functions in the installed target chips 131 in multiple Site modules 13. Specifically, when the target chips 131 are placed in the test socket 132, when the STM32 powers on the target Site module 13 , the computer can obtain the chip ID, and automatically generate test instructions according to the model of the target chip and the function to be tested. After the Site module 13 receives the test instruction, the target chip 131 in it can automatically execute the test instruction, and automatically feed back the test instruction to computer.

As an example, after the computer obtains the identification of each chip to be tested, it can automatically generate corresponding test instructions. The chip testing device includes 3 Site modules. If each Site module is installed with the same chip A to be tested, the computer After obtaining the chip identification of the chip A to be tested, generate the first test instruction about testing the chip A, and send it to the 3 Site modules in parallel, and then the chips in each Site module execute the first test instruction to Complete the final test results.

If chip B, chip C, and chip D are installed on the three Site modules for co-processing, chip C needs to perform data processing based on chip B’s test result 1 to generate test result 2 when chip C is tested, and chip D needs to be tested Data processing is performed based on the test result 2 of the chip C to generate the final test result 3 . Then the computer generates the second test instruction after obtaining the above-mentioned identifications of chip B, chip C and chip D, so that the three chips cooperate to process the test instructions in a specified order to generate the final test result.

If the chip E, chip F and chip G are installed on the three Site modules, after the computer obtains the identification of each chip, it will generate the third test instruction. Both the first test instruction and the second test instruction are different.

In this embodiment, since the computer is based on the test instructions generated by the target chip identification, in addition to being able to realize the automatic detection of the target chip 131, it can also further realize a variety of different chip test requirements based on the pre-established target chip 131 test rules, satisfying The chip testing methods are more flexible and abundant, and the computer can automatically generate test instructions according to the preset test rules of the target chip 131 to be tested, without excessive human intervention, which saves time and improves efficiency.

In summary, the computer is connected to the conversion module, and the conversion module sends the test instructions of the computer to a plurality of Site modules 13, and the target chip 131 in the Site module 13 executes the test according to the test instructions, and the Site module 13 passes the test results through the interface conversion module 12 automatically feeds back to the computer, and can complete the test of the target chip 131. It can be seen that this method can realize automated testing, and at the same time, one computer can test multiple chips, which solves the problem that a machine only tests one chip at a time, which takes a long time , lower efficiency and higher cost.

Scenario Example:

Fig. 3 is a schematic flowchart of an application scenario of a chip testing method according to an embodiment of the present specification. In this embodiment, the method includes the steps of:

S302 , the manipulator puts n chips to be tested into n test sockets 132 of n Site modules 13 .

Before the system-level test starts, the manipulator places a plurality of packaged target chips 131 to be tested on the test socket 132 in the Site module 13 .

S304, the STM32 performs initialization.

Power on the chip testing device 1, initialize the STM32 system, and wait for the computer to send commands.

S306, the computer sends a "start" test command to the STM32 through the UART121 interface.

S308, power on the STM32 chip to be tested.

According to step S306, after the STM32 receives the "start" test command sent by the computer, the STM32 controls the power supply control circuit to power on the chips to be tested in each Site module 13 .

S310, the computer obtains the Site identifier.

Through step S308, after the chip to be tested is powered on, the computer sends the "acquire site identification" command to the serial port 121 of each Site module 13 through the USB to 121 chip, and the chip to be tested will feed back the current corresponding Site identification through the serial port 121.

S312. The computer acquires the chip ID.

Through step S310, after the computer obtains the Site identification, the computer continues to send the "obtain chip ID" command to the serial port 121 of each Site module 13 through the USB-to-serial port 121 chip, and the chip to be tested will obtain the chip ID of the chip from efuse. The serial port 121 feeds back the corresponding chip ID.

S314, the chip to be tested executes a test program and feeds back a test result.

After the chip to be tested feeds back the chip ID to the computer according to step S312, the test program is transferred from the memory 135 and the test program is run, and each peripheral device 134 is tested, and the test results are recorded. After the system-level test is completed, the tested chip feeds back the test results to the computer through UART121 according to the test situation.

S316, the computer sends a power-off instruction to the STM32.

After the computer receives the S314 test result, it displays the test result, and sends a "power off" test command to STM32 through UART121. After STM32 receives the "power off" test command sent by the computer, STM32 controls the power control circuit of the chip under test to power off the chip under test.

S318, the manipulator takes out the n tested chips into the tray, and waits for the next round of testing.

The robotic arm in this process is able to sort the chips, separating those that pass from those that do not.

In the example of this scenario, the manipulator can automatically pick and place the tested chip, avoiding the problem of irregular chip placement and the problems introduced by some human factors. The single-chip microcomputer STM32 can power on and off the chip to be tested by controlling the power control circuit Electricity, a computer can test the chips in multiple Site modules 13, and obtain the Site logo and chip ID at the same time, which is convenient for classifying and tracing the tested chips, and the chip to be tested can automatically execute the test program and feed back the test results to the computer , and the computer can also send instructions automatically. After the test is over, the manipulator will automatically take out the tested chip and wait for the next round of testing. In summary, during this process, just click "Start Test" on the computer and turn on the power switch, the entire system test process will run according to the process steps set by the program, and complete the upload of the final results and the classification of the test chips, which improves the degree of automation of the test and solves the problem that a machine only tests one chip at a time, which is time-consuming. long, low efficiency and high cost.

4 is a schematic structural diagram of a chip testing device according to an embodiment of the present invention. As shown in the figure, a chip testing device includes: a testing module 13 , an interface conversion module 12 , a single-chip microcomputer module 11 , and a chip mounting module 41 .

In one implementation, a plurality of test modules 13, each of the test modules 13 includes: a test socket 132 for installing a target chip to be tested, a peripheral device 134 matched with the target chip 131, a memory 135 and Power control circuit;

The interface conversion module 12 includes a first interface connected to the computer for communication, and a plurality of serial ports 121 corresponding to the plurality of test modules 13, and each of the serial ports 121 is correspondingly connected to one of the test modules 13;

When the interface conversion module 12 is connected to the computer, it receives the test instruction sent by the computer, sends the test instruction to the test module 13, and executes it by the target chip 131 installed on the test module 13. The test command generates a test result, and the test module 13 feeds back the test result to the computer through the interface conversion module 12 .

In one implementation, the test module 13 is configured to receive an instruction for obtaining the test module identification sent by the computer through the serial port 121, and the test module 13 converts the test module to the test module through the interface conversion module 12. ID is sent to the computer.

In one implementation, the test module 13 is further configured to receive an instruction for obtaining the target chip 131 identifier sent by the computer through the serial port 121 corresponding to the test module 13; the test module 13 passes The interface conversion module 12 sends the corresponding identification of the target chip 131 to the computer.

In one implementation, when the test instructions are test instructions executed in parallel, the plurality of test modules 13 receive the test instructions executed in parallel in parallel, and pass the generated test results through the interface conversion module 12 Feedback to the computer; or, when the test instruction is a test instruction executed in a preset order, the plurality of test modules 13 receive the test instructions successively according to the preset order, and pass the generated test results through the The interface conversion module 12 is fed back to the computer.

In one implementation, the device further includes: a single-chip microcomputer module 11, the single-chip microcomputer module 11 is connected to the computer through the serial port 121, and receives the power-on instruction issued by the computer to the single-chip microcomputer module 11, according to The power-on command controls the multiple test modules 13 to be powered on.

In one implementation, the device further includes: a chip-mounting module 41, the chip-mounting module 41 is configured to, after the target test module 13 receives the test end instruction, , removing the target chip 131 on the target site module 13 , and installing the next target chip 131 to be tested on the target site module 13 .

The chip testing device in the embodiment of the present application may be a device, or a component in a terminal, an integrated circuit, or a chip. The device may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device can be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a vehicle electronic device, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant) , PDA), etc., the non-mobile electronic device can be a server, a network attached storage (NetworkAttached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., the embodiment of the present application Not specifically limited.

The chip testing device in the embodiment of the present application may be a device with an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in this embodiment of the present application.

The various processes and effects achieved by the chip testing device provided in the embodiments of the present application in the above embodiments have been described, and will not be repeated here to avoid repetition.

Based on the same technical idea, the embodiment of the present application also provides an electronic device, which is used to execute the above chip testing method. FIG. 5 is a schematic structural diagram of an electronic device implementing various embodiments of the present application. Electronic equipment may have relatively large differences due to different configurations or performances, and may include a processor (processor) 510, a communication interface (Communications Interface) 520, a memory (memory) 530, and a communication bus 540, wherein the processor 510, the communication interface 520 , the memories 530 communicate with each other through the communication bus 540 . The processor 510 can invoke a computer program stored on the memory 530 and operable on the processor 510. The method is applied to any of the chip testing devices described above to perform the following steps:

In one implementation, it includes: receiving the test instruction sent by the computer through the interface conversion module 12, sending the test instruction to the corresponding test module 13, executing the test instruction through the target chip installed on the test module 13 and generating the test instruction. As a result, the test result is fed back to the computer through the interface conversion module 12 through the test module 13 .

In an implementation manner, the test instruction includes: a test instruction automatically generated by a computer according to a preset chip test rule according to the target chips 131 installed on the plurality of test modules 13 .

For specific execution steps, reference may be made to the above-mentioned embodiments of the chip testing device, and the same technical effect can be achieved. To avoid repetition, details are not repeated here.

It should be noted that the electronic device in the embodiment of the present application includes: a server, a terminal or other devices except the terminal.

The above electronic device structure does not constitute a limitation to the electronic device, and the electronic device may include more or fewer components than shown in the illustration, or combine certain components, or arrange different components, for example, an input unit may include a graphics processor (Graphics Processing Unit, GPU) and a microphone, and the display unit may be configured with a display panel in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit includes at least one of a touch panel and other input devices. A touch panel is also called a touch screen. Other input devices may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, switch buttons, etc.), trackballs, mice, and joysticks, which will not be repeated here.

The memory can be used to store software programs as well as various data. The memory may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, application programs or instructions required by at least one function (such as sound playback function, image playback function, etc.) etc. Also, memory may include volatile memory or nonvolatile memory, or memory may include both volatile and nonvolatile memory. Wherein, the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electronically programmable Erase Programmable Read-Only Memory (Electrically EPROM, EEPROM) or Flash. Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synchlink DRAM, SLDRAM) and Direct Memory Bus Random Access Memory (Direct Rambus RAM, DRRAM).

The processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly handles operations related to the operating system, user interface, and application programs, and the modem The tone processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the foregoing modem processor may not be integrated into the processor.

The embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, each process of the above-mentioned chip testing method embodiment is realized, and the same To avoid repetition, the technical effects will not be repeated here.

Wherein, the processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

The embodiment of the present application further provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the above chip testing method embodiment Each process can achieve the same technical effect, so in order to avoid repetition, it will not be repeated here.

It should be understood that the chips mentioned in the embodiments of the present application may also be called system-on-chip, system-on-chip, system-on-a-chip, or system-on-a-chip.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved. Functions are performed, for example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, disk, CD) contains several instructions to enable a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in various embodiments of the present application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of this application, without departing from the purpose of this application and the scope of protection of the claims, many forms can also be made, all of which belong to the protection of this application.

Claims (10)

1. A chip testing apparatus, comprising:

a plurality of test modules, each of the test modules comprising: the test seat is used for installing a target chip to be tested, and the peripheral, the memory and the power supply control circuit are matched with the target chip;

the interface conversion module comprises a first interface which is in communication connection with the computer and a plurality of serial ports which correspond to the plurality of test modules, and each serial port is correspondingly connected with one test module;

the interface conversion module receives a test instruction sent by a computer in a state of being connected with the computer, the test instruction is sent to the test module, the test instruction is executed by the target chip installed on the test module, a test result is generated, and the test result is fed back to the computer through the interface conversion module.

2. The apparatus of claim 1, wherein the device comprises a plurality of sensors,

the test module receives an instruction which is sent by the computer through the serial port and used for acquiring the identification of the test module; and the test module sends the test module identification to the computer through the interface conversion module.

3. The apparatus of claim 1, wherein the device comprises a plurality of sensors,

the test module receives an instruction which is sent by the computer through the serial port corresponding to the test module and used for acquiring the target chip identification; and the test module sends the corresponding target chip identifier to the computer through the interface conversion module.

4. The apparatus of claim 1, wherein the device comprises a plurality of sensors,

when the test instruction is a parallel execution test instruction, the plurality of test modules receive the parallel execution test instruction in parallel and feed back a generated test result to the computer through the interface conversion module;

or,

when the test instruction is executed according to a preset sequence, the plurality of test modules sequentially receive the test instruction according to the preset sequence, and the generated test result is fed back to the computer through the interface conversion module.

5. The apparatus of claim 1, wherein the apparatus further comprises: a singlechip module, wherein the singlechip module is provided with a plurality of control circuits,

the single chip microcomputer module is connected with the computer through the serial port, receives a power-on instruction issued by the computer to the single chip microcomputer module, and controls the plurality of test modules to be powered on according to the power-on instruction.

6. The apparatus of claim 1, wherein the apparatus further comprises: the chip is carried out and is provided with a module,

and the chip executing module is used for removing the target chip on the target test module according to the test ending instruction after the target test module receives the test ending instruction, and installing the next target chip to be tested on the target test module.

7. A chip testing method applied to the chip testing device according to any one of claims 1 to 6, comprising:

receiving a test instruction sent by a computer through an interface conversion module, and sending the test instruction to a corresponding test module;

executing the test instruction through a target chip installed on the test module and generating a test result;

and feeding the test result back to the computer through the interface conversion module by the test module.

8. The method of claim 7, wherein the test instruction comprises:

and the computer automatically generates a test instruction according to a preset chip test rule according to the target chips installed on the plurality of test modules.

9. An electronic device, the device comprising:

A processor; and

a memory arranged to store computer executable instructions configured to be executed by the processor, the executable instructions comprising instructions for performing the method of any of claims 7-8.

10. A storage medium storing computer-executable instructions for causing a computer to perform the method of any one of claims 7-8.

Images