CN116246668B

CN116246668B - Data processing circuit, data processing method and memory

Info

Publication number: CN116246668B
Application number: CN202310248373.XA
Authority: CN
Inventors: 马鹏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-03-10
Filing date: 2023-03-10
Publication date: 2025-10-03
Anticipated expiration: 2043-03-10
Also published as: CN116246668A

Abstract

The embodiment of the disclosure provides a data processing circuit, a data processing method and a memory, wherein the data processing circuit comprises a preprocessing module, a driving module and at least one second target data signal, the preprocessing module is used for sampling a first data signal according to a clock signal to obtain a first intermediate data signal, the sampling module is used for sampling at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, the at least one second data signal is obtained by carrying out shift processing on the first data signal, the driving module is used for carrying out driving processing on the first intermediate data signal to generate a first target data signal, the driving processing is carried out on the at least one second intermediate data signal to generate at least one second target data signal, and the at least one second target data signal is used for compensating the first target data signal to form the target data signal. The embodiment of the disclosure can ensure the accuracy of the data signal and improve the high-speed performance of the memory.

Description

Data processing circuit, data processing method and memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a data processing circuit, a data processing method, and a memory.

Background

With the continuous development of semiconductor technology, higher and higher requirements are being placed on the data transmission speed when manufacturing and using devices such as computers. In order to obtain a faster Data transmission speed, a series of devices such as a memory capable of transmitting Data at Double Data Rate (DDR), for example, a DDR4 chip and a DDR5 chip, have been developed.

Compared to DDR4 chips, the highest data speed of DDR5 chips is increased from 3200 megabits per second (Mbps) to 6400Mbps. However, during transmission of high-speed signals, inter-symbol interference (Inter Symbol Interference, ISI) is very likely to occur, resulting in signal distortion.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a data processing circuit, including a preprocessing module and a driving module, where an output end of the preprocessing module is connected to an input end of the driving module, where:

The preprocessing module is used for receiving a first data signal and at least one second data signal, sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, wherein the at least one second data signal is obtained by performing shift processing on the first data signal;

The driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, driving the first intermediate data signal to generate a first target data signal, driving the at least one second intermediate data signal to generate at least one second target data signal, and driving the at least one second intermediate data signal to generate a second target data signal;

The first data signal and the second data signal are parallel data signals, the first intermediate data signal and the second intermediate data signal are serial data signals, and the at least one second target data signal is used for compensating the first target data signal to form a target data signal.

In some embodiments, the preprocessing module includes a first data selection module and at least one second data selection module, and the at least one second data selection module and the at least one second data signal are in one-to-one correspondence, the first data signal and the second data signal each include M parallel sub-data, the clock signal includes M clock sub-signals, wherein:

The first data selection module is configured to receive M clock sub-signals and M sub-data in the first data signal, and sample the M sub-data in the first data signal according to the M clock sub-signals, so as to generate the first intermediate data signal;

the second data selection module is configured to receive M clock sub-signals and M sub-data in the corresponding second data signals, and sample the M sub-data in the second data signals according to the M clock sub-signals, so as to generate the corresponding second intermediate data signals;

wherein, M clock sub-signals and M sub-data are in one-to-one correspondence.

In some embodiments, the data selection module comprises a clock generation module, M D flip-flops, M switch units, and one D flip-flop and one switch unit are connected in series, wherein the data selection module represents any one of the first data selection module and at least one second data selection module, wherein:

the clock generation module is used for receiving M clock sub-signals, generating M target clock sub-signals according to the M clock sub-signals, wherein the target clock sub-signals are frequency multiplication signals of the clock sub-signals;

The y-th D trigger is used for receiving the y-th sub-data and the y-th clock sub-signal, and sampling the y-th sub-data according to the y-th clock sub-signal to obtain y-th sampling sub-data;

The y-th switching unit is used for receiving the y-th target clock sub-signal and the y-th sampling sub-data, and outputting the y-th sampling sub-data as y-th intermediate sub-data under the condition that the y-th target clock sub-signal is in an effective state;

Wherein y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constituting an intermediate data signal, the intermediate data signal representing any one of the first data signal and the at least one second data signal.

In some embodiments, the drive module comprises a pull-up drive module and a pull-down drive module, wherein:

The pull-up driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, driving the first intermediate data signal to generate a first pull-up target data signal, driving the at least one second intermediate data signal to generate at least one second pull-up target data signal, and driving the at least one second intermediate data signal to generate a second pull-up target data signal;

the pull-down driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, driving the first intermediate data signal to generate a first pull-down target data signal, driving the at least one second intermediate data signal to generate at least one second pull-down target data signal, and driving the at least one second intermediate data signal to generate a second pull-down target data signal;

wherein the first target data signal comprises the first pull-up target data signal and/or the first pull-down target data signal, and the at least one second target data signal comprises the at least one second pull-up target data signal and/or the at least one second pull-down target data signal.

In some embodiments, the pull-up driving module includes a pull-up driving main module and a pull-up driving compensation module, the pull-up driving compensation module includes at least one pull-up compensation sub-module, the at least one pull-up compensation sub-module and the at least one second intermediate data signal correspond one-to-one, wherein:

the pull-up driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-up target data signal;

the pull-up compensation sub-module is used for receiving the corresponding second intermediate data signal, driving the second intermediate data signal and generating the corresponding second pull-up target data signal;

The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation sub-module.

In some embodiments, the pull-down driving module includes a pull-down driving main module and a pull-down driving compensation module, the pull-down driving compensation module includes at least one pull-down compensation sub-module, the at least one pull-down compensation sub-module and the at least one second intermediate data signal correspond one-to-one, wherein:

the pull-down driving main module is configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate the first pull-down target data signal;

The pull-down compensation sub-module is used for receiving the corresponding second intermediate data signal, driving the second intermediate data signal and generating the corresponding second pull-down target data signal;

The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation sub-module.

In some embodiments, the pull-up compensation submodule includes a pre-drive module and a first main drive module, wherein:

The pre-driving module is used for receiving the corresponding second intermediate data signals, performing pre-driving processing on the second intermediate data signals and generating corresponding second intermediate driving signals;

The first main driving module is configured to receive the corresponding second intermediate driving signal, and perform compensation driving processing on the second intermediate driving signal to obtain the corresponding second pull-up target data signal.

In some embodiments, the pre-drive module and the first main drive module are connected, wherein:

the pre-driving module is further configured to receive a pull-up compensation control signal, and determine a compensation coefficient of the first main driving module according to the pull-up compensation control signal.

In some embodiments, the first main driving module includes a pull-up driving unit and a multiplier, wherein:

the pull-up driving unit is used for driving the second intermediate driving signal to obtain a pull-up driving signal;

The multiplier is used for performing compensation processing on the pull-up driving signal to obtain the second pull-up target data signal;

The multiplier is used for controlling the compensation coefficient of the first main driving module.

In some embodiments, the pull-down compensation submodule includes a pre-drive module and a second main drive module, wherein:

the second main driving module is configured to receive the corresponding second intermediate driving signal, and perform compensation driving processing on the second intermediate driving signal to obtain the corresponding second pull-down target data signal.

In some embodiments, the pre-drive module and the second main drive module are connected, wherein:

The pre-driving module is further configured to receive a pull-down compensation control signal, and determine a compensation coefficient of the second main driving module according to the pull-down compensation control signal.

In some embodiments, the second main driving module includes a pull-down driving unit and a multiplier, wherein:

The pull-down driving unit is used for driving the second intermediate driving signal to obtain a pull-down driving signal;

The multiplier is used for performing compensation processing on the pull-down driving signal to obtain the second pull-down target data signal;

The multiplier is used for controlling the compensation coefficient of the second main driving module.

In some embodiments, the data processing circuit further comprises a shift register module, wherein:

The shift register module is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain the at least one second data signal.

In some embodiments, the shift register module includes at least one shift register, the at least one shift register and the at least one second data signal each being N in number, N being an integer greater than 0, wherein:

when N is equal to 1, the shift register is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain the second data signal;

When N is greater than 1, the 1 st shift register is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain a1 st second data signal;

And the ith shift register is used for receiving the ith-1 second data signal and the clock signal, and carrying out shift processing on the ith-1 second data signal according to the clock signal to obtain the ith second data signal, wherein i is an integer which is more than 1 and less than or equal to N.

In a second aspect, an embodiment of the present disclosure provides a data processing method, including:

Sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, wherein the at least one second data signal is obtained by performing shift processing on the first data signal;

The driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, driving the first intermediate data signal to generate a first target data signal, driving the at least one second intermediate data signal to generate at least one second target data signal, and driving the at least one second target data signal to generate a second target data signal;

In a third aspect, embodiments of the present disclosure provide a memory comprising the data processing circuit of any one of the first aspects.

The embodiment of the disclosure provides a data processing circuit, a data processing method and a memory, wherein the data processing circuit comprises a preprocessing module and a driving module, the output end of the preprocessing module is connected with the input end of the driving module, the preprocessing module is used for receiving a first data signal and at least one second data signal, the first data signal is sampled according to a clock signal to obtain a first intermediate data signal, the at least one second data signal is sampled according to the clock signal to obtain at least one second intermediate data signal, the at least one second data signal is obtained by carrying out shift processing on the first data signal, the driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, the driving module is used for carrying out driving processing on the first intermediate data signal to generate a first target data signal and carrying out driving processing on the at least one second intermediate data signal to generate at least one second target data signal, the first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are serial data signals, and the first target data signal and the second target data signal are used for compensating the first target data signal. Thus, through predistortion processing of the signals, the accuracy of the signals received by the controller after the signals are transmitted through the channel is ensured, the distortion of the signals is improved, and the high-speed performance of the memory is improved.

Drawings

FIG. 1 is a schematic diagram of a data processing circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a second embodiment of a data processing circuit according to the present disclosure;

fig. 3A is a schematic diagram of a composition structure of a data selection module according to an embodiment of the disclosure;

Fig. 3B is a schematic diagram of a second component structure of a data selection module according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a signal timing diagram according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram of a third embodiment of a data processing circuit according to the present disclosure;

fig. 6 is a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the disclosure;

fig. 7 is a schematic diagram of a composition structure of a pull-up driving module according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a composition structure of a pull-down driving module according to an embodiment of the disclosure;

Fig. 9 is a schematic diagram of a second component structure of a pull-up driving module according to an embodiment of the disclosure;

Fig. 10 is a schematic diagram of a composition structure of a pull-up compensation sub-module according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a second component structure of a pull-up compensation sub-module according to an embodiment of the present disclosure;

fig. 12 is a schematic diagram of a second component structure of a pull-down driving module according to an embodiment of the disclosure;

FIG. 13 is a schematic diagram of a pull-down compensation sub-module according to an embodiment of the present disclosure;

fig. 14 is a schematic diagram of a second component structure of a pull-down compensation sub-module according to an embodiment of the present disclosure;

Fig. 15 is a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the present disclosure;

FIG. 16 is a schematic diagram showing a data processing circuit according to an embodiment of the present disclosure;

FIG. 17 is a second signal timing diagram according to an embodiment of the disclosure;

FIG. 18 is a third signal timing diagram according to an embodiment of the present disclosure;

FIG. 19 is a flowchart of a data processing method according to an embodiment of the present disclosure;

FIG. 20 is a schematic diagram of a memory according to an embodiment of the disclosure;

fig. 21 is a schematic diagram of a composition structure of a storage system according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the related disclosure and not limiting thereof. It should be further noted that, for convenience of description, only the portions related to the disclosure are shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

For dynamic random access memory (Dynamic Random Access Memory, DRAM), compared with DDR4, the data speed of DDR5 is increased from 3200Mbps to 6400Mbps, and the interface of DDR5 (including the transmitting end TX and the receiving end RX) can reach high speed, which is half the internal operating speed of DDR 5. When the transmitting end transmits a high-speed signal to the DRAM controller through a channel, ISI may occur, resulting in signal distortion, affecting performance.

Based on the data, the embodiment of the disclosure provides a data processing circuit, which comprises a preprocessing module and a driving module, wherein the output end of the preprocessing module is connected with the input end of the driving module, the preprocessing module is used for receiving a first data signal and at least one second data signal, sampling the first data signal according to a clock signal to obtain a first intermediate data signal, sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, the at least one second data signal is obtained by carrying out shift processing on the first data signal, the driving module is used for receiving the first intermediate data signal and the at least one second intermediate data signal, carrying out driving processing on the first intermediate data signal to generate a first target data signal, and carrying out driving processing on the at least one second intermediate data signal to generate at least one second target data signal, wherein the first data signal and the second data signal are parallel data signals, the first intermediate data signal and the second intermediate data signal are serial data signals, and the at least one second target data signal is used for compensating the first target data signal.

In this way, the first data signal to be transmitted is shifted to obtain at least one second data signal, and then the first data signal and the at least one second data signal are respectively driven to obtain a first target data signal and at least one second target data signal, and the first target data signal is compensated by the at least one second target data signal to form a target data signal. Therefore, predistortion processing of signals is realized, accuracy of signals received by the controller after the signals are transmitted through the channel is guaranteed, and high-speed performance of the memory is further improved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, referring to fig. 1, a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the present disclosure is shown. As shown in fig. 1, the data processing circuit 10 includes a preprocessing module 11 and a driving module 12, and an output terminal of the preprocessing module 11 is connected to an input terminal of the driving module 12, wherein:

the preprocessing module 11 is configured to receive a first data signal and at least one second data signal, sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, where the at least one second data signal is obtained by performing shift processing on the first data signal;

a driving module 12 for receiving the first intermediate data signal and the at least one second intermediate data signal, performing driving processing on the first intermediate data signal to generate a first target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

The first data signal and the second data signal are parallel data signals, the first intermediate data signal and the second intermediate data signal are serial data signals, and at least one second target data signal is used for compensating the first target data signal to form a target data signal.

It should be noted that, the data processing circuit 10 may be located at a transmitting end of the DRAM, and is configured to perform predistortion processing on a data signal, so as to ensure that distortion generated by channel transmission can be "offset" in a process of transmitting the data signal in a channel, and further, when the signal arrives at the DRAM controller, the influence of ISI on the signal is improved, distortion of the data signal is reduced, and performance is improved.

It should also be noted that in the embodiments of the present disclosure, the first data signal is a transmitted data signal. Taking the number of second data signals as N (N is an integer greater than 0) as an example, as shown in fig. 1, the N second data signals include a second data signal 1, a second data signal 2, a second data signal N. The N second data signals are obtained by shifting the first data signals. More specifically, the first data signal is shifted to obtain a second data signal 1, the second data signal 1 is shifted to obtain a second data signal 2.

The preprocessing module 11 samples the first data signal and the at least one second data signal according to the clock signal, respectively, to obtain a first intermediate data signal and at least one second intermediate data signal, respectively. As shown in fig. 1, the number of second intermediate data signals is also N, corresponding to N second data signals, where the second data signal 1 is sampled to obtain a second intermediate data signal 1, the second data signal 2 is sampled to obtain a second intermediate data signal 2, # the second data signal N is sampled to obtain a second intermediate data signal N.

The first data signal may be a parallel data signal, and at least one second data signal obtained by performing shift processing on the first data signal is also a parallel data signal. Correspondingly, sampling the data signals may mean that each data in the parallel data signals is sampled with a clock signal to be sequentially output in time sequence, thereby realizing conversion of the parallel data signals into serial data signals. The serial data signal can be transmitted at a higher rate than the parallel data signal. It is understood that the sampled first intermediate data signal and the at least one second intermediate data signal may each be a serial data signal.

The output end of the preprocessing module 11 is connected with the input end of the driving module 12, the preprocessing module 11 sends the first intermediate data signal and at least one second intermediate data signal to the driving module 12, and the driving module 12 respectively carries out driving processing on the first intermediate data signal and the at least one second intermediate data signal to respectively obtain a first target data signal and at least one second target data signal. The number of the second target data signals is also N corresponding to the N second intermediate data signals, wherein the second intermediate data signals 1 are subjected to driving processing to obtain second target data signals 1, the second intermediate data signals 2 are subjected to driving processing to obtain second target data signals 2, & gt.

It should be further noted that the N second target data signals are used for performing compensation processing on the first target data signal, and the first target data signal and the N second target data signals are combined to form the target data signal. I.e. the voltage value of the target data signal is a superposition of the voltage values of the first target data signal and the N second target data signals. As shown in fig. 1, the driving module 12 outputs a target data signal composed of a first target data signal and N second target data.

That is, the present embodiment adds a compensation process (or predistortion process) to the transmitted data signal to compensate for distortion of the signal when transmitting in the channel. If compensation processing is not added, only the first data signal is sampled to obtain a first intermediate data signal, and driving processing is carried out on the first intermediate data signal to obtain a first target data signal serving as a target data signal, and the first target data signal is sent to the controller through a channel, wherein in the case, ISI exists to cause distortion of the target data signal received by the controller. According to the method, on the basis of processing the first data signal to obtain the first target data signal, at least one second data signal obtained by shifting the first data signal is processed to obtain at least one second target data signal, compensation processing is performed on the first target data signal by using the at least one second target data signal to obtain the target data signal, and pre-distortion processing of the signal before entering a channel is achieved, so that the influence of inter-code crosstalk can be reduced, and the reliability of the signal reaching a controller after being transmitted through the channel is guaranteed.

When the driving process is performed on the N second intermediate data signals, the corresponding compensation coefficients may be set, so that the voltage value of the second target data signal is the product of the voltage value/logic voltage value of the corresponding second intermediate data signal and the corresponding compensation coefficient. Here, a specific value of the compensation coefficient may be set in connection with a specific channel environment, which is not particularly limited.

Referring to fig. 2, a schematic diagram of a second component structure of a data processing circuit according to an embodiment of the disclosure is shown. As shown in fig. 2, in some embodiments, the preprocessing module 11 includes a first data selection module 111 and at least one second data selection module 112, and the at least one second data selection module 112 and the at least one second data signal are in one-to-one correspondence, the first data signal and the second data signal each include M parallel sub-data, and the clock signal includes M clock sub-signals, wherein:

the first data selecting module 111 is configured to receive M clock sub-signals and M sub-data in the first data signal, and sample the M sub-data in the first data signal according to the M clock sub-signals, so as to generate a first intermediate data signal;

The second data selecting module 112 is configured to receive M clock sub-signals and M sub-data in the corresponding second data signals, and sample the M sub-data in the second data signals according to the M clock sub-signals, so as to generate corresponding second intermediate data signals;

Wherein, M clock sub-signals and M sub-data are in one-to-one correspondence.

It should be noted that the first data selecting module 111 and the second data selecting module 112 may have the same structure to implement parallel-to-serial processing of the data signal, and for convenience of description, the first data selecting module 111 or any one of the second data selecting modules 112 may be referred to as the data selecting module 113. Taking the first data selection module 111 as an example, as shown in fig. 2, the signals received by the first data selection module 111 are a first data signal and a clock signal, that is, M parallel sub-data and M clock sub-signals are received, where a time delay exists between the M clock sub-signals in sequence.

Next, the operation of the data selection module 113 will be briefly described. Referring to fig. 3A, a schematic diagram of a composition structure of a data selection module according to an embodiment of the disclosure is shown. As shown in fig. 3A, in some embodiments, the data selection module 113 may include a clock generation module 1131, M D flip-flops (DFF 1, DFF2,) M switching units (S1, S2,) and one D flip-flop and one switching unit are connected in series, wherein:

the clock generation module 1131 is configured to receive M clock sub-signals, generate M target clock sub-signals according to the M clock sub-signals, where the target clock sub-signals are frequency-multiplied signals of the clock sub-signals;

the y D trigger is used for receiving the y sub-data and the y clock sub-signal, and sampling the y sub-data according to the y clock sub-signal to obtain y sampling sub-data;

The y-th switch unit is used for receiving the y-th target clock sub-signal and the y-th sampling sub-data, and outputting the y-th sampling sub-data into the y-th intermediate sub-data under the condition that the y-th target clock sub-signal is in an effective state;

It should be noted that, the "valid state" may be a logic 1 at a high level or a logic 0 at a low level, and in the embodiment of the present disclosure, the "valid state" may be a logic 1 at a high level is described as an example.

Further, the data selecting module 131 may further include a data enhancing module 1132, as shown in fig. 3A, and the data enhancing module 1132 may include an even number of inverters (NOT, 2 are shown in fig. 3A) for enhancing the intermediate data signal.

Taking M equal to 4 as an example, the data selection module may include a one-out-of-four data selector (4-1 MUX). Referring to fig. 3B, which shows a second schematic diagram of the composition structure of a data selection module provided by an embodiment of the present disclosure, as shown in fig. 3B, the data selection module 113 may include a clock generation module 1131, four D flip-flops including DFF1, DFF2, DFF3 and DFF4, and four switch units including S1, S2, S3 and S4, wherein:

The clock generation module is configured to receive the first clock Zhong Zi signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK and the fourth clock sub-signal QBCLK and generate a first target clock sub-signal iclk_n, a second target clock sub-signal qclk_n, a third target clock sub-signal ibclk_n and a fourth target clock sub-signal QBCLK _n.

Fig. 4 shows a corresponding signal timing diagram. As shown in conjunction with fig. 3B and 4, the clock signal includes four clock sub-signals, a first clock Zhong Zi signal ICLK, a second clock sub-signal QCLK, a third clock sub-signal IBCLK, and a fourth clock sub-signal QBCLK, which may have a time delay in sequence, and the four clock sub-signals may have phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees in sequence, and the first Data signal includes four sub-Data, a first sub-Data data_0 (including Data D0 and Data D4), a second sub-Data data_1 (including Data D1 and Data D5), a third sub-Data data_2 (including Data D2 and Data D6), and a fourth sub-Data data_3 (including Data D3 and Data D7).

The clock generation module 1131 may generate a first target clock sub-signal iclk_n, a second target clock sub-signal qclk_n, a third target clock sub-signal ibclk_n, and a fourth target clock sub-signal QBCLK _n, which are combined to be referred to as target clock signals, from the first clock Zhong Zi signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK, and the fourth clock sub-signal QBCLK. As shown in fig. 4, the high level pulse of each clock sub-signal has a width H1, and the high level pulse of each target clock sub-signal has a width H2. The clock generation module generates the first target clock sub-signal iclk_n according to the rising edge of the first clock Zhong Zi signal ICLK, the clock generation module generates the second target clock sub-signal qclk_n according to the rising edge of the second clock sub-signal QCLK, the clock generation module generates the third target clock sub-signal ibclk_n according to the rising edge of the third clock sub-signal IBCLK, and the clock generation module generates the fourth target clock sub-signal QBCLK _n according to the rising edge of the fourth clock Zhong Zi signal QBCLK. The pulse width of the target clock sub-signal is smaller than the pulse width of the corresponding clock sub-signal. The clock generation module 1131 may be implemented by a clock signal generator, among other things.

The Data selecting module 113 performs a sampling latch process on the first sub Data data_0 at a rising edge of the first clock sub signal ICLK, specifically, samples and latches the Data D0 at a first rising edge and samples and latches the Data D4 at a next rising edge shown in fig. 4, outputs the sampled Data D0 during a first high level pulse of the first target clock sub signal iclk_n, and outputs the sampled Data D4 during a next high level pulse. Taking the circuit structure shown in fig. 3B as an example, the DDF1 performs sampling and latching processing on D0 at the rising edge of the first clock sub-signal ICLK, and turns on the switch unit S1 when the first target clock sub-signal iclk_n is in the high level state, and none of the other switch units is turned on, so as to output the sampled data during the high level pulse of the first target clock sub-signal iclk_n, and further, the signal may be enhanced and/or delayed by two NOT gates NOT.

The same processing manner is also adopted for the rest clock sub-signals and the corresponding sub-data, and the detailed description is omitted here.

Thus, the parallel first data signal and the parallel second data signal are converted into a serial first intermediate data signal and a serial second intermediate data signal, respectively, through the processing of the first data selection module 111 and the second data selection module 112.

Referring to fig. 5, a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the disclosure is shown. As shown in fig. 5, in one specific implementation, the at least one second Data selection module includes a first Data selection sub-module MUX-1, a second Data selection sub-module MUX-2, a third Data selection sub-module MUX-3, and a fourth Data selection sub-module MUX-4, and the at least one second Data signal includes a first sub-Data signal data_z1<3:0>, a second sub-Data signal data_z2<3:0>, a third sub-Data signal data_z3<3:0>, and a fourth sub-Data signal data_z4<3:0>, wherein:

the first Data selecting sub-module MUX-1 is used for receiving M clock sub-signals and M sub-Data in the first sub-Data signals data_Z1<3:0>, and respectively carrying out sampling processing on the M sub-Data in the first sub-Data signals according to the M clock sub-signals to generate serial first intermediate sub-Data signals;

The second Data selecting sub-module MUX-2 is used for receiving M clock sub-signals and M sub-Data in the second sub-Data signals data_Z2<3:0>, and respectively carrying out sampling processing on the M sub-Data in the second sub-Data signals according to the M clock sub-signals to generate a serial second intermediate sub-Data signal;

The third Data selecting sub-module MUX-3 is used for receiving M clock sub-signals and M sub-Data in the third sub-Data signal data_Z3<3:0>, and respectively carrying out sampling processing on the M sub-Data in the third sub-Data signal according to the M clock sub-signals to generate a serial third intermediate sub-Data signal;

A fourth Data selecting sub-module MUX-4, configured to receive M clock sub-signals and M sub-Data in the fourth sub-Data signal data_z4<3:0>, and sample the M sub-Data in the fourth sub-Data signal according to the M clock sub-signals, so as to generate a serial fourth intermediate sub-Data signal;

Wherein the at least one second intermediate data signal comprises a first intermediate sub data signal mid_z1, a second intermediate sub data signal mid_z2, a third intermediate sub data signal mid_z3 and a fourth intermediate sub data signal mid_z4.

It should be noted that, as shown in fig. 5, the Main-MUX represents the first data processing module. Taking the data signal to be transmitted as a data sequence of 8-bit sub-data, the 8-bit sub-data are respectively data <0>, data <1>, data <2>, data <3>, data <4>, data <5>, data <6> and data <7>, and are collectively denoted as data <7:0>, taking the data selection module as an example comprising a 4-1MUX, where M is equal to 4, i.e. the first data signal and the second data signal each comprise 4 sub-data. Wherein, the first Data signal data_z1<3:0> is Data <3:0>, the first sub Data signal data_z1<3:0> is Data <4:1>, the second sub Data signal data_z2<3:0> is Data <5:2>, the third sub Data signal data_z3<3:0> is Data <6:3>, and the fourth sub Data signal data_z4<3:0> is Data <7:4>, for each second Data signal.

The operation of each data selecting sub-module may be understood with reference to fig. 3B and the related description, and will not be repeated here.

It should also be noted that this embodiment is used for predistortion/predistortion processing of a transmitted data signal prior to channel transmission, and thus the entire data processing circuit may also be referred to as a feed-forward equalization (Feed Forward Equalization, FFE) circuit or FFE architecture. The conventional FFE architecture is generally implemented by a digital circuit, the main driving circuit adopts a differential structure, the output of the DRAM adopts a single-ended structure, so that the FFE architecture of the DRAM needs to consider the predistortion effect on signals and the requirement of DRAM standards on output impedance, in order to meet the requirement, the transmitting end of the FFE is divided into a FFE module (i.e. a preprocessing module 11) and an output driving module (i.e. a driving module 12), in the specific implementation shown in fig. 5, the FFE module of the DRAM consists of 5 muxes selected from four, and 4-bit signals fed into the 5 muxes are low-speed signals with sequential delay.

For the drive module 12, in some embodiments, as shown in fig. 2, the drive module 12 includes a pull-up drive module 121 and a pull-down drive module 122, wherein:

A pull-up driving module 121 for receiving the first intermediate data signal and at least one second intermediate data signal, driving the first intermediate data signal to generate a first pull-up target data signal, and driving the at least one second intermediate data signal to generate at least one second pull-up target data signal;

A pull-down driving module 122 for receiving the first intermediate data signal and at least one second intermediate data signal, driving the first intermediate data signal to generate a first pull-down target data signal, and driving the at least one second intermediate data signal to generate at least one second pull-down target data signal;

wherein the first target data signal comprises a first pull-up target data signal and/or a first pull-down target data signal and the at least one second target data signal comprises at least one second pull-up target data signal and/or at least one second pull-down target data signal.

It should be noted that, since the DRAM adopts a single-ended output structure, it becomes particularly important to control the impedance of the driving module of the DRAM. Accordingly, the driving module 12 of the DRAM is divided into two parts, namely, a Pull-Up driving module 121 (Pull Up) and a Pull-Down driving module 122 (Pull Down). The pull-up driving module 121 is configured to perform pull-up processing on the received signal, and the pull-down driving module 122 is configured to perform pull-down processing on the received signal.

In the implementation shown in fig. 2, the inputs of the pull-up driving module 121 and the pull-down driving module 122 are both connected to the output of the preprocessing module 11, and the preprocessing module 11 provides the first intermediate data signal and the at least one second intermediate data signal to the pull-up driving module 121 and the pull-down driving module 122 at the same time. In another implementation, referring to fig. 6, a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the disclosure is shown. As shown in fig. 6, the data processing circuit 10 may include two preprocessing modules, namely a pull-up preprocessing module 11A and a pull-down preprocessing module 11B, where the pull-up preprocessing module 11A and the pull-down preprocessing module 11B have the same structure and function as the preprocessing module 11 shown in fig. 2, an output end of the pull-up preprocessing module 11A is connected with an input end of the pull-up driving module 121 to provide a first intermediate data signal and at least one second intermediate data signal to the pull-up driving module 121, and an output end of the pull-down preprocessing module 11B is connected with an input end of the pull-down driving module 122 to provide the first intermediate data signal and the at least one second intermediate data signal to the pull-down driving module 122. The implementation of the preprocessing module is not particularly limited herein.

It should be noted that, according to the level state of the received signal, one of the pull-up driving module 121 and the pull-down driving module 122 is in an operating state to implement a pull-up driving process or a pull-down driving process on the signal. Here, the example in which the pull-up driving module 121 is in the operating state and the pull-down driving module 122 is not operated when the signal is in the first level state, and the pull-up driving module 121 is not operated and the pull-down driving module 122 is in the operating state when the signal is in the second level state is described. The first level state may represent a logic 1 of a high level, the second level state may represent a logic 0 of a low level, or the first level state may represent a logic 0 of a low level, the second level state may represent a logic 1 of a high level, etc., which are specifically set in connection with the circuit structure, and are not specifically limited herein.

For the first intermediate data signal, when the pull-up driving module 121 operates, the pull-up driving module 121 performs pull-up driving processing on the first intermediate data signal to obtain a first pull-up target data signal, and when the pull-down driving module 122 operates, the pull-down driving module 122 performs pull-down driving processing on the first intermediate data signal to obtain a first pull-down target data signal. That is, at a certain data point, the first target data signal is a first pull-up target data signal or a first pull-down target data signal, such that the first pull-up target data signal and the first pull-down target data signal constitute the first target data signal, i.e., the first target data signal includes the first pull-up target data signal and/or the first pull-down target data signal.

For any one of the second intermediate data signals, when the pull-up driving module 121 works, the pull-up driving module 121 performs pull-up driving processing on the second intermediate data signal according to the corresponding compensation coefficient, so as to obtain a second pull-up target data signal. When the pull-down driving module 122 works, the pull-down driving module 122 performs pull-down driving processing on the second intermediate data signal according to the corresponding compensation coefficient, so as to obtain a second pull-down target data signal. So that the voltage value (logic voltage value) of the second pull-up target data signal is the product of the voltage value (logic voltage value) of the second intermediate data signal and the corresponding compensation coefficient.

Here, it should be noted that, since the driving module 12 is divided into the pull-up driving module 121 and the pull-down driving module 122, corresponding compensation coefficients are respectively set in the pull-up driving module 121 and the pull-down driving module 122 for the N second intermediate signals. For example, the N second intermediate data signals have corresponding N compensation coefficients in the pull-up driving module 121 of pull-up compensation coefficient 1, pull-up compensation coefficient 2, and pull-up compensation coefficient N, respectively; the N compensation coefficients corresponding to the N second intermediate data signals in the pull-down driving module 122 are respectively a pull-down compensation coefficient 1, a pull-down compensation coefficient 2, and a pull-down compensation coefficient N. The values of the compensation coefficients may be the same or different, and may be positive or negative. In addition, the pull-up compensation coefficient i and the pull-down compensation coefficient i may be the same value or different values, where i is an integer greater than or equal to 1 and less than or equal to N.

Similar to the first target data signal, at a certain data point, the second target data signal is either a second pull-up target data signal or a second pull-down target data signal, such that the second pull-up target data signal and the second pull-down target data signal constitute the second target data signal, i.e. the second target data signal comprises the second pull-up target data signal and/or the second pull-down target data signal.

In addition, for convenience of description, in fig. 2, the first pull-up target data signal and the N second pull-up target data signals are collectively referred to as pull-up target data signals, and the first pull-down target data signal and the N second pull-down target data signals are collectively referred to as pull-down target data signals.

Further, referring to fig. 7, a schematic diagram of a composition structure of a pull-up driving module according to an embodiment of the disclosure is shown. As shown in fig. 7, in some embodiments, the pull-up driving module 121 includes a pull-up driving main module 1211 and a pull-up driving compensation module 1212, wherein:

A pull-up driving main module 1211, configured to receive the first intermediate data signal, perform driving processing on the first intermediate data signal, and generate a first pull-up target data signal;

the pull-up driving compensation module 1212 is configured to receive at least one second intermediate data signal, perform driving processing on the at least one second intermediate data signal, and generate at least one second pull-up target data signal.

It should be noted that, the pull-up driving main module 1211 is a module for performing pull-up processing on the data signal by default in the DRAM, and the pull-up driving compensation module 1212 is a compensation module added in this embodiment to implement predistortion on the signal, and the pull-up driving compensation module 1212 may also be referred to as a pull-up FFE module or FFE output driver (pull-up).

The pull-up driving compensation module 1212 is configured to increase or decrease the voltage of the output signal by increasing or decreasing a portion of the small current based on the original default output current, thereby implementing predistortion processing on the signal and ensuring the reliability of the signal transmitted through the channel.

As shown in fig. 7, in some embodiments, the pull-up drive compensation module 1212 includes at least one pull-up compensation sub-module, the at least one pull-up compensation sub-module and the at least one second intermediate data signal being in one-to-one correspondence, wherein:

The pull-up compensation sub-module is used for receiving a corresponding second intermediate data signal, driving the second intermediate data signal and generating a corresponding second pull-up target data signal;

As shown in fig. 7, the pull-up driving compensation module 1212 includes N pull-up compensation sub-modules corresponding to N second intermediate data signals, i.e., a pull-up compensation sub-module 1, a pull-up compensation sub-module 2, and a pull-up compensation sub-module N. Each pull-up compensation sub-module is provided with a respective compensation coefficient to realize driving processing of the received second intermediate data signal according to the compensation coefficient.

The pull-up compensation sub-module 1 performs driving processing on the second intermediate data signal 1, and the obtained voltage value of the second pull-up target data signal 1 is the product of the voltage value of the second intermediate data signal 1 and the compensation coefficient of the pull-up compensation sub-module 1.

Similar to the composition of the pull-up driving module 121, referring to fig. 8, a schematic diagram of the composition of a pull-down driving module according to an embodiment of the present disclosure is shown. As shown in fig. 8, in some embodiments, the pull-down drive module 122 includes a pull-down drive master module 1221 and a pull-down drive compensation module 1222, wherein:

A pull-down driving main module 1221 for receiving the first intermediate data signal, performing driving processing on the first intermediate data signal, and generating a first pull-down target data signal;

The pull-down driving compensation module 1222 is configured to receive at least one second intermediate data signal, perform driving processing on the at least one second intermediate data signal, and generate at least one second pull-down target data signal.

It should be noted that, the pull-down driving main module 1221 is a module for performing pull-down processing on the data signal by default in the DRAM, and the pull-down driving compensation module 1222 is a compensation module added in this embodiment to implement predistortion on the signal, and the pull-down driving compensation module 1222 may also be referred to as a pull-down FFE module or FFE output driver (pull-up).

The pull-down driving compensation module 1222 has the function of increasing or decreasing the voltage of the output signal by increasing or decreasing a part of small current based on the original default output current, thereby realizing the predistortion processing of the signal and ensuring the reliability of the signal transmitted through the channel.

As shown in fig. 8, in some embodiments, the pull-down drive compensation module 1222 includes at least one pull-down compensation sub-module, the at least one pull-down compensation sub-module and the at least one second intermediate data signal being in one-to-one correspondence, wherein:

The pull-down compensation sub-module is used for receiving a corresponding second intermediate data signal, driving the second intermediate data signal and generating a corresponding second pull-down target data signal;

As shown in fig. 8, the pull-down driving compensation module 1212 includes N pull-down compensation sub-modules corresponding to the N second intermediate data signals, i.e., a pull-down compensation sub-module 1, a pull-down compensation sub-module 2, and a pull-down compensation sub-module N. Each pull-down compensation sub-module is provided with a respective compensation coefficient to realize driving processing of the received second intermediate data signal according to the compensation coefficient.

The pull-down compensation sub-module 1 performs driving processing on the second intermediate data signal 1, and the obtained voltage value of the second pull-down target data signal 1 is the product of the voltage value of the second intermediate data signal 1 and the compensation coefficient of the pull-down compensation sub-module 1.

Further, referring to fig. 9, a schematic diagram of a second component structure of a pull-up driving module according to an embodiment of the disclosure is shown. As shown in fig. 9, in some embodiments, at least one pull-up compensation sub-module includes a first pull-up compensation sub-module 1212A, a second pull-up compensation sub-module 1212B, a third pull-up compensation sub-module 1212C, and a fourth pull-up compensation sub-module 1212D, with an input of the first pull-up compensation sub-module 1212A connected to an output of the first data selection sub-module MUX-1, an input of the second pull-up compensation sub-module 1212B connected to an output of the second data selection sub-module MUX-2, an input of the third pull-up compensation sub-module 1212C connected to an output of the third data selection sub-module MUX-3, and an input of the fourth pull-up compensation sub-module 1212D connected to an output of the fourth data selection sub-module MUX-4, wherein:

the first pull-up compensation sub-module 1212A is configured to receive the first intermediate sub-data signal (ffe_tap_0), perform driving processing on the first intermediate sub-data signal, and generate a first pull-up sub-target data signal (ffe_up_0);

The second pull-up compensation sub-module 1212B is configured to receive the second intermediate sub-data signal (ffe_tap_1), perform driving processing on the second intermediate sub-data signal, and generate a second pull-up sub-target data signal (ffe_up_1), where a voltage value of the second pull-up sub-target data signal is a product of a voltage value of the second intermediate sub-data signal and a compensation coefficient of the second pull-up compensation sub-module 1212B;

A third pull-up compensation sub-module 1212C for receiving the third intermediate sub-data signal (ffe_tap_2), driving the third intermediate sub-data signal to generate a third pull-up sub-target data signal (ffe_up_2), wherein the voltage value of the third pull-up sub-target data signal is the product of the voltage value of the third intermediate sub-data signal ffe_tap_2 and the compensation coefficient of the third pull-up compensation sub-module 1212C;

a fourth pull-up compensation sub-module 1212D for receiving the fourth intermediate sub-data signal (ffe_tap_3), driving the fourth intermediate sub-data signal to generate a fourth pull-up sub-target data signal (ffe_up_3), wherein the voltage value of the fourth pull-up sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal ffe_tap_3 and the compensation coefficient of the fourth pull-up compensation sub-module 1212D;

wherein the at least one second pull-up target data signal includes a first pull-up sub-target data signal, a second pull-up sub-target data signal, a third pull-up sub-target data signal, and a fourth pull-up sub-target data signal.

In the embodiment of the disclosure, as shown in fig. 9, taking four taps (4-taps) as an example, the number of the pull-up compensation sub-modules is four, and the first pull-up compensation sub-module 1212A, the second pull-up compensation sub-module 1212B, the third pull-up compensation sub-module 1212C, and the fourth pull-up compensation sub-module 1212D respectively implement driving processing on each intermediate data signal, so as to obtain a corresponding second pull-up target data signal.

For each pull-up compensation sub-module, taking fig. 9 as an example, in some embodiments, the pull-up compensation sub-module includes a PRE-drive module (pre_drv) and a first Main drive module (main_drv1), wherein:

the first main driving module is used for receiving the corresponding second intermediate driving signal, and performing compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-up target data signal.

It should be noted that, in the pull-up compensation sub-module, a PRE-driving module (indicated by pre_drv in fig. 9, abbreviated by Predrive) is used to PRE-drive the received second intermediate data signal, so as to perform the PRE-driving enhancement on the second intermediate data signal, and the specific structure and the working manner thereof may refer to the structure of the existing DRAM and will not be described in detail herein.

It should be further noted that the compensation coefficient (also referred to as tap coefficient or FFE coefficient) of the pull-up compensation sub-module specifically refers to the compensation coefficient of the first Main driving module (indicated by main_drv1 in fig. 9, MAINDRIVER is abbreviated, and for distinguishing from the second Main driving module in the pull-down compensation sub-module, the number 1 is added as a number), and the compensation coefficient of the first Main driving module may be determined by the number of resistors connected in parallel inside the first Main driving module. In addition, the first Main driving module may include one main_drv1 (same as the first pull-up driving Main module 1211A in the pull-up driving Main module 1211), but may be a greater number of main_drv1 connected in parallel, for example, two main_drv1 connected in parallel (see the second pull-up driving Main module 1211B).

In the pull-up driving module 121, the first main driving module is formed by using a P-type metal oxide field effect transistor (PMOS transistor) +resistor. In the pull-up driving main module 1211 shown in fig. 9, a first pull-up driving main module 1211A and three second pull-up driving main modules 1211B are included to respectively receive four control signals default_dr <0>, default_dr <1>, default_dr <2> and default_dr <3>, so as to adjust the number of resistors connected in parallel in the first main driving module, thereby adjusting the driving capability of the first main driving module. The first and second pull-up driving main modules 1211A and 1211B also simultaneously receive the first intermediate data signal to perform a driving process thereon to generate a first pull-up target data signal (default_up_out). Wherein data_up_out represents the pull-up target Data signal.

The pull-up driving compensation module 1212 increases/decreases the voltage across the resistor in the first main driving module by increasing/decreasing a portion of the small current based on the original default output current, thereby increasing/decreasing the output signal voltage.

Further, for the compensation coefficient of the first main driving module (denoted as a pull-up compensation coefficient), referring to fig. 10, a schematic diagram of the composition structure of a pull-up compensation sub-module provided in an embodiment of the disclosure is shown. As shown in fig. 10, in one implementation, the PRE-drive module (pre_drv) is connected to the first Main drive module (main_drv1), wherein:

the pre-driving module 201 is further configured to receive a pull-up compensation control signal, and determine a compensation coefficient of the first main driving module 202 according to the pull-up compensation control signal.

In fig. 10, the first main driving module 202 is composed of a PMOS transistor and a resistor. As shown in fig. 10, for any one of the pull-up compensation sub-modules i, the pre-driving module 201 changes the number of resistors connected in parallel in the first main driving module 202 according to the received pull-up compensation control signal i, thereby changing the output impedance of the first main driving module 202 and further changing the compensation coefficient of the first main driving module 202, so that the voltage value of the finally outputted second pull-up target data signal i is the product of the voltage value of the second intermediate data signal i and the corresponding pull-up compensation coefficient i when the second intermediate data signal i is driven. Wherein i is an integer greater than or equal to 1 and less than or equal to N.

In this way, the embodiment of the disclosure may determine the compensation coefficient of the corresponding first main driving module by using the pull-up compensation control signal, so as to implement driving processing of the corresponding second intermediate data signal according to the compensation coefficient, and finally perform compensation processing on the first target data signal, so as to improve ISI and improve high-speed performance of the data signal. Wherein the pull-up compensation signal may be a region qualifier (Zone Qualifier, ZQ) calibration code, or the like.

Referring to fig. 11, a second schematic diagram of a composition structure of a pull-up compensation sub-module according to an embodiment of the disclosure is shown. As shown in fig. 11, in another implementation, the first main driving module 202 includes a pull-up driving unit 2021 and a multiplier 2022, where:

a pull-up driving unit 2021, configured to perform driving processing on the second intermediate driving signal to obtain a pull-up driving signal;

a multiplier 2022 for performing compensation processing on the pull-up driving signal to obtain a second pull-up target data signal;

the multiplier 2022 is used to control the compensation coefficient of the first main driving module 202.

It should be noted that the embodiments of the present disclosure may also use a multiplier to control the compensation coefficient of the first main driving module 202. In this implementation, as shown in fig. 11, for any one of the pull-up compensation sub-modules i, the pre-driving module 201 receives a corresponding second intermediate data signal i, performs a pre-driving process on the second intermediate data signal i to obtain a corresponding second intermediate driving signal i, and the pull-up driving unit 2021 is formed by a PMOS transistor+resistor, and has the same structure as main_drv1 in fig. 10, and the pull-up driving unit 2021 performs a driving process on the second intermediate driving signal i to obtain a pull-up driving signal i, and then multiplies the pull-up driving signal i by a corresponding pull-up compensation coefficient i to obtain a corresponding second pull-up target data signal i through a process of the multiplier 2022. Wherein i is an integer greater than or equal to 1 and less than or equal to N.

In this way, the embodiment of the disclosure may further control the compensation coefficient of the first main driving module by using the multiplier, so as to implement predistortion processing on signals.

Referring to fig. 12, a second schematic diagram of a composition structure of a pull-down driving module according to an embodiment of the disclosure is shown. As shown in fig. 12, in some embodiments, the at least one pull-down compensation sub-module includes a first pull-down compensation sub-module 1222A, a second pull-down compensation sub-module 1222B, a third pull-down compensation sub-module 1222C, and a fourth pull-down compensation sub-module 1222D, with an input of the first pull-down compensation sub-module 1222A connected to an output of the first data selection sub-module MUX-1, an input of the second pull-down compensation sub-module 1222B connected to an output of the second data selection sub-module MUX-2, an input of the third pull-down compensation sub-module 1222C connected to an output of the third data selection sub-module MUX-3, and an input of the fourth pull-down compensation sub-module 1222D connected to an output of the fourth data selection sub-module MUX-4, wherein:

The first pull-down compensation submodule 1222A is configured to receive a first intermediate data signal (FFE_tap_0), perform driving processing on the first intermediate data signal, and generate a first pull-down sub-target data signal (FFE_down_0);

The second pull-down compensation submodule 1222B is configured to receive a second intermediate data signal (FFE_tap_1), perform driving processing on the second intermediate data signal, and generate a second pull-down target data signal (FFE_down_1);

a third pull-down compensation sub-module 1222C for receiving the third intermediate sub-data signal (ffe_tap_2), driving the third intermediate sub-data signal to generate a third pull-down sub-target data signal (ffe_down_2), wherein the voltage value of the third pull-down sub-target data signal is the product of the voltage value of the third intermediate sub-data signal and the compensation coefficient of the third pull-down compensation sub-module;

A fourth pull-down compensation sub-module 1222D for receiving the fourth intermediate sub-data signal (FFE_tap_3), driving the fourth intermediate sub-data signal to generate a fourth pull-down sub-target data signal (FFE_down_3), wherein the voltage value of the fourth pull-down sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal and the compensation coefficient of the fourth pull-down compensation sub-module;

wherein the at least one second pull-down target data signal includes a first pull-down sub-target data signal, a second pull-down sub-target data signal, a third pull-down sub-target data signal, and a fourth pull-down sub-target data signal.

In the embodiment of the disclosure, as shown in fig. 12, taking four taps (4-tap) as an example, the number of the pull-down compensation submodules is four, namely, the first pull-down compensation submodule 1222A, the second pull-down compensation submodule 1222B, the third pull-down compensation submodule 1222C and the fourth pull-down compensation submodule 1222D, respectively, to implement driving processing on each intermediate data signal, so as to obtain a corresponding second pull-down target data signal.

For each pull-down compensation sub-module, taking fig. 12 as an example, in some embodiments the pull-down compensation sub-module comprises a PRE-drive module (pre_drv) and a second Main drive module (main_drv2), wherein:

and the second main driving module is used for receiving the corresponding second intermediate driving signal, and carrying out compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-down target data signal.

It should be noted that, in the pull-down compensation sub-module, the PRE-driving module (pre_drv) is used for PRE-driving the received second intermediate data signal, and the specific structure and the working manner thereof may refer to the structure of the existing DRAM and will not be described in detail herein. In addition, the pre-driving module in the pull-up compensation sub-module may have the same or different structure from the pre-driving module in the pull-down compensation sub-module, and when the structures are different, the pre-driving module in the pull-up compensation sub-module may be referred to as a first pre-driving module, and the pre-driving module in the pull-down compensation sub-module may be referred to as a pre-driving module for convenience of distinction.

It should be further noted that, the compensation coefficient (also referred to as tap coefficient or FFE coefficient) of the pull-down compensation sub-module specifically refers to the compensation coefficient of the second main driving module, and the compensation coefficient of the second main driving module may be determined by the number of resistors connected in parallel inside the second main driving module. In addition, the second Main driving module may include one main_drv2 (same as the first pull-down driving Main module 1221A in the pull-down driving Main module 1221), but may be a greater number of main_drv2 connected in parallel, for example, two main_drv2 connected in parallel (see the second pull-down driving Main module 1221B).

In the pull-down driving module 121, the second main driving module is formed by N-type metal oxide semiconductor field effect transistors (NEGATIVE CHANNEL METAL Oxide Semiconductor, nmos+resistor), and in the pull-down driving main module 1221 shown in fig. 12, one first pull-down driving main module 1221A and three second pull-down driving main modules 1221B are included to receive four control signals, default_dr <0>, default_dr <1>, default_dr <2>, and default_dr <3>, respectively, so as to adjust the number of resistors connected in parallel in the second main driving module, and thus adjust the driving capability of the second main driving module.

The pull-down driving compensation module 1222 increases/decreases the voltage across the resistor in the second main driving module by increasing/decreasing a portion of the small current based on the original default output current, thereby increasing/decreasing the output signal voltage.

Further, for the compensation coefficient of the second driving main module (denoted as the pull-down compensation coefficient), referring to fig. 13, a schematic diagram of the composition structure of a pull-down compensation sub-module provided in an embodiment of the present disclosure is shown. As shown in fig. 13, in one implementation, the PRE-drive module (pre_drv) is connected to the second Main drive module (main_drv2), wherein:

The pre-driving module 201 is further configured to receive the pull-down compensation control signal, and determine a compensation coefficient of the second main driving module 203 according to the pull-down compensation control signal.

In fig. 13, the second main driving module 203 is composed of an NMOS transistor and a resistor. As shown in fig. 13, for any one of the pull-down compensation sub-modules i, the pre-driving module 201 changes the number of resistors connected in parallel in the second main driving module 203 according to the received pull-down compensation control signal i, thereby changing the output impedance of the second main driving module 203, and further changing the compensation coefficient of the second main driving module 203, so that when the second intermediate data signal i is driven, the voltage value of the finally output second pull-down target data signal i is the product of the voltage value of the second intermediate data signal i and the corresponding pull-down compensation coefficient i. Wherein i is an integer greater than or equal to 1 and less than or equal to N.

In this way, the embodiment of the disclosure may determine the compensation coefficient of the corresponding second main driving module by using the pull-down compensation control signal, so as to implement driving processing of the corresponding second intermediate data signal according to the compensation coefficient, and finally perform compensation processing on the first target data signal, so as to improve ISI and improve high-speed performance of the data signal. The pull-down compensation signal may be a ZQ calibration code, etc.

Referring to fig. 14, a second schematic diagram of a composition structure of a pull-down compensation sub-module according to an embodiment of the disclosure is shown. As shown in fig. 14, in another implementation, the second main driving module 203 includes a pull-down driving unit 2031 and a multiplier 2032, wherein:

A pull-down driving unit 2031, configured to perform driving processing on the second intermediate driving signal to obtain a pull-down driving signal;

multiplier 2032 for performing compensation processing on the pull-down driving signal to obtain a second pull-down target data signal;

Wherein the multiplier 2032 is for controlling the compensation coefficient of the second main drive module 2031.

It should be noted that, the embodiments of the present disclosure may also use a multiplier to control the compensation coefficient of the second main driving module 203. In this implementation, as shown in fig. 14, for any one of the pull-down compensation sub-modules i, the pre-driving module 201 receives the corresponding second intermediate data signal i, performs the pre-driving process on the second intermediate data signal i to obtain the corresponding second intermediate driving signal i, and the pull-down driving unit 2021 is formed by an NMOS transistor+resistor, and has the same structure as main_drv2 in fig. 13, and performs the driving process on the second intermediate driving signal i by the pull-down driving unit 2021 to obtain the pull-down driving signal i, and then multiplies the pull-down driving signal i by the corresponding pull-down compensation coefficient i to obtain the corresponding second pull-down target data signal i through the process of the multiplier 2032. Wherein i is an integer greater than or equal to 1 and less than or equal to N.

In this way, the embodiment of the disclosure may further control the compensation coefficient of the second main driving module by using the multiplier, so as to implement predistortion processing on signals.

Referring to fig. 15, a schematic diagram of a composition structure of a data processing circuit according to an embodiment of the present disclosure is shown. As shown in fig. 15, in some embodiments, the data processing circuit 10 further comprises a shift register module 13, wherein:

The shift register module 13 is configured to receive the first data signal and the clock signal, and perform shift processing on the first data signal according to the clock signal to obtain at least one second data signal.

Specifically, as shown in fig. 15, the shift register module 13 includes at least one shift register, and the number of the at least one shift register and the at least one second data signal is N, where N is an integer greater than 0:

When N is equal to 1, the shift register is used for receiving the first data signal and the clock signal, and carrying out shift processing on the first data signal according to the clock signal to obtain a second data signal;

when N is greater than 1, the 1 st shift register is used for receiving the first data signal and the clock signal, and carrying out shift processing on the first data signal according to the clock signal to obtain a 1 st second data signal;

In fig. 15, taking 4-tap as an example, the shift register module 13 may include four shift registers, wherein the shift registers may be implemented by DFFs, and thus, the four shift registers are denoted as DFF-1, DFF-2, DFF-3, and DFF-4, respectively.

Wherein the DFF-1 shifts the first Data signal data_Z0<3:0> (including four sub-Data D0_Z0, D1_Z0, D2_Z0 and D3_Z0) according to the clock signal (including the first clock Zhong Zi signal ICLK, the second clock sub-signal QCLK, the third clock sub-signal IBCLK and the fourth clock sub-signal QBCLK) to obtain a first sub-Data signal data_Z1<3:0> (including four sub-Data D0_Z1, D1_Z1, D2_Z1 and D3_Z1), and transmits the first sub-Data signal to the MUX-1 while also transmitting the first sub-Data signal to the DFF-2 shifts the first sub-Data signal data_Z1<3:0> (including four sub-Data D0_Z1, D1_Z1, D2_Z1 and D3_Z1) according to the clock signal to obtain a second sub-Data signal Data data_Z2<3 > (including four sub-Data D0_Z1, D2_Z1 and D2_Z2), and transmits the second sub Data signal to MUX-2 while transmitting the first sub Data signal to DFF-3, DFF-3 shifts the second sub Data signal data_Z2<3:0> (including four sub Data D0_Z2, D1_Z2, D2_Z2 and D3_Z2) according to the clock signal to obtain a third sub Data signal data_Z3<3:0> (including four sub Data D0_Z3, D1_Z3, D2_Z3 and D3_Z3), and transmits the third sub Data signal to MUX-3 while transmitting the first sub Data signal to DFF-4, and DFF-4 shifts the third sub Data signal data_Z3<3:0> (including four sub Data D0_Z3, D1_Z3) according to the clock signal, D2_z3 and d3_z3) to obtain a fourth sub Data signal data_z4<3:0> (including four sub Data d0_z4, d1_z4, d2_z4 and d3_z4), and transmitting the fourth sub Data signal to MUX-4.

The operation of the preprocessing module 11 and the driving module 12 is not described here.

In addition, corresponding to fig. 6, referring to fig. 16, which shows a sixth schematic diagram of the composition structure of a data processing circuit provided in the embodiment of the present disclosure, in fig. 16, the register modules are divided into a pull-up register module 13A and a pull-down register module 13B, where the pull-up register module 13A and the pull-down register module 13B have the same structure and function as the register module 13 shown in fig. 15, and are not repeated here.

It should be noted that, as shown in fig. 9 and 12, the difference between the pull-up driving module 121 and the pull-down driving module 122 is that the Main driving stages (main_drv1 and main_drv2) are different, the Main driving of the pull-up driving module 121 is formed by pmos+ resistor, the Main driving of the pull-down driving module 122 is formed by nmos+ resistor, and in general, the Main driving stage needs to ensure that the resistance of one resistor is 240 Ω during different processes, voltages and temperatures (Process, voltage, temperature and PVT). Pre_drv is a secondary driver stage of the DRAM, which mainly functions to adjust the DRAM output impedance in different situations according to Standard (SPEC) requirements. The FFE output drive (the pull-up drive compensation module and the pull-down drive compensation module) has the function of raising/lowering the voltage at two ends of the resistor by increasing/decreasing a part of small current on the basis of the original default output current, so that the output signal voltage can be raised/lowered.

Further, pre_drv in the default output drive (i.e., pull-up drive master module 1211 and pull-down drive master module 1221) is the output impedance of the DRAM at different PVTs controlled by the calibration unit of On-Die Termination (ODT). The FFE selects different resistance values (each MOS tube is provided with a resistor connected in series with the MOS tube, and controls the conduction and the closing of the MOS tubes, namely, controls the resistance values of all the resistors in combination) by finely adjusting the conduction quantity of the MOS tubes in the main_DRV.

Referring to FIG. 17, a second signal timing diagram is shown, wherein (a), (b), (c), and (d) show the generation of high-speed signals corresponding to data_Z1<3:0>, data_Z2<3:0>, data_Z3<3:0>, and data_Z4<3:0>, respectively. The description of the specific generation manner may be understood with reference to fig. 3B and fig. 4 and the related description, and will not be repeated here.

Referring to fig. 18, a signal timing diagram three provided by an embodiment of the disclosure is shown, which takes the case that a 4-tap FFE signal is superimposed on an output driving module as an example, and illustrates the basic principle of the embodiment of the disclosure. Table 1 further illustrates the principle of DRAM FFE (corresponding to the first 13 bits of fig. 18) by specific voltage values, taking sequence 001110100001 as an example.

TABLE 1

Signal signal	1	2	3	4	5	6	7	8	9	10	11	12	13
														Main drv	0.00	0.00	1.00	1.00	1.00	0.00	1.00	0.00	0.00	0.00	0.00	0.00	1.00
Shift 1bit	0.00	0.00	0.00	1.00	1.00	1.00	0.00	1.00	0.00	0.00	0.00	0.00	0.00
														Tap 1	0.00	0.00	0.00	0.30	0.30	0.30	0.00	0.30	0.00	0.00	0.00	0.00	0.00
Shift 2bit	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	1.00	0.00	0.00	0.00	0.00
														Tap 2	0.00	0.00	0.00	0.00	-0.20	-0.20	-0.20	0.00	-0.20	0.00	0.00	0.00	0.00
Shift 3bit	0.00	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	1.00	0.00	0.00	0.00
														Tap 3	0.00	0.00	0.00	0.00	0.00	0.17	0.17	0.17	0.00	0.17	0.00	0.00	0.00
Shift 4bit	0.00	0.00	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	1.00	0.00	0.00
														Tap 4	0.00	0.00	0.00	0.00	0.00	0.00	-0.08	-0.08	-0.08	0.00	-0.08	0.00	0.00
DQ OUT	0.00	0.00	1.00	1.30	1.10	0.27	0.89	0.39	-0.28	0.17	-0.08	0.00	1.00

In table 1 and fig. 18, for convenience of description, data is shown in a serial manner, main represents a first intermediate data signal, that is, a first data signal to be transmitted is subjected to parallel processing, shift bit 1 represents a first intermediate sub data signal, that is, a first data signal is shifted by 1 bit to obtain a first sub data signal and then subjected to parallel processing, shift bit 2 represents a second intermediate sub data signal, that is, a first data signal is shifted by 1 bit to obtain a second sub data signal and then subjected to parallel processing, shift bit 3 represents a third intermediate sub data signal, that is, a second data signal is shifted by 1 bit to obtain a third sub data signal and then subjected to parallel processing, and Shift bit 4 represents a fourth intermediate sub data signal, that is, a third sub data signal is shifted by 1 bit to obtain a fourth sub data signal and then subjected to parallel processing. DQ_OUT represents the target data signal.

It is assumed that the compensation coefficients corresponding to the four pull-up compensation sub-modules in the pull-up driving compensation module 1212 and the four pull-down compensation sub-modules in the pull-down driving compensation module 1222 are respectively 0.3, -0.2, 0.17 and-0.08. That is, the compensation coefficient for compensating the first intermediate sub data signal is 0.3, the compensation coefficient for compensating the second intermediate sub data signal is-0.2, the compensation coefficient for compensating the third intermediate sub data signal is 0.17, and the compensation coefficient for compensating the fourth intermediate sub data signal is-0.08.

Thus, as shown in fig. 18, the waveform of the signal that needs to be transmitted originally is shown as Main, and the waveform of the signal that enters the channel after compensation processing is shown as DQ OUT, when the signal is transmitted through the channel, the influence of ISI can be improved, so that the waveform of the signal that is finally transmitted to the memory controller after the influence of the channel is basically consistent with the waveform of the original transmitted signal, and the distortion of the signal is improved. The reliability of the signal is guaranteed.

Briefly, the present embodiment introduces a four tap DFF in the Data (DQ) transmitter of the DDR5 DRAM, optimizing the signal integrity when the signal reaches the controller. The output current is regulated by using the pull-up driving module and the pull-down driving module, so that the speed of Joint Electron DEVICE ENGINEERING Council (JEDEC) SPEC of the Joint engineering design development association can be met, and FFE is adapted to a higher speed in the DRAM field.

The output resistors include default resistors (the resistor of the main driving stage in the pull-up driving main module and the resistor of the main driving stage in the pull-down driving main module) and FFE resistors (the resistor of the main driving stage in the pull-down driving compensation module and the resistor of the main driving stage in the pull-down driving compensation module). The default resistor adopts a traditional DRAM output circuit structure. The FFE resistance is controlled by the value of the Tap-1/Tap-2/Tap-3/Tap-4 coefficient (compensation coefficient). Wherein the FFE resistor and the conventional default resistor may be connected in parallel. The output resistance, which consists of the FFE resistance and the conventional default resistance, should be as close as possible to the SPEC, but allow for a small range of deviations. In addition, the FFE driving circuit structure is single-ended output, and the output resistance is important, so that SPEC must be satisfied.

The present embodiment relates to a memory, particularly a high-speed memory such as DDR 5. The DDR5 transmitter sends a data signal to the DRAM controller. Because of the high signal rate, the channel attenuation is large and when the signal reaches the controller, the signal integrity at the controller may be poor. To solve this problem, the signal integrity of the TX of DDR5 on the DRAM controller is guaranteed, and the present embodiment proposes a 4-tap FFE circuit that pre-distorts the signal before sending it to the controller. Enabling DDR5 TX to achieve higher data speeds.

In another embodiment of the present disclosure, attention is directed to fig. 19, which is a schematic flow chart illustrating a data processing method provided in an embodiment of the present disclosure, as shown in fig. 19, the method includes:

S191, receiving a first data signal and at least one second data signal through a preprocessing module, sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal, wherein the at least one second data signal is obtained by shifting the first data signal.

S192, receiving the first intermediate data signal and at least one second intermediate data signal through a driving module, performing driving processing on the first intermediate data signal to generate a first target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second target data signal.

In some embodiments, the clock signal includes M clock sub-signals, step S191, including:

receiving M clock sub-signals and M sub-data in the first data signal through a first data selection module, and respectively carrying out selection processing on the M sub-data in the first data signal according to the M clock sub-signals to generate a first intermediate data signal;

Receiving M clock sub-signals and M sub-data in the corresponding second data signals through a second data selection module, and respectively carrying out selection processing on the M sub-data in the second data signals according to the M clock sub-signals to generate corresponding second intermediate data signals;

Wherein, M clock sub-signals and M sub-data are in one-to-one correspondence.

In some embodiments, the selecting the data signal by the data selecting module to generate the intermediate data signal includes:

receiving M clock sub-signals through a clock generation module, and generating M target clock sub-signals according to the M clock sub-signals, wherein the target clock sub-signals are frequency multiplication signals of the corresponding clock sub-signals;

receiving the y sub-data and the y clock sub-signal through the y D trigger, and sampling the y sub-data according to the y clock sub-signal to obtain y sampling sub-data;

Receiving a y-th target clock sub-signal and y-th sampling sub-data through a y-th switch unit, and outputting the y-th sampling sub-data as y-th intermediate sub-data under the condition that the y-th target clock sub-signal is in an effective state;

In some embodiments, sampling the at least one second data signal to obtain at least one second intermediate data signal comprises:

Receiving M clock sub-signals and M sub-data in the first sub-data signals through a first data selection sub-module, and respectively carrying out selection processing on the M sub-data in the first sub-data signals according to the M clock sub-signals to generate a serial first intermediate sub-data signal;

receiving M clock sub-signals and M sub-data in the second sub-data signals through a second data selection sub-module, and respectively selecting and processing the M sub-data in the second sub-data signals according to the M clock sub-signals to generate a serial second intermediate sub-data signal;

receiving M clock sub-signals and M sub-data in the third sub-data signals through a third data selection sub-module, and respectively selecting and processing the M sub-data in the third sub-data signals according to the M clock sub-signals to generate a serial third intermediate sub-data signal;

Receiving M clock sub-signals and M sub-data in the fourth sub-data signal through a fourth data selection sub-module, and respectively selecting and processing the M sub-data in the fourth sub-data signal according to the M clock sub-signals to generate a serial fourth intermediate sub-data signal;

wherein the at least one second intermediate data signal comprises a first intermediate sub-data signal, a second intermediate sub-data signal, a third intermediate sub-data signal and a fourth intermediate sub-data signal.

In some embodiments, step S192 includes:

s1921, receiving the first intermediate data signal and at least one second intermediate data signal through a pull-up driving module, performing driving processing on the first intermediate data signal to generate a first pull-up target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second pull-up target data signal;

S1922, receiving the first intermediate data signal and the at least one second intermediate data signal through a pull-down driving module, performing driving processing on the first intermediate data signal to generate a first pull-down target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second pull-down target data signal;

In some embodiments, step S1921 comprises:

Receiving a first intermediate data signal through a pull-up driving main module, and driving the first intermediate data signal to generate a first pull-up target data signal;

and receiving at least one second intermediate data signal through a pull-up driving compensation module, and driving the at least one second intermediate data signal to generate at least one second pull-up target data signal.

In some embodiments, step S1922 includes:

Receiving a first intermediate data signal by a pull-down driving main module, and driving the first intermediate data signal to generate a first pull-down target data signal;

And receiving at least one second intermediate data signal through the pull-down driving compensation module, and driving the at least one second intermediate data signal to generate at least one second pull-down target data signal.

In some embodiments, receiving the at least one second intermediate data signal by the pull-up drive compensation module, driving the at least one second intermediate data signal, generating at least one second pull-up target data signal, includes:

receiving a corresponding second intermediate data signal through a pull-up compensation submodule, and performing driving processing on the second intermediate data signal to generate a corresponding second pull-up target data signal;

the first pull-up compensation sub-module is used for receiving a first intermediate sub-data signal, and driving the first intermediate sub-data signal to generate a first pull-up sub-target data signal, wherein the voltage value of the first pull-up sub-target data signal is the product of the voltage value of the first intermediate sub-data signal and the compensation coefficient of the first pull-up compensation sub-module;

Receiving a second intermediate sub-data signal through a second pull-up compensation sub-module, and performing driving processing on the second intermediate sub-data signal to generate a second pull-up sub-target data signal, wherein the voltage value of the second pull-up sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-up compensation sub-module;

Receiving a third intermediate sub-data signal through a third pull-up compensation sub-module, and performing driving processing on the third intermediate sub-data signal to generate a third pull-up sub-target data signal, wherein the voltage value of the third pull-up sub-target data signal is the product of the voltage value of the third intermediate sub-data signal and the compensation coefficient of the third pull-up compensation sub-module;

Receiving a fourth intermediate sub-data signal through a fourth pull-up compensation sub-module, and performing driving processing on the fourth intermediate sub-data signal to generate a fourth pull-up sub-target data signal, wherein the voltage value of the fourth pull-up sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal and the compensation coefficient of the fourth pull-up compensation sub-module;

In some embodiments, receiving the at least one second intermediate data signal by the pull-down drive compensation module, driving the at least one second intermediate data signal, generating at least one second pull-down target data signal, includes:

Receiving a corresponding second intermediate data signal through a pull-down compensation submodule, and performing driving processing on the second intermediate data signal to generate a corresponding second pull-down target data signal;

the first intermediate sub data signal is received through the first pull-down compensation sub module, and is driven to generate a first pull-down sub target data signal, wherein the voltage value of the first pull-down sub target data signal is the product of the voltage value of the first intermediate sub data signal and the compensation coefficient of the first pull-down compensation sub module;

receiving a second intermediate sub-data signal through a second pull-down compensation sub-module, and performing driving processing on the second intermediate sub-data signal to generate a second pull-down sub-target data signal, wherein the voltage value of the second pull-down sub-target data signal is the product of the voltage value of the second intermediate sub-data signal and the compensation coefficient of the second pull-down compensation sub-module;

receiving a third intermediate sub-data signal through a third pull-down compensation sub-module, and performing driving processing on the third intermediate sub-data signal to generate a third pull-down sub-target data signal, wherein the voltage value of the third pull-down sub-target data signal is the product of the voltage value of the third intermediate sub-data signal and the compensation coefficient of the third pull-down compensation sub-module;

Receiving a fourth intermediate sub-data signal through a fourth pull-down compensation sub-module, and performing driving processing on the fourth intermediate sub-data signal to generate a fourth pull-down sub-target data signal, wherein the voltage value of the fourth pull-down sub-target data signal is the product of the voltage value of the fourth intermediate sub-data signal and the compensation coefficient of the fourth pull-down compensation sub-module;

In some embodiments, the step of receiving the corresponding second intermediate data signal through the pull-up compensation submodule, and performing driving processing on the second intermediate data signal to obtain a corresponding second pull-up target data signal includes:

receiving a corresponding second intermediate data signal through a pre-driving module, and performing pre-driving processing on the second intermediate data signal to generate a corresponding second intermediate driving signal;

And receiving a corresponding second intermediate driving signal through the first main driving module, and performing compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-up target data signal.

In some embodiments, the method further comprises:

And the pre-driving module is also used for receiving the pull-up compensation control signal and determining the compensation coefficient of the first main driving module according to the pull-up compensation control signal.

In some embodiments, receiving, by the first main driving module, a corresponding second intermediate driving signal, performing compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-up target data signal, including:

receiving a second intermediate driving signal through a pull-up driving unit, and driving the second intermediate driving signal to obtain a pull-up driving signal;

receiving the pull-up driving signal through a multiplier, and performing compensation processing on the pull-up driving signal to obtain a second pull-up target data signal;

In some embodiments, the step of receiving the corresponding second intermediate data signal through the pull-down compensation submodule, and performing driving processing on the second intermediate data signal to obtain a corresponding second pull-down target data signal includes:

and receiving a corresponding second intermediate driving signal through a second main driving module, and performing compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-down target data signal.

In some embodiments, the method further comprises:

and receiving the pull-down compensation control signal through the pre-driving module, and determining the compensation coefficient of the second main driving module according to the pull-down compensation control signal.

In some embodiments, receiving, by the second main driving module, a corresponding second intermediate driving signal, performing compensation driving processing on the second intermediate driving signal to obtain a corresponding second pull-down target data signal, including:

receiving a second intermediate driving signal through a pull-down driving unit, and driving the second intermediate driving signal to obtain a pull-down driving signal;

receiving the pull-down driving signal through a multiplier, and performing compensation processing on the pull-down driving signal to obtain a second pull-down target data signal;

In some embodiments, the method further comprises:

And receiving the first data signal and the clock signal through the shift register module, and carrying out shift processing on the first data signal according to the clock signal to obtain at least one second data signal.

In some embodiments, the number of the at least one shift register and the at least one second data signal are each N, N being an integer greater than 0, wherein:

when N is equal to 1, the shift register module receives the first data signal and the clock signal, and performs shift processing on the first data signal according to the clock signal to obtain at least one second data signal, including:

Receiving the first data signal and the clock signal through the shift register, and carrying out shift processing on the first data signal according to the clock signal to obtain a second data signal;

When N is greater than 1, the shift register module is used for receiving the first data signal and the clock signal, and shifting the first data signal according to the clock signal to obtain at least one second data signal, wherein the shift register module comprises:

receiving a first data signal and a clock signal through a 1 st shift register, and carrying out shift processing on the first data signal according to the clock signal to obtain a 1 st second data signal;

And receiving the ith-1 second data signal and the clock signal through the ith shift register, and carrying out shift processing on the ith-1 second data signal according to the clock signal to obtain the ith second data signal, wherein i is an integer which is more than 1 and less than or equal to N.

It should be noted that, the method is applied to the data processing circuit 10 of the foregoing embodiment, and details and specific descriptions of the embodiments of the present disclosure that are not disclosed are omitted herein.

The embodiment of the disclosure provides a data processing method, which is characterized in that at least one second data signal is obtained by performing shift processing on a first data signal to be transmitted, and then the first data signal and the at least one second data signal are respectively driven to obtain a first target data signal and at least one second target data signal, and the first target data signal is compensated by the at least one second target data signal to form a target data signal. Therefore, predistortion processing of signals is realized, and the accuracy of signals received by the controller after the signals are transmitted through the channel is ensured.

In yet another embodiment of the present disclosure, reference is made to fig. 20, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. As shown in fig. 20, the memory 200 may include at least the data processing circuit 10 according to any of the preceding embodiments.

In some embodiments, memory 10 is a semiconductor memory, such as a DRAM chip.

In the embodiment of the present disclosure, the DRAM chip may not only conform to the memory specifications of DDR, DDR2, DDR3, DDR4, DDR5, etc., but also conform to the memory specifications of LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., which is not limited herein.

Since the memory 200 includes the data processing circuit 10, the memory can improve the bad influence of ISI on signals, ensure the transmission performance of signals, and facilitate the improvement of the high-speed performance of the memory.

In yet another embodiment of the present disclosure, reference is made to fig. 21, which illustrates a schematic diagram of the composition of a storage system provided by an embodiment of the present disclosure. As shown in fig. 21, the memory system 400 includes the memory 200 and the memory controller 300 in the foregoing embodiments, wherein the memory 200 and the memory controller 300 are connected through a channel.

In the memory system 400, since the memory 200 includes the data processing circuit 10, when signals are transmitted to the memory controller 300 via channels, the effect of predistortion and distortion of the channels cancel each other, so that the influence of ISI on the signals is improved, and the reliability of the signals is ensured.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data processing circuit, comprising: a preprocessing module and a driving module, wherein the output end of the preprocessing module is connected to the input end of the driving module, wherein:

The pre-processing module is configured to receive a first data signal and at least one second data signal; sample the first data signal according to a clock signal to obtain a first intermediate data signal, and sample the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal;

The driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal; perform driving processing on the first intermediate data signal to generate a first target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

The first data signal and the second data signal are both parallel data signals, the first intermediate data signal and the second intermediate data signal are both serial data signals, and the at least one second target data signal is used to compensate the first target data signal to form a target data signal.

2. The data processing circuit according to claim 1 , wherein the preprocessing module comprises a first data selection module and at least one second data selection module, and the at least one second data selection module corresponds one-to-one to the at least one second data signal, the first data signal and the second data signal each comprise M parallel sub-data, and the clock signal comprises M clock sub-signals, wherein:

the first data selection module is configured to receive the M clock sub-signals and the M sub-data in the first data signal, and sample the M sub-data in the first data signal according to the M clock sub-signals to generate the first intermediate data signal;

the second data selection module is configured to receive the M clock sub-signals and the corresponding M sub-data in the second data signal, and sample the M sub-data in the second data signal according to the M clock sub-signals to generate the corresponding second intermediate data signal;

The M clock sub-signals and the M sub-data correspond one to one.

3. The data processing circuit according to claim 2, wherein the data selection module comprises: a clock generation module, M D flip-flops, and M switch units, wherein one D flip-flop and one switch unit are connected in series; the data selection module represents any one of the first data selection module and the at least one second data selection module, wherein:

The clock generation module is configured to receive the M clock sub-signals and generate M target clock sub-signals according to the M clock sub-signals, wherein the target clock sub-signals are frequency-multiplied signals of the clock sub-signals;

the yth D flip-flop, configured to receive the yth sub-data and the yth clock sub-signal, and sample the yth sub-data according to the yth clock sub-signal to obtain the yth sampled sub-data;

the yth switching unit is configured to receive the yth target clock sub-signal and the yth sampled sub-data, and output the yth sampled sub-data as the yth intermediate sub-data when the yth target clock sub-signal is in a valid state;

Wherein, y is an integer greater than or equal to 1 and less than or equal to M, the M intermediate sub-data constitute an intermediate data signal, and the intermediate data signal represents any one of the first data signal and the at least one second data signal.

4. The data processing circuit according to claim 1, wherein the driving module comprises a pull-up driving module and a pull-down driving module, wherein:

The pull-up driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-up target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-up target data signal;

The pull-down driving module is configured to receive the first intermediate data signal and the at least one second intermediate data signal, perform driving processing on the first intermediate data signal to generate a first pull-down target data signal; and perform driving processing on the at least one second intermediate data signal to generate at least one second pull-down target data signal;

The first target data signal includes the first pull-up target data signal and/or the first pull-down target data signal, and the at least one second target data signal includes the at least one second pull-up target data signal and/or the at least one second pull-down target data signal.

5. The data processing circuit according to claim 4 , wherein the pull-up driving module comprises a pull-up driving main module and a pull-up driving compensation module, the pull-up driving compensation module comprises at least one pull-up compensation submodule, the at least one pull-up compensation submodule corresponds to the at least one second intermediate data signal in a one-to-one manner, wherein:

The pull-up compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-up target data signal;

The voltage value of the second pull-up target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-up compensation submodule.

6. The data processing circuit according to claim 4 , wherein the pull-down driving module comprises a pull-down driving main module and a pull-down driving compensation module, the pull-down driving compensation module comprises at least one pull-down compensation submodule, the at least one pull-down compensation submodule corresponds to the at least one second intermediate data signal in a one-to-one manner, wherein:

The pull-down compensation submodule is configured to receive the corresponding second intermediate data signal, perform drive processing on the second intermediate data signal, and generate the corresponding second pull-down target data signal;

The voltage value of the second pull-down target data signal is the product of the voltage value of the second intermediate data signal and the compensation coefficient of the pull-down compensation submodule.

7. The data processing circuit according to claim 5, wherein the pull-up compensation submodule comprises a pre-driver module and a first main driver module, wherein:

The pre-driving module is configured to receive the corresponding second intermediate data signal, perform pre-driving processing on the second intermediate data signal, and generate a corresponding second intermediate driving signal;

The first main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-up target data signal.

8. The data processing circuit according to claim 7, wherein the pre-driver module is connected to the first main driver module; wherein:

The pre-driving module is further configured to receive a pull-up compensation control signal and determine a compensation coefficient of the first main driving module according to the pull-up compensation control signal.

9. The data processing circuit according to claim 7, wherein the first main driving module comprises a pull-up driving unit and a multiplier, wherein:

The pull-up driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-up driving signal;

The multiplier is configured to perform compensation processing on the pull-up driving signal to obtain the second pull-up target data signal;

The multiplier is used to control the compensation coefficient of the first main driving module.

10. The data processing circuit according to claim 6, wherein the pull-down compensation submodule comprises a pre-driver module and a second main driver module, wherein:

The second main driving module is configured to receive the corresponding second intermediate driving signal, perform compensation driving processing on the second intermediate driving signal, and obtain the corresponding second pull-down target data signal.

11. The data processing circuit according to claim 10, wherein the pre-driver module is connected to the second main driver module; wherein:

The pre-driving module is further configured to receive a pull-down compensation control signal and determine a compensation coefficient of the second main driving module according to the pull-down compensation control signal.

12. The data processing circuit according to claim 10, wherein the second main driving module comprises a pull-down driving unit and a multiplier, wherein:

The pull-down driving unit is configured to perform driving processing on the second intermediate driving signal to obtain a pull-down driving signal;

The multiplier is configured to perform compensation processing on the pull-down driving signal to obtain the second pull-down target data signal;

The multiplier is used to control the compensation coefficient of the second main driving module.

13. The data processing circuit according to any one of claims 1 to 12, further comprising a shift register module, wherein:

14. The data processing circuit according to claim 13, wherein the shift register module comprises at least one shift register, the number of the at least one shift register and the number of the at least one second data signal are both N, where N is an integer greater than 0, wherein:

When N is equal to 1, the shift register is used to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain the second data signal;

When N is greater than 1, the first shift register is configured to receive the first data signal and the clock signal, and shift the first data signal according to the clock signal to obtain a first second data signal;

The i-th shift register is used to receive the i-1-th second data signal and the clock signal, and shift the i-1-th second data signal according to the clock signal to obtain the i-th second data signal; wherein i is an integer greater than 1 and less than or equal to N.

15. A data processing method, characterized in that the method comprises:

receiving a first data signal and at least one second data signal through a preprocessing module; sampling the first data signal according to a clock signal to obtain a first intermediate data signal, and sampling the at least one second data signal according to the clock signal to obtain at least one second intermediate data signal; wherein the at least one second data signal is obtained by performing a shift process on the first data signal;

receiving the first intermediate data signal and the at least one second intermediate data signal through a driving module; performing driving processing on the first intermediate data signal to generate a first target data signal, and performing driving processing on the at least one second intermediate data signal to generate at least one second target data signal;

16. A memory, comprising the data processing circuit according to any one of claims 1 to 14.