CN116244228A

CN116244228A - AXI protocol-based memory arbitration method and device and memory controller

Info

Publication number: CN116244228A
Application number: CN202310091936.9A
Authority: CN
Inventors: 湛厚超; 黄杨国
Original assignee: Rockchip Electronics Co Ltd
Current assignee: Rockchip Electronics Co Ltd
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2023-06-09

Abstract

The present disclosure provides a memory arbitration method and device based on AXI protocol, and a memory controller. The AXI protocol-based memory arbitrator device includes: an arbitration module comprising an arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order; and a receiving module configured to receive an AXI read request and/or an AXI write request and to input the AXI read request and/or the AXI write request into the arbitration chain of the arbitration module, wherein the arbitration module is configured to arbitrate the AXI read request and/or the AXI write request based on the various arbitration mechanisms of the arbitration chain to output a granted request. In the technical scheme of the disclosure, cascade arbitration is realized by connecting a plurality of arbitration mechanisms in series so as to meet arbitration requirements of different application scenes.

Description

AXI protocol-based memory arbitration method and device and memory controller

Technical Field

The present disclosure relates to the field of memory technology, and in particular, to a method and apparatus for memory arbitration, a memory controller, an electronic device, and a computer-readable storage medium based on AXI protocol.

Background

AXI (Advanced eXtensible Interface) is a bus protocol, which is the most important part of AMBA (Advanced Microcontroller Bus Architecture) 3.0.0 protocols proposed by ARM corporation, and is an on-chip bus with high performance, high bandwidth and low latency. The address/control and the data phase are separated, the misaligned data transmission is supported, only the first address is needed in burst transmission, the out-of-order transmission access and the out-of-order access are supported, and the timing sequence convergence is easier to carry out. AXI is a new high performance protocol in AMBA. AXI technology enriches the existing AMBA standard content and meets the requirements of ultra-high performance and complex system on chip (SoC) design.

Because the AXI protocol has the characteristic of parallel reading and writing, the device using AXI transmission has the problem of competing reading and writing, and the storage controller is one type. For Double Data Rate (DDR) synchronous dynamic random access memories, when the memory controller receives read and write access requests from the AXI bus at the same time, a read and write Data collision may occur, i.e., there is an overlap in address space accessed by the read and write requests.

Arbitration methods are commonly used in the prior art to handle the read-write data collision. Arbitration includes fixed priority arbitration, time-division multiplexing arbitration, random arbitration, polling arbitration, and the like. However, with the diversification of SoC system application scenarios, no arbitration method can meet the data access requirements of all scenarios.

Disclosure of Invention

Embodiments of the present disclosure provide a memory arbitration method and apparatus, a memory controller, an electronic device, and a computer-readable storage medium based on AXI protocol, which implement cascade arbitration by concatenating multiple arbitration mechanisms to meet arbitration requirements of different application scenarios.

In a first aspect, the present disclosure provides a memory arbitration device based on the AXI protocol. The device comprises: an arbitration module comprising an arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order; and a receiving module configured to receive an AXI read request and/or an AXI write request and to input the AXI read request and/or the AXI write request into the arbitration chain of the arbitration module, wherein the arbitration module is configured to arbitrate the AXI read request and/or the AXI write request based on the various arbitration mechanisms of the arbitration chain to output a granted request.

In one implementation of the first aspect, the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method.

In an implementation manner of the first aspect, the configurable order is determined by configuration information of a register, and different configuration information corresponds to different cascading orders of the plurality of arbitration mechanisms.

In an implementation manner of the first aspect, the receiving module includes: a caching module configured to receive and cache at least one of said AXI read requests and/or at least one of said AXI write requests; and an input module configured to input at least one of the AXI read requests and/or at least one of the AXI write requests simultaneously into the arbitration chain.

In one implementation of the first aspect, the arbitration module is configured to: arbitrating the AXI read request and/or the AXI write request by adopting an arbitration mechanism positioned at a first stage in the arbitration chain; if the arbitration is successful, outputting the authorized AXI read request and/or the AXI write request based on an arbitration result; if the arbitration fails, adopting an arbitration mechanism positioned at the next stage in the arbitration chain to arbitrate the AXI read request and/or the AXI write request until the arbitration is successful.

In one implementation manner of the first aspect, the apparatus further includes a counter, an initial count value of the counter being zero, the counter being configured to: adding one to the count value for each time of arbitration so as to determine an arbitration mechanism corresponding to the next arbitration according to the count value and the configurable order; and zeroing the count value after the arbitration is successful.

In one implementation manner of the first aspect, the apparatus further includes a protocol conversion module configured to receive the authorized request, and perform protocol conversion on the authorized request to access the memory based on the protocol-converted authorized request.

In a second aspect, the present disclosure provides a memory arbitration method based on AXI protocol, applied to a memory controller. The method comprises the following steps: inputting a received AXI read request and/or AXI write request into an arbitration chain, the arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order; and arbitrating the AXI read request and/or the AXI write request based on the plurality of arbitration mechanisms of the arbitration chain to output a granted request.

In one implementation of the second aspect, the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method.

In one implementation manner of the second aspect, the method further includes: the configurable order is determined by setting configuration information for registers in the memory controller, different configuration information corresponding to different concatenation orders for the plurality of arbitration mechanisms.

In one implementation of the second aspect, inputting the received AXI read request and/or AXI write request into the arbitration chain includes: receiving and caching at least one AXI read request and/or at least one AXI write request; and simultaneously inputting at least one of said AXI read requests and/or at least one of said AXI write requests into said arbitration chain.

In one implementation of the second aspect, arbitrating the AXI read request and/or the AXI write request based on the plurality of arbitration mechanisms of the arbitration chain to output a granted request includes: arbitrating the AXI read request and/or the AXI write request by adopting an arbitration mechanism positioned at a first stage in the arbitration chain; if the arbitration is successful, outputting the authorized AXI read request and/or the AXI write request based on an arbitration result; if the arbitration fails, adopting an arbitration mechanism positioned at the next stage in the arbitration chain to arbitrate the AXI read request and/or the AXI write request until the arbitration is successful.

In one implementation manner of the second aspect, the method further includes: setting a counter, wherein the initial count value of the counter is zero; adding one to the count value for each time of arbitration so as to determine an arbitration mechanism corresponding to the next arbitration according to the count value and the configurable order; and zeroing the count value after the arbitration is successful.

In one implementation manner of the second aspect, the method further includes: and carrying out protocol conversion on the authorized request so as to access the memory based on the authorized request after protocol conversion.

In a third aspect, the present disclosure provides a memory controller. The memory controller includes: the memory arbitration device based on the AXI protocol; and a register configured to store configuration information corresponding to a concatenation order of the plurality of arbitration mechanisms.

In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon. The computer program, when executed, implements a memory arbitration method according to the AXI protocol described above.

In a fifth aspect, the present disclosure provides an electronic device. The electronic device includes: a memory configured to store a computer program; and a processor configured to execute the computer program to cause the electronic device to perform a memory arbitration method according to the AXI protocol described above.

According to the embodiment of the disclosure, the memory arbitration method and device based on the AXI protocol, the memory controller, the electronic equipment and the computer readable storage medium construct an arbitration chain by connecting a plurality of arbitration mechanisms in series, and the position of the arbitration mechanism in the arbitration chain can be flexibly adjusted through the configuration register so as to meet the arbitration requirements of different application scenes, so that the universality is good, the consistency of data access can be well ensured, and the access efficiency of the memory controller is improved; at the same time, the present disclosure is directed to arbitration of AXI read-write requests for a single interface only, where the read-write requests may come from different hosts.

Drawings

FIG. 1 is a schematic diagram of an AXI protocol-based memory arbitration device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an arbitration sequence of an arbitration module according to one embodiment of the disclosure;

FIG. 3 is a schematic diagram of an arbitration module according to an embodiment of the disclosure;

FIG. 4 is a flow chart of an embodiment of the method for AXI protocol-based memory arbitration according to the present disclosure;

FIG. 5 is a schematic diagram of an electronic device according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a memory controller according to an embodiment of the disclosure.

Detailed Description

Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

According to the AXI protocol-based memory arbitration method and device and the memory controller, various arbitration mechanisms are built in the memory controller, different arbitration mechanism sequences can be configured according to different scene characteristics, and an arbitration chain which is matched with different application scenes is obtained, so that the consistency of data access can be well ensured, the access efficiency of the memory controller is improved, and the universality of the SoC applicable to multiple scenes is improved.

Hereinafter, embodiments according to the present disclosure are described by way of specific embodiments with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a memory arbitration device based on AXI protocol according to the present disclosure in an embodiment. As shown in fig. 1, the AXI protocol-based memory arbitration device of the present disclosure includes a receiving module 1 and an arbitration module 2.

The arbitration module 2 comprises an arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order. The receiving module 1 is connected to the arbitration module 2 and is configured to receive an AXI read request and/or an AXI write request and input the AXI read request and/or the AXI write request into the arbitration chain of the arbitration module 2, wherein the arbitration module 2 is configured to arbitrate the AXI read request and/or the AXI write request based on the various arbitration mechanisms of the arbitration chain to output a granted request.

In some embodiments, multiple arbitration mechanisms cascaded in a configurable order in the memory controller form an arbitration chain. In some embodiments, the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method. The cascade order of the plurality of arbitration mechanisms is determined by configuration information of a register arb_seq in the memory controller, different configuration information corresponding to a different cascade order than the plurality of arbitration mechanisms. Therefore, different arbitration mechanism cascading sequences can be selected according to different application scenes.

It is assumed that three arbitration mechanisms of ABC are respectively fixed host master priority arbitration, access storage address arbitration and read-write polling arbitration. When the register arb_seq is configured to 3' B001, this indicates that the arbitration chain order is A-B-C; when arb_seq is configured as 3' B010, it indicates that the arbitration chain order is B-A-C; when arb_seq is configured as 3' B100, this indicates that the arbitration chain order is C-A-B.

For example, in the vehicle field, it is necessary to set a master (master) to transmit fastest, and its transmission speed is better than that of all other masters, and the memory register may configure the register arb_seq to 3' b001. At this time, the memory controller places the fixed host priority arbitration method in a first order. When the master initiates read-write access at the same time, the subsequent memory address arbitration and read-write polling arbitration are entered.

For another example, in the field of edge computing, it is desirable to design access priority to a block or page of memory to be highest, while accessing a block based on host arbitration. When the same host initiates a read-write request, and arbitrates according to the read-write poll, the memory controller may configure the register arb_seq to be 3' b010.

For another example, an arbitration logic that can distinguish priority, such as read-write polling arbitration, needs to be configured in the arbitration chain. In the above example, the arbitration chain order is A-B-C when the register arb_seq is configured as 3' B001. In most cases, arbitration results have been obtained by means of fixed host priority and access memory address arbitration. If the same host computer appears, the same block of memory address is accessed simultaneously, and then the arbitration is carried out according to the read-write polling. The previous step is read transmission, then the current is write transmission; the last step is a write transfer, then the current is a read transfer. At this point, priority may be assigned.

The receiving module 1 receives an AXI read request and an AXI write request, and then inputs the AXI read request and the AXI write request into the arbitration chain at the same time. In one embodiment, the receiving module 1 includes a buffering module 11 and an input module 12. The caching module 11 is configured to receive and cache at least one of the AXI read requests and/or at least one of the AXI write requests. In some embodiments, the buffer module 11 includes a write address/control signal buffer module, a write data buffer module, a write response buffer module, a read address/control signal buffer module, and a read data buffer module. The input module 12 is connected to the cache module 11 and is configured to input at least one AXI read request and/or at least one AXI write request into the arbitration chain simultaneously, so that the arbitration chain performs arbitration processing on the AXI read request and/or the AXI write request.

The arbitration chain in the arbitration module 2 performs arbitration processing on the AXI read request and/or the AXI write request according to a cascade sequence of a plurality of blanking mechanisms. As shown in fig. 2, the arbitration module 2 sequentially arbitrates the AXI read request and/or the AXI write request according to the first-level arbitration sequence, the second-level arbitration sequence, and the third-level arbitration sequence … … until an arbitration result can be obtained. Specifically, after the arbitration chain receives the AXI read request and/or the AXI write request, an arbitration mechanism positioned at a first stage in the arbitration chain is adopted to arbitrate the AXI read request and/or the AXI write request; if the arbitration is successful, outputting the authorized AXI read request and/or the AXI write request based on an arbitration result; if the arbitration fails, adopting an arbitration mechanism positioned at the next stage in the arbitration chain to arbitrate the AXI read request and/or the AXI write request until the arbitration is successful.

In one embodiment, as shown in fig. 3, the AXI protocol-based memory arbitration device of the present disclosure further includes a Counter (Counter), whose initial count value is zero. And adding one to the count value for each time of arbitration, determining an arbitration mechanism corresponding to the next time of arbitration according to the count value and the configurable order, and zeroing the count value after the arbitration is successful. In performing arbitration, the arb_req_x arbitration request signal of the corresponding arbitration method is pulled up according to the set value of the register arb_seq and the result of the Comparator. For example, when the register arb_seq is configured to 3' B001, the arbitration chain is a-B-C in order, and the arbitration count is performed by the counter. Then the arb_req_a arbitration request signal is pulled high when arb_seq equals 3' b001 and the counter value equals 0. Here both "equal" determination operations require comparators to perform. Similarly, the conditions for pulling the arb_req_b arbitration request signal high are: when arb_seq equals 3' b001 and the counter value equals 1. And if the arbitration fails, the arb_x_fail signal is used for enabling to indicate that the counter is increased by one, and the arbitration method corresponding to the next arbitration is determined according to the count value and the preset sequence. If the arbitration is successful, the arbitration result is output through the arb_x_result, and the counter is cleared.

In an embodiment, the AXI protocol-based memory arbitration device of the present disclosure further includes a protocol conversion module 3, where the protocol conversion module 3 is connected to the arbitration module 2 and configured to receive the grant request, and perform protocol conversion on the grant request to access the memory based on the granted request after the protocol conversion.

It should be noted that, the implementation device of the AXI protocol-based memory arbitration device according to the present disclosure includes, but is not limited to, the structure of the AXI protocol-based memory arbitration device set forth in the present embodiment, and all structural modifications and substitutions made in accordance with the principles of the present disclosure in the prior art are included in the scope of protection of the present disclosure.

Fig. 4 is a flow chart illustrating an AXI protocol-based memory arbitration method of the present disclosure in one embodiment. As shown in fig. 4, the AXI protocol-based memory arbitration method of the present disclosure is applied to a memory controller, and includes steps S1 and S2.

In step S1, the received AXI read request and/or AXI write request is entered into an arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order.

In some embodiments, multiple arbitration mechanisms cascaded in a configurable order in the memory controller form an arbitration chain. In some embodiments, the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method. The cascade order of the plurality of arbitration mechanisms is determined by configuration information of a register arb_seq in the memory controller; different configuration information corresponds to different cascading orders than the plurality of arbitration mechanisms. Therefore, different arbitration mechanism cascading sequences can be selected according to different application scenes.

The three arbitration methods of ABC are respectively fixed host master priority arbitration, access storage address arbitration and read-write polling arbitration. When the register arb_seq is configured to 3' B001, this indicates that the arbitration chain order is A-B-C; when arb_seq is configured as 3' B010, it indicates that the arbitration chain order is B-A-C; when arb_seq is configured as 3' B100, this indicates that the arbitration chain order is C-A-B.

The memory controller, upon receiving an AXI read request and/or an AXI write request, simultaneously enters the AXI read request and/or the AXI write request into the arbitration chain. In some embodiments, inputting the received AXI read request and/or AXI write request into the arbitration chain includes: receiving and caching at least one AXI read request and/or at least one AXI write request; at least one of the AXI read requests and/or at least one of the AXI write requests is entered into the arbitration chain simultaneously. In some embodiments, the caches may employ a write address/control signal cache module, a write data cache module, a write response cache module, a read address/control signal cache module, and a read data cache module. And inputting the AXI read request and/or the AXI write request into the arbitration chain simultaneously, so that the arbitration chain can perform arbitration processing on the AXI read request and/or the AXI write request.

In step S2, the AXI read request and/or the AXI write request is arbitrated based on the plurality of arbitration mechanisms of the arbitration chain to output a granted request.

In some embodiments, the arbitration chain arbitrates the AXI read requests and/or the AXI write requests according to a cascade sequence of a plurality of blanking mechanisms. As shown in fig. 2, the arbitration module 2 sequentially arbitrates the AXI read request and/or the AXI write request according to the first-level arbitration sequence, the second-level arbitration sequence, and the third-level arbitration sequence … … until an arbitration result can be obtained. Specifically, after the arbitration chain receives the AXI read request and the AXI write request, an arbitration mechanism positioned at a first stage in the arbitration chain is adopted to arbitrate the AXI read request and/or the AXI write request; if the arbitration is successful, outputting the authorized AXI read request and/or the AXI write request based on an arbitration result; if the arbitration fails, adopting an arbitration mechanism positioned at the next stage in the arbitration chain to arbitrate the AXI read request and/or the AXI write request until the arbitration is successful.

In one embodiment, the AXI protocol-based memory arbitration method of the present disclosure further includes setting a Counter (Counter) whose initial count value is zero. And adding one to the count value for each time of arbitration, determining an arbitration mechanism corresponding to the next time of arbitration according to the count value and the configurable order, and zeroing the count value after the arbitration is successful. In performing arbitration, the arb_req_x arbitration request signal of the corresponding arbitration method is pulled up according to the set value of the register arb_seq and the result of the Comparator. For example, when the register arb_seq is configured to 3' B001, the arbitration chain is a-B-C in order, and the arbitration count is performed by the counter. Then the arb_req_a arbitration request signal is pulled high when arb_seq equals 3' b001 and the counter value equals 0. Here both "equal" determination operations require comparators to perform. Similarly, the conditions for pulling the arb_req_b arbitration request signal high are: when arb_seq equals 3' b001 and the counter value equals 1. And if the arbitration fails, the arb_x_fail signal is used for enabling to indicate that the counter is increased by one, and the arbitration method corresponding to the next arbitration is determined according to the count value and the preset sequence. If the arbitration is successful, the arbitration result is output through the arb_x_result, and the counter is cleared.

In an embodiment, the method for arbitrating memory based on AXI protocol of the present disclosure further includes performing protocol conversion on the granted request according to the arbitration result, so as to access the memory based on the granted request after protocol conversion.

It should be noted that, the protection scope of the memory arbitration method based on AXI protocol according to the embodiments of the present disclosure is not limited to the order of execution of the steps listed in the embodiments, and all the schemes implemented by adding or removing steps and replacing steps according to the prior art according to the principles of the present disclosure are included in the protection scope of the present disclosure.

In several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, or method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules/units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or units may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules or units, which may be in electrical, mechanical or other forms.

The modules/units illustrated as separate components may or may not be physically separate, and components shown as modules/units may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules/units may be selected according to actual needs to achieve the objectives of the embodiments of the present disclosure. For example, functional modules/units in various embodiments of the present disclosure may be integrated into one processing module, or each module/unit may exist alone physically, or two or more modules/units may be integrated into one module/unit.

Those of ordinary skill would further appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Embodiments of the present disclosure also provide a computer-readable storage medium. Those of ordinary skill in the art will appreciate that all or part of the steps in implementing the AXI protocol-based memory arbitration method of the above embodiments may be performed by a program that may be stored in a computer readable storage medium, such as a non-transitory (non-transitory) medium, for example, a random access memory, a read-only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape (tape), a floppy disk (floppy disk), an optical disk (optical disk), and any combination thereof. The storage media may be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The embodiment of the disclosure also provides electronic equipment. The electronic device includes a processor and a memory.

The memory is used for storing a computer program. The memory may include: various media capable of storing program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.

The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the electronic equipment to execute the memory arbitration method based on the AXI protocol. In some embodiments, the processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), and the like. In other embodiments, the processor may also be a digital signal processor (Digital Signal Processor, DSP for short), application specific integrated circuit (Application Specific Integrated Circuit, ASIC for short), field programmable gate array (Field Programmable Gate Array, FPGA for short), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.

As shown in fig. 5, the electronic device of the present disclosure is embodied in the form of a general purpose computing device. Components of an electronic device may include, but are not limited to: one or more processors or processing units 51, a memory 52, a bus 53 that connects the various system components, including the memory 52 and the processing unit 51.

Bus 53 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, micro channel architecture (MAC) bus, enhanced ISA bus, video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

Electronic devices typically include a variety of computer system readable media. Such media can be any available media that can be accessed by the electronic device and includes both volatile and nonvolatile media, removable and non-removable media.

Memory 52 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 521 and/or cache memory 522. The electronic device may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 523 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, commonly referred to as a "hard disk drive"). Although not shown in fig. 5, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be coupled to bus 53 through one or more data medium interfaces. Memory 52 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the various embodiments of the disclosure.

A program/utility 524 having a set (at least one) of program modules 5241 may be stored in, for example, memory 52, such program modules 5241 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 5241 generally perform the functions and/or methods in the embodiments described in this disclosure.

The electronic device may also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), with one or more devices that enable a user to interact with the electronic device, and/or with any device (e.g., network card, modem, etc.) that enables the memory controller chip to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 54. And, the electronic device may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through the network adapter 55. As shown in fig. 5, the network adapter 55 communicates with other modules of the electronic device over the bus 53. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with an electronic device, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

FIG. 6 is a schematic diagram of a memory controller according to an embodiment of the disclosure. As shown in fig. 6, the memory controller includes the above-described AXI protocol-based memory arbitration means 61 and registers 62.

The register 62 is configured to store configuration information corresponding to a concatenation order of the plurality of arbitration mechanisms.

The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.

Claims

1. A memory arbitration device based on AXI protocol, comprising:

an arbitration module comprising an arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order; and

a receiving module configured to receive an AXI read request and/or an AXI write request and to input the AXI read request and/or the AXI write request into the arbitration chain of the arbitration module,

wherein the arbitration module is configured to arbitrate the AXI read requests and/or the AXI write requests based on the plurality of arbitration mechanisms of the arbitration chain to output granted requests.

2. The apparatus of claim 1, wherein the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method.

3. The apparatus of claim 1, wherein the configurable order is determined by configuration information of registers, different configuration information corresponding to different concatenation orders of the plurality of arbitration mechanisms.

4. The apparatus of claim 1, wherein the receiving means comprises:

a caching module configured to receive and cache at least one of said AXI read requests and/or at least one of said AXI write requests; and

an input module configured to input at least one of the AXI read requests and/or at least one of the AXI write requests simultaneously into the arbitration chain.

5. The apparatus of claim 1, wherein the arbitration module is configured to:

arbitrating the AXI read request and/or the AXI write request by adopting an arbitration mechanism positioned at a first stage in the arbitration chain;

if the arbitration is successful, outputting the authorized AXI read request and/or the AXI write request based on an arbitration result;

if the arbitration fails, adopting an arbitration mechanism positioned at the next stage in the arbitration chain to arbitrate the AXI read request and/or the AXI write request until the arbitration is successful.

6. The apparatus of claim 5, further comprising a counter having an initial count value of zero, the counter configured to:

adding one to the count value for each time of arbitration so as to determine an arbitration mechanism corresponding to the next arbitration according to the count value and the configurable order; and

the count value is zeroed after arbitration is successful.

7. The apparatus of claim 1, further comprising a protocol conversion module configured to receive the authorized request, and to protocol convert the authorized request to access memory based on the protocol-converted authorized request.

8. A memory arbitration method based on AXI protocol, applied to a memory controller, characterized in that the method comprises:

inputting a received AXI read request and/or AXI write request into an arbitration chain, the arbitration chain comprising a plurality of arbitration mechanisms cascaded in a configurable order; and

the AXI read requests and/or the AXI write requests are arbitrated based on the plurality of arbitration mechanisms of the arbitration chain to output granted requests.

9. The method of claim 8, wherein the plurality of arbitration mechanisms includes a fixed host priority arbitration method, an access memory address arbitration method, and a read-write polling arbitration method.

10. The method as recited in claim 8, further comprising:

the configurable order is determined by setting configuration information for registers in the memory controller, different configuration information corresponding to different concatenation orders for the plurality of arbitration mechanisms.

11. The method of claim 8, wherein inputting the received AXI read request and/or AXI write request into the arbitration chain comprises:

receiving and caching at least one AXI read request and/or at least one AXI write request; and

at least one of the AXI read requests and/or at least one of the AXI write requests is entered into the arbitration chain simultaneously.

12. The method of claim 8, wherein arbitrating the AXI read request and/or the AXI write request based on the plurality of arbitration mechanisms of the arbitration chain to output a granted request comprises:

13. The method as recited in claim 12, further comprising:

setting a counter, wherein the initial count value of the counter is zero;

the count value is zeroed after arbitration is successful.

14. The method as recited in claim 8, further comprising:

and carrying out protocol conversion on the authorized request so as to access the memory based on the authorized request after protocol conversion.

15. A memory controller, comprising:

the AXI protocol based memory arbitration device of any one of claims 1 to 7; and

a register configured to store configuration information corresponding to a concatenation order of the plurality of arbitration mechanisms.

16. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed, implements the AXI protocol based memory arbitration method according to any one of claims 8 to 14.

17. An electronic device, comprising:

a memory configured to store a computer program; and

a processor configured to execute the computer program to cause the electronic device to perform the AXI protocol based memory arbitration method of any one of claims 8 to 14.