CN116232541A - A method and system for generating a single-carrier signal - Google Patents

Abstract

The invention relates to a single carrier signal generation method, which comprises the following steps: the off-chip processor determines a data frame structure and a time slot structure corresponding to the single carrier signal according to the single carrier signal generated by the on-chip processor; the off-chip processor generates configuration parameters corresponding to the single carrier signal and writes the configuration parameters into the shared memory; generating corresponding frame header data and communication module data according to the single carrier signal generated by the off-chip processor, and writing the frame header data and the communication module data into a shared memory; the baseband processor acquires data to be transmitted, reads configuration parameters and frame header data from the shared memory, realizes state hopping under a data transmission state machine, reads corresponding communication module data according to a communication module selection enabling switch under each hopping state, and processes the read communication module data to generate a single carrier signal. According to the technical scheme, the generation efficiency of the single carrier signal is improved, long-term maintenance is facilitated, and research, development and labor cost are saved.

Description

A method and system for generating a single carrier signal

technical field

The present invention relates to the technical field of wireless communication, in particular to a single-carrier signal generation method and system based on a baseband processor and an off-chip processor.

Background technique

At present, wireless communication technology has been widely used in scenarios such as satellite communication and mobile communication. Taking satellite communication as an example, in satellite communication of different communication systems, there are many waveforms in the physical layer of a single carrier. Different physical layer waveforms need to generate physical layer modulation waveforms according to the communication system. The modulation, demodulation and decoding methods of different satellite communication systems are different. all the same. Typically, the work of generating a single-carrier modulated signal can be done through a baseband processor.

For a communication system with a slightly slower information rate, the baseband processor can be implemented by a DSP (Digital Signal Processing, digital signal processing) chip, etc., while for a communication system with a higher information rate, the baseband processor generally uses an FPGA (Field Programmable Gate Array, Programmable Gate Array) dedicated chip to achieve.

However, the inventors of the present application found in the research that in the scenario of using an FPGA-specific chip to implement a baseband processor, due to the poor versatility of the FPGA, different codes need to be written for different physical layer systems of satellite communications to realize a single The generation of carrier modulation signal, so there are problems such as low generation efficiency of single carrier signal and difficult maintenance of software and hardware system.

Contents of the invention

In view of the above problems, the object of the present invention is to provide a method and system for generating a single-carrier signal. Based on the cooperation of the baseband processor and the off-chip processor, the baseband single-carrier modulation signal can be quickly generated for different physical layer communication systems, and the single-carrier signal can be improved. The production efficiency is high, and it is also conducive to long-term maintenance, saving R&D and labor costs.

To achieve the above object, the present invention takes the following technical solutions:

In a first aspect, the present application provides a method for generating a single carrier signal, the method comprising:

The off-chip processor determines the data frame structure and slot structure corresponding to the single carrier signal according to the single carrier signal generated by the need;

The off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and the baseband processor , the configuration parameters include the jump state and jump condition of the data transmission state machine of the baseband processor, and the communication module selection enable switch under each jump state;

The off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and the communication module data into the shared memory;

The baseband processor obtains the data to be sent, and reads the configuration parameters and the frame header data from the shared memory, realizes the state jump under the data sending state machine, and in each jump state Reading corresponding communication module data according to the communication module selection enable switch, processing the read communication module data, and generating a single carrier signal with the data frame structure and time slot structure.

In an implementation manner of the present application, the method further includes: the baseband processor reports the data transmission status information of the single carrier signal to the off-chip processor through an interrupt signal, so that the off-chip The processor verifies whether the baseband processor correctly generates the single carrier signal.

In an implementation manner of the present application, the method further includes: when the off-chip processor determines that the baseband processor has incorrectly generated a single-carrier signal, readjusting the configuration parameters and the communication module data, And write into the shared memory for the baseband processor to read and process again.

In an implementation manner of the present application, the off-chip processor determines the physical layer single-carrier signal to be generated according to the communication system selection signal sent by the host computer.

In an implementation manner of the present application, the shared memory is a dual-port RAM shared by the baseband processor and the off-chip processor, and the dual-port RAM shared by the baseband processor and the off-chip processor Each address corresponds to a jump state of the data sending state machine, and the data stored in each address is combined in bits to select an enabling switch for the communication module in the jump state.

In an implementation manner of the present application, the communication module includes interleaving, scrambling and channel coding.

In an implementation manner of the present application, the form of the single carrier includes FDD or TDD.

In an implementation manner of the present application, the pilot mode of the single carrier includes continuous pilot or distributed pilot.

In a second aspect, the present application provides a single-carrier signal generation system, including a baseband processor, an off-chip processor, and a shared memory;

The off-chip processor is used to determine the data frame structure and slot structure corresponding to the single carrier signal according to the single carrier signal generated as required;

The off-chip processor is also used to generate configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and write the configuration parameters between the off-chip processor and the baseband processor The shared memory among, described configuration parameter comprises the jump state and jump condition of the data transmission state machine of described baseband processor, and the communication module selection enabling switch under each jump state;

The off-chip processor is also used to generate corresponding frame header data and communication module data according to the single carrier signal generated as required, and write the frame header data and the communication module data into the shared memory;

The baseband processor is used to obtain the data to be sent, and read the configuration parameters and the frame header data from the shared memory, realize the state jump under the data sending state machine, and In the transition state, read the corresponding communication module data according to the communication module selection enable switch, process the read communication module data, and generate the single carrier signal of the data frame structure and time slot structure.

In an implementation manner of the present application, the baseband processor is an FPGA; the off-chip processor is a DSP, CPU or MCU off-chip of the FPGA.

Because the present invention adopts the above technical scheme, it has the following advantages: the single carrier signal generated by the off-chip processor in the application scheme of the present invention generates configuration parameters according to needs, and writes them into the shared memory, and then reads the configuration parameters by the baseband processor According to the configuration parameters, the state jump of the data transmission state machine and the processing of the module data in each state are realized to generate the required single-carrier signal. Compared with the existing technology, the fast Generate single-carrier signals of different communication systems, which improves efficiency and effectively reduces maintenance costs.

Description of drawings

FIG. 1 is a schematic structural diagram of a single carrier generation system provided by an embodiment of the present invention;

FIG. 2 is a schematic flowchart of a method for generating a single carrier provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram and a schematic signal flow diagram of a single carrier generation system provided by an embodiment of the present invention;

Fig. 4 is a schematic diagram of the processing flow of the off-chip processor in the embodiment of Fig. 3;

Fig. 5 is a schematic diagram of the processing flow of the baseband processor in the embodiment of Fig. 3;

Fig. 6 is a schematic diagram of the state jump of the transmitter state machine of the baseband processor in Fig. 3;

FIG. 7 is a schematic diagram of generation of pilots and scrambling codes in the embodiment of FIG. 3;

Fig. 8 is a schematic diagram of a data frame structure in an embodiment of the present invention;

FIG. 9 is a schematic diagram of another data frame structure in an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the following will clearly and completely describe the technical solutions of the embodiments of the present invention in conjunction with the drawings of the embodiments of the present invention. Apparently, the described embodiments are some, not all, embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention belong to the protection scope of the present invention.

In the scenario where FPGA-specific chips are used to implement baseband processors in the existing technology, due to the poor versatility of FPGA, different codes need to be written for different physical layer systems of satellite communications to realize the generation of single-carrier modulation signals, so there are In view of the low efficiency of single-carrier signal generation and difficult maintenance of software and hardware systems, this application provides a single-carrier signal generation method and system based on a baseband processor and an off-chip processor, including: a single-carrier signal generated by the off-chip processor as needed Carrier signal, determine the data frame structure and slot structure corresponding to the single carrier signal; the off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and slot structure, and configures Parameters are written into the shared memory between the off-chip processor and the baseband processor, and the configuration parameters include the jump state and the jump condition of the data sending state machine of the baseband processor, and each jump state The communication module selection enable switch; the off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated by the need, and writes the frame header data and the communication module data into the shared memory; the baseband processor obtains the data to be sent, and reads the configuration parameters and the frame header data from the shared memory, realizes the state jump under the data sending state machine, and at each jump state, read the corresponding communication module data according to the communication module selection enable switch, process the read communication module data, and generate the single carrier signal of the data frame structure and time slot structure. The technical solution of the present application can improve the generation efficiency of the single-carrier signal, is also beneficial to long-term maintenance, and saves research and development and labor costs.

As mentioned in the background art, in satellite communication systems carrying different systems, the modulation, demodulation and codec methods of various satellite communication systems are not the same. Generally, modulation and demodulation in a communication system with a slightly slower communication rate can be implemented on chips such as DSP or CPU, and for a communication system with a higher communication aluminum plating, it can be implemented on an FPGA. However, the general performance of the system implemented by FPGA is poor, and it cannot make good use of a unified hardware platform and software code to realize the physical layer single-carrier waveform under different communication systems.

In order to overcome the above defects, in the technical solution of this application, a unified hardware platform will be provided, which can quickly realize the generation of physical layer single carrier for different satellite communication systems, without the need for the baseband processor implemented by the existing FPGA. The program code is modified to reduce maintenance costs.

As shown in FIG. 1 , an embodiment of the present application provides a system for generating a single-carrier signal. The single carrier signal generating system can be used as a unified hardware platform for generating physical layer single carriers under different communication systems.

Specifically, the single-carrier signal generating system in the embodiment of FIG. 1 includes: a baseband processor 101 , an off-chip processor 102 and a shared memory 103 .

Among them, the baseband processor 101 can be various chips with digital signal storage, transmission and calculation processing functions, such as DSP, CPU, etc. Of course, in the scenario where the data transmission rate is relatively high, the baseband processor 101 It may preferably be an FPGA dedicated chip. In the subsequent embodiments of the present application, the baseband processor 101 will take FPGA as an example.

The off-chip processor 102 is an off-chip processor relative to the baseband processor 101 . The off-chip processor 102 may be a chip such as DSP, CPU or MCU.

The shared memory 103 is a memory that the baseband processor 101 and the off-chip memory 102 can jointly access to write and read data. In some scenarios, the shared memory 103 may be built in the baseband processor 101 or the off-chip processor 102. For example, if the baseband processor 101 is an FPGA, the shared memory 103 may be a RAM built in the FPGA.

In the embodiment of the present application, the working principle of the single-carrier signal generating system is as follows.

Wherein, the off-chip processor 102 is configured to determine the data frame structure and the slot structure corresponding to the single carrier signal according to the generated single carrier signal.

The off-chip processor 102 is also used to generate configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and write the configuration parameters into the shared memory 103 between the off-chip processor 102 and the baseband processor 101 , the configuration parameters include the jump states and jump conditions of the data sending state machine of the baseband processor, and the communication module selection enabling switch in each jump state.

The off-chip processor 102 is also used to generate corresponding frame header data and communication module data according to the single carrier signal generated as needed, and write the frame header data and communication module data into the shared memory 103 .

The baseband processor 101 is used to obtain the data to be sent, and read configuration parameters and frame header data from the shared memory 103 to realize the state jump under the data sending state machine, and in each jump state, select according to the communication module The enable switch reads the corresponding communication module data, processes the read communication module data, and generates a single carrier signal with a data frame structure and a time slot structure.

Corresponding to the system provided in the embodiment in FIG. 1 , another aspect of the embodiment of the present application provides a method for generating a single-carrier signal applied to the system in FIG. 1 . Refer to Figure 2 for details.

As shown in FIG. 2 , an embodiment of the present application provides a method for generating a single carrier.

The method for generating a single carrier includes:

S21, the off-chip processor determines the data frame structure and slot structure corresponding to the single carrier signal according to the single carrier signal generated by the need;

Specifically, the off-chip processor can determine the physical layer single-carrier signal to be generated according to the communication system selection signal sent by the host computer.

In some more detailed embodiments of the present application, the single carrier signal may include a single carrier in the form of FDD or TDD. Pilot schemes may include continuous pilots or distributed pilots.

S22, the off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and writes the configuration parameters into the shared memory between the off-chip processor and the baseband processor, the configuration parameters including the baseband processor The jump state and jump condition of the data sending state machine, and the communication module selection enable switch in each jump state;

Specifically, in some embodiments of the present application, the shared memory is a dual-port RAM shared by the baseband processor and the off-chip processor, and each address of the dual-port RAM shared by the baseband processor and the off-chip processor corresponds to A jump state of the data sending state machine, and the data stored in each address is combined into a communication module selection enable switch in the jump state according to bits.

In the embodiment of the present application, the jump states of the data sending state machine generally include an idle state and a data sending state. Wherein, in the data sending state, the baseband processor sends the generated single-carrier data to the outside. In the data sending state, the baseband processor can send different data, such as frame header data, frame information data or channel coding data, which is controlled by the communication module selection enable switch.

In the embodiment of the present application, different processing of data may be implemented through multiple communication modules, and the communication modules may include interleaving, scrambling, or channel coding and the like.

S23, the off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and communication module data into the shared memory;

S24, the baseband processor obtains the data to be sent, and reads the configuration parameters and frame header data from the shared memory, realizes the state jump under the data sending state machine, and selects the enable switch according to the communication module in each jump state Read the corresponding communication module data, process the read communication module data, and generate a single carrier signal with a data frame structure and a time slot structure.

In the embodiment of the present application, in order to enable the baseband processor to correctly generate the required baseband signal. The method may further include:

S25, the baseband processor reports the data transmission state information of the single carrier signal to the off-chip processor through the interrupt signal, so that the off-chip processor can verify whether the baseband processor correctly generates the single carrier signal. as well as

S26. When the off-chip processor determines that the baseband processor does not correctly generate the single carrier signal, readjust configuration parameters and communication module data, and write them into the shared memory for the baseband processor to read and process again.

That is, when the off-chip processor verifies that the baseband processor fails to correctly generate single-carrier signals, it returns to execute S22-S24 until the baseband processor generates all correct single-carrier signals.

In the above-mentioned single-carrier signal generation system and method in the embodiment of the present application, the off-chip processor generates configuration parameters according to the single-carrier signal generated as needed, and writes the configuration parameters into the shared memory, and then the baseband processor reads the configuration parameters, and according to the configuration parameters Realize the state jump of the data transmission state machine and the processing of module data in each state to generate the required single carrier signal. Compared with the existing technology, different communication systems can be quickly generated without changing the hardware platform and code The single-carrier signal improves efficiency and effectively reduces maintenance costs.

The above-mentioned system and method for generating a single-carrier signal will be described below in some more detailed embodiments of the present application, and the advantages of the present application will be described.

The single carrier generation system provided by the embodiment of the present application includes a baseband processor, an off-chip processor and a shared memory.

In one embodiment of the present application, as shown in FIG. 3 , the baseband processor is an FPGA as an example. The off-chip processor is an off-chip DSP or CPU relative to the FPGA. The shared memory is a dual-port RAM built into the FPGA.

Single-carrier signal generating system in the embodiment of Fig. 3, the signal flow of its work is:

In step (1), the off-chip DSP or CPU determines the physical layer single-carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and slot structure corresponding to the single-carrier signal.

Step (2), off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA, and the configuration parameters include the data transmission status of the FPGA The jump state and jump condition of the machine, as well as the communication module selection enable switch in each jump state.

Specifically, in the system in the embodiment in FIG. 3 , the data of each communication module may be header data, pilot data, channel coding, interleaving or scrambling, and the like. In an optional scenario, more or fewer communication modules may be selected first, which will not be limited in this embodiment of the present application.

In step (3), the off-chip DSP or CPU generates the corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and communication module data into RAM.

Specifically, the frame header data is used for physical frame synchronization, and the communication module data may be scrambled data used for scrambling as an example.

In step (4), the FPGA obtains the data to be sent, and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data sending state machine, and in each jump state, select the enable switch according to the communication module to read Get the corresponding communication module data, process the read communication module data, and generate a single carrier signal corresponding to the data frame structure and slot structure.

Specifically, in the embodiment of the present application, each address of the dual-port RAM corresponds to a jump state of the data sending state machine, and the data stored at each address is combined into bits for communication in the jump state. Module selection enable switch (such as: interleaving, scrambling, channel coding and other module enabling), and corresponding configuration data of each module. According to the data frame to be generated, the FPGA determines which modules are enabled in each jump state, and configures the configuration data to the corresponding communication modules. At the same time, for each strip state, the parameter RAM address corresponding to the next state is also given to ensure that the state of the state machine jumps normally.

The data sending state machine of FPGA jumps into the next state through the state machine start enable (FPGAStartEn) configured by off-chip DSP or CPU. The state of the state machine may include an idle state and a data sending state.

Among them, in the data sending state of the FPGA state machine, frame header data, frame information data, or channel coded data can be sent. The specific sending type is determined by the sending enable of different data types configured by DSP or CPU. The amount of sent data of each data type can also be determined by the DSP or CPU configuration, and the data sending state machine can also be controlled to jump between the idle state and the sending data state, so that the FPGA sender can complete the jump according to the jump mode configured by the DSP or CPU The physical frame generation of continuous pilot and distributed pilot can also complete the frame structure generation of FDD mode and TDD mode.

For data with different data types and different modulation methods, the FPGA can be configured through the DSP or CPU according to the modulation method corresponding to the data type, and the FPGA will complete the phase mapping for the modulated data.

Step (5), FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU through an interrupt signal, so that whether the off-chip DSP or CPU correctly generates the single carrier signal is verified by the FPGA.

Step (6), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and judges whether the FPGA responds correctly according to the reported status information. If it is correct, no intervention will be made; Report information to adjust configuration parameters.

Step (7), the off-chip DSP or CPU chip judges whether the physical layer single-carrier signal is generated according to the state parameters reported by the FPGA chip, if not, repeat steps (2) to (6) until the physical layer single-carrier signal The signal is generated.

From the above steps (1) to (7), it can be seen that the processing flow of the single carrier signal generation method of the present application is a collaborative processing process in which the baseband processor (FPGA) interacts with the off-chip processor (off-chip DSP or CPU). Wherein, the processing flow of the off-chip processor is shown in FIG. 4 , and the processing flow of the baseband processor is shown in FIG. 5 .

Specifically, in FIG. 4, the processing flow of the off-chip processor, taking off-chip DSP or CPU as an example, includes:

401. The off-chip DSP or CPU judges whether it receives a communication system selection signal from the host computer.

If not, it will be in a waiting state, and if so, go to 402 .

402. The off-chip DSP or CPU generates a corresponding frame structure and slot structure.

403. The off-chip DSP or CPU generates configuration parameters of the sending state machine of the FPGA, and stores them in the shared RAM of the FPGA.

404. Set FPGAStartEn to 1 to start the FPGA modulation program.

405. Wait for the data sending status reported by the FPGA through the interrupt.

406. The off-chip DSP or CPU judges whether the sending of the data frame is completed.

If so, process and end. If not, return 405.

Correspondingly, the processing flow of the FPGA in Figure 5 includes:

The FPGA is in an idle state (Idle) in advance.

501. The FPGA determines whether FPGAStartEn is set to 1.

If yes, go to step 502; otherwise, it is in a waiting state.

502. Read the configuration parameters written into the RAM by the off-chip DSP or the CPU.

503. Generate and send a single carrier signal according to configuration parameters.

504. The FPGA judges whether the sending of the data frame is completed.

If yes, go to 505, otherwise return to 503.

505. The FPGA checks whether FPGAStartEn is set to 1.

If so, return to 502, otherwise the FPGA sending state machine enters an idle state. More specifically, in the embodiment of the present application, the jump state and jump condition of the FPGA are shown in FIG. 6 .

In the following, in one embodiment of the present application, the following specific parameters of the baseband single-carrier signal to be generated are taken as an example to illustrate the processing flow of the present application.

Specifically, the single carrier that needs to be generated is in the form of FDD, the pilot is distributed pilot mode, the length of the pilot symbol is 1024, a pilot symbol is inserted into each 15 data symbols, the pilot is modulated by BPSK, and the data symbol is QPSK Modulation, the pilot sequence generator polynomial is: f(x)=1+X+X ² +X ⁸ +X ¹² , the initial phase is: 12'b101010110011, the data part scrambling pseudo-random sequence generator polynomial is f(x)= 1+X ³ +X ²⁵ , the initial phase is: 1, the channel coding adopts LDPC coding with a code length of 2560 bits and a code rate of 1/3.

The processing flow of the system includes:

In step (A), the off-chip DSP or CPU determines the physical layer single-carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and slot structure corresponding to the single-carrier signal.

Specifically, the data frame structure in this example is shown in FIG. 8 .

Step (B), the off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA, and the configuration parameters include the data transmission status of the FPGA The jump state and jump condition of the machine, as well as the communication module selection enable switch in each jump state.

Specifically, configure the following configuration parameters: configure the length of the pilot symbol to be sent each time to 1, the length of the data symbol to be sent to 15, and configure the pilot reset after every 1024 pilots are sent. In the state of sending data symbols, configure parameters such as scrambling enable and LDPC encoding enable to be on. Then, these configuration parameters are written into the dual-port RAM shared with the DSP or CPU in the FPGA chip through the bus between the DSP or the CPU and the FPGA chip, and wait for the sending program in the FPGA chip to read.

In step (C), the off-chip DSP or CPU generates the corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and communication module data into RAM.

Specifically, the DSP or CPU chip uses the algorithm flow shown in Figure 7 to generate the frame header data for synchronization and the scrambling code data for scrambling of the physical layer frame according to the FDD waveform pilot parameters configured by the host computer, and sends The data and the scrambled data are written into the dual-port data RAM in the FPGA chip through the DSP or the bus between the CPU and the FPGA chip, and wait for the FPGA chip to read.

Step (D), the FPGA obtains the data to be sent, and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data sending state machine, and in each jump state, select the enable switch according to the communication module to read Get the corresponding communication module data, process the read communication module data, and generate a single carrier signal corresponding to the data frame structure and slot structure.

Specifically, the DSP or CPU chip modulates the pilot symbols into BPSK according to the waveform requirements, and specifically maps 0 to (X:0x81, Y:0x00) and 1 to (X:0x7F, Y:0x00). The data symbol is modulated into QPSK, specifically, 00 is mapped to (X:0xA6, Y:0xA6), 01 is mapped to (X:0x5A, Y:0xA6), 10 is mapped to (X:0xA6, Y:0x5A), and 11 is mapped to (X: 0x5A, Y: 0x5A), and then the mapped value is written into the dual-port mapping data RAM in the FPGA chip through the DSP or the bus between the CPU and the FPGA chip.

Read the configuration parameter RAM of the DSP or CPU chip in the FPGA chip, turn on the scrambling enable and LDPC encoding enable according to the length of the pilot symbol sent each time, the length of the data symbol, and each general state parameter, and according to the general state machine The jump address of the FDD cyclically jumps between the status address of sending pilot symbols and sending data symbols, and at the same time reads the mapping value in the mapping data RAM according to the mapping relationship between pilot symbols and data symbols to complete the generation and mapping of FDD waveform data.

In step (E), the FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU through an interrupt signal, so that the off-chip DSP or CPU can verify whether the FPGA correctly generates the single carrier signal.

Specifically, the FPGA chip reports parameters such as the state value of the state machine in the sending program, the count value of the sent data symbol to the DSP and the CPU chip through an interrupt, and the time of the sending interrupt is the moment when the sent symbol counter is 1.

Step (F), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and judges whether the FPGA responds correctly according to the reported status information. If it is correct, no intervention will be made; Report information to adjust configuration parameters.

Step (G), the off-chip DSP or CPU chip judges whether the physical layer single-carrier signal is generated according to the state parameters reported by the FPGA chip. If the generation is not completed, repeat steps (B) to (F) until the physical layer single-carrier signal The signal is generated.

In another embodiment of the present application, the following specific parameters of the baseband single-carrier signal to be generated are taken as an example to illustrate the processing flow of the present application.

Among them, the baseband waveform to be generated is in the form of TDD, the time guard interval is 1ms, the pilot is continuous pilot, the pilot symbol length is 2048, the pilot adopts BPSK modulation, the data symbol length of a superframe is 16384, and QPSK modulation is adopted , the pilot sequence generator polynomial is: f(x)=1+X+X ² +X ¹⁰ +X ¹³ , the initial phase is: 13'b1110001110101, and the channel coding adopts Viterb coding with code length (2,1,9) . Baseband waveforms can be quickly generated by following the steps below.

The processing flow of the system includes:

In step (a), the off-chip DSP or CPU determines the physical layer single-carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and slot structure corresponding to the single-carrier signal.

Specifically, the data frame structure in this example is shown in FIG. 9 .

Step (b), the off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA, and the configuration parameters include the data transmission status of the FPGA The jump state and jump condition of the machine, as well as the communication module selection enable switch in each jump state.

Specifically, configure the following configuration parameters: configure the length of the pilot symbol to be 2048, configure the length of the data symbol to be 16384, and configure the reset of the pilot after continuously sending 2048 pilots. In the state of sending data symbols, set parameters such as (2,1,9) Viterb encoding enable to open state. Then, the configuration parameters are written into the shared parameter configuration dual-port RAM with the DSP or CPU in the FPGA chip through the bus between the DSP or the CPU and the FPGA chip, and wait for the sending program in the FPGA chip to read.

In step (c), the off-chip DSP or CPU generates the corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and communication module data into RAM.

Specifically, according to the TDD waveform pilot parameters configured by the host computer, the DSP or CPU chip uses Figure 7 to generate the header data of the physical layer frame for synchronization and the scrambling data for scrambling, and the frame header data and the scrambling data Write it into the dual-port data RAM in the FPGA chip through the DSP or the bus between the CPU and the FPGA chip, and wait for the FPGA chip to read it.

In step (d), the FPGA obtains the data to be sent, and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data sending state machine, and in each jump state, select the enable switch according to the communication module to read Get the corresponding communication module data, process the read communication module data, and generate a single carrier signal corresponding to the data frame structure and slot structure.

Specifically, the DSP or CPU chip modulates the pilot symbols into BPSK according to the waveform requirements, and specifically maps 0 to (X:0x81, Y:0x00) and 1 to (X:0x7F, Y:0x00). The data symbol is modulated into QPSK, specifically, 00 is mapped to (X:0xA6, Y:0xA6), 01 is mapped to (X:0x5A, Y:0xA6), 10 is mapped to (X:0xA6, Y:0x5A), and 11 is mapped to (X: 0x5A, Y: 0x5A), and then the mapped value is written into the dual-port mapping data RAM in the FPGA chip through the DSP or the bus between the CPU and the FPGA chip.

Read the parameter RAM configured by the DSP and the CPU chip in the FPGA chip, enable the (2,1,9) Viterb encoding according to the length of the pilot symbol sent each time, the length of the data symbol, and each general state parameter, and jump according to the state The transfer address cyclically jumps between sending pilot symbols, sending data symbols and time guard interval status addresses, and at the same time reads the mapping value in the mapping data RAM according to the mapping relationship between pilot symbols and data symbols to complete the generation and mapping of TDD waveform data .

In step (e), the FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU through an interrupt signal, so that the off-chip DSP or CPU can verify whether the FPGA correctly generates the single carrier signal.

Specifically, the FPGA chip reports parameters such as the state value of the state machine in the sending program, the count value of the sent data symbol to the DSP and the CPU chip through an interrupt, and the time of the sending interrupt is when the sending symbol counter is 128.

Step (f), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and judges whether the FPGA responds correctly according to the reported status information. If it is correct, it will not intervene. Report information to adjust configuration parameters.

In step (g), the off-chip DSP or CPU chip judges whether the physical layer single-carrier signal is generated according to the state parameters reported by the FPGA chip. If the generation is not completed, repeat steps (b) to (f) until the physical layer single-carrier signal The signal is generated.

To sum up, in some embodiments of the present application, it has been explained how the unified hardware platform provided can quickly generate the required single-carrier signal, and the technical solution of the present application has , can quickly generate single-carrier waveforms of different systems under the configuration of an external DSP or CPU, which saves a lot of waveform generation and development time, and can effectively reduce the work of system maintenance personnel.

It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and/or combinations thereof.

Claims (10)

1. A method of generating a single carrier signal, the method comprising:

the off-chip processor determines a data frame structure and a time slot structure corresponding to the single carrier signal according to the single carrier signal generated by the on-chip processor;

the off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and a baseband processor, wherein the configuration parameters comprise a jump state and jump conditions of a data transmission state machine of the baseband processor, and a communication module selection enabling switch in each jump state;

the off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as required, and writes the frame header data and the communication module data into the shared memory;

the baseband processor acquires data to be transmitted, reads the configuration parameters and the frame header data from the shared memory, realizes state skip under the data transmission state machine, reads corresponding communication module data according to the communication module selection enabling switch under each skip state, and processes the read communication module data to generate a single carrier signal of the data frame structure and the time slot structure.

2. The single carrier signal generation method of claim 1, wherein the method further comprises: and the baseband processor reports the data transmission state information of the single carrier signal to the off-chip processor through an interrupt signal so that the off-chip processor can verify whether the baseband processor correctly generates the single carrier signal.

3. The single carrier signal generation method of claim 2, wherein the method further comprises: and when the off-chip processor determines that the baseband processor does not generate the single carrier signal correctly, readjusting the configuration parameters and the communication module data, and writing the configuration parameters and the communication module data into the shared memory for the baseband processor to read and process again.

4. The method of generating a single carrier signal according to claim 1, wherein the off-chip processor determines a physical layer single carrier signal to be generated according to a communication system selection signal transmitted from an upper computer.

5. The method of generating a single carrier signal according to claim 1, wherein the shared memory is a dual port RAM shared by the baseband processor and the off-chip processor, each address of the dual port RAM shared by the baseband processor and the off-chip processor corresponds to a skip state of the data transmission state machine, and data stored in each address is combined into a communication module selection enable switch in the skip state by bits.

6. The method of generating a single carrier signal as claimed in claim 5, wherein the communication module comprises interleaving, scrambling, and channel coding.

7. The single carrier signal generation method of claim 1, wherein the single carrier form comprises FDD or TDD.

8. The method of generating a single carrier signal according to claim 1, wherein the pilot pattern of the single carrier includes a continuous pilot or a distributed pilot.

9. The single carrier signal generating system is characterized by comprising a baseband processor, an off-chip processor and a shared memory;

the off-chip processor is used for determining a data frame structure and a time slot structure corresponding to the single carrier signal according to the single carrier signal generated as required;

the off-chip processor is further configured to generate configuration parameters corresponding to the single carrier signal according to the data frame structure and the slot structure, and write the configuration parameters into a shared memory between the off-chip processor and a baseband processor, where the configuration parameters include a skip state and skip conditions of a data transmission state machine of the baseband processor, and a communication module selection enabling switch in each skip state;

the off-chip processor is further configured to generate corresponding frame header data and communication module data according to a single carrier signal generated as needed, and write the frame header data and the communication module data into the shared memory;

the baseband processor is configured to obtain data to be transmitted, read the configuration parameters and the frame header data from the shared memory, implement state hopping under the data transmission state machine, and in each hopping state, read corresponding communication module data according to the communication module selection enabling switch, and process the read communication module data to generate a single carrier signal of the data frame structure and the time slot structure.

10. The single carrier generation system of claim 9, wherein the baseband processor is an FPGA; the off-chip processor is a DSP, a CPU or an MCU outside the FPGA chip.

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