CN116234300A - Dynamic memory cell and dynamic memory device - Google Patents
Dynamic memory cell and dynamic memory device Download PDFInfo
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- 230000005669 field effect Effects 0.000 claims abstract description 59
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
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Abstract
The embodiment of the application provides a dynamic memory cell and a dynamic memory device. The dynamic storage device includes: a substrate; the first field effect transistor is arranged on one side of the substrate; the second field effect tube is arranged on one side of the first field effect tube; the first field effect transistor comprises a first grid electrode, a first insulating layer and a first metal oxide semiconductor layer which are sequentially arranged from inside to outside, wherein the first metal oxide semiconductor layer surrounds the first grid electrode; the second field effect transistor comprises a second source electrode, a second drain electrode, a second metal oxide semiconductor layer, a second insulating layer and a second grid electrode, wherein the second grid electrode is basically vertical to the second metal oxide semiconductor layer. In the embodiment of the application, two field effect transistors are adopted to form a dynamic memory unit, one semiconductor layer surrounds the grid electrode, and the other grid electrode is basically vertical to the semiconductor layer. The minimum area of the dynamic memory cell is 4F 2 . Therefore, the cell area is reduced, the cell density is improved, and the miniaturization, the light weight and the integration are facilitated.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to a dynamic storage unit and a dynamic storage device.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) is the largest sub-division of the memory market. Meanwhile, as the demands of products such as servers, smart phones, personal computers and the like for dynamic memories are increased, the semiconductor products are expected to have a new super growth period.
From the structural point of view, the memory cell of the dynamic memory is composed of a capacitor and a field-effect transistor (MOS). The capacitor is used for storing charge, the field effect transistor is used for accessing the capacitor, and the capacitor can read the stored charge and store new charge. However, with the development of miniaturization and integration, the disadvantage of larger dynamic memory cell area is also exposed. High density memory is becoming an increasingly important part of cache memory.
In summary, the dynamic memory in the prior art has the technical problems that the memory cell area is larger, the density of the memory cells is insufficient, and the memory device is unfavorable for light weight and thin and integration.
Disclosure of Invention
The application aims at the defects of the prior art and provides a dynamic memory unit and a dynamic memory device, which are used for solving the technical problems that the dynamic memory in the prior art has larger memory unit area and insufficient density of the memory unit, and is unfavorable for the thinning and integration of the memory device.
In a first aspect, embodiments of the present application provide a dynamic memory cell, including:
a substrate;
the first field effect transistor is arranged on one side of the substrate;
the second field effect tube is arranged on one side, far away from the substrate, of the first field effect tube;
the first field effect transistor comprises a first grid electrode, a first insulating layer and a first metal oxide semiconductor layer which are sequentially arranged from inside to outside, wherein the first insulating layer surrounds the first grid electrode, the first metal oxide semiconductor layer surrounds the first insulating layer, and the first metal oxide semiconductor layer is basically vertical to the substrate;
the second field effect transistor comprises a second source electrode, a second drain electrode, a second metal oxide semiconductor layer, a second insulating layer and a second grid electrode, wherein the second source electrode is connected with the first grid electrode, the second drain electrode is positioned on one side, far away from the first grid electrode, of the second source electrode, the second metal oxide semiconductor layer is arranged between the second source electrode and the second drain electrode, the second insulating layer is an encircling structure arranged between the second source electrode and the second drain electrode, and the second grid electrode penetrates through the second insulating layer and is basically perpendicular to the second metal oxide semiconductor layer.
In some embodiments of the present application, the first field effect transistor further includes a first source and a first drain, the first source and the first drain surrounding the first metal oxide semiconductor layer, respectively.
In some embodiments of the present application, the first source is located on a side of the substrate, and the first drain is located on a side of the first source away from the substrate; alternatively, the first drain electrode is located at a side of the substrate, and the first source electrode is located at a side of the first drain electrode away from the substrate.
In some embodiments of the present application, the first field effect transistor further includes a first word line electrically connected to the first source and a first bit line electrically connected to the first drain.
In some embodiments of the present application, the first word line and the first bit line are perpendicular to each other.
In some embodiments of the present application, the second metal oxide semiconductor is in contact with the second insulating layer portion, and an orthographic projection of the second metal oxide semiconductor layer on the substrate and an orthographic projection of the second insulating layer on the substrate do not coincide with each other.
In some embodiments of the present application, the second field effect transistor further includes a second word line electrically connected to the second gate and a second bit line electrically connected to the second drain.
In some embodiments of the present application, the second word line and the second bit line are perpendicular to each other.
In some embodiments of the present application, the first fet is a read fet and the second fet is a write fet; alternatively, the first field effect transistor is a writing field effect transistor, and the second field effect transistor is a reading field effect transistor.
In some embodiments of the present application, the material of at least one of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprises ITO, IWO, or IGZO.
In some embodiments of the present application, further comprising a first word line, a first bit line, a second word line, and a second bit line, the material of at least one of the first word line, the first bit line, the second word line, and the second bit line comprises tungsten.
Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a dynamic storage device, where the dynamic storage device includes a dynamic storage unit in any one of the embodiments of the first aspect.
The beneficial technical effects that technical scheme that this application embodiment provided brought include: in the embodiment of the application, an upper field effect transistor and a lower field effect transistor which are respectively responsible for reading and writing are adopted to form a dynamic memory unit, the grid electrode of one field effect transistor is basically vertical to the substrate, the metal oxide semiconductor layer surrounds the grid electrode, and the grid electrode of the other field effect transistor is basically vertical to the metal oxide semiconductor layer. The cell using the design has very small occupied area, when the line width of the signal line is the Feature Size (F), a plurality of dynamic memory cells form an array, the signal line spacing of the same layer in two adjacent dynamic memory cells is 1F, and the minimum area of the dynamic memory cells is 4F 2 . Therefore, the area of a single dynamic memory unit is reduced, the density of the dynamic memory units in the dynamic memory device is improved, and the miniaturization, the light weight and the integration of the dynamic memory device are facilitated. Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a dynamic memory cell according to an embodiment of the present application.
In the figure:
1-substrate, 2-first field effect transistor, 3-second field effect transistor;
21-first gate, 22-first insulating layer, 23-first metal oxide semiconductor layer, 24-first source, 25-first drain, 26-first word line, 27-first bit line;
31-second source, 32-second drain, 33-second metal oxide semiconductor layer, 34-second insulating layer, 35-second gate, 36-second word line, 37-second bit line.
Detailed Description
Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
Research shows that the dynamic memory in the prior art has the technical problems that the area of the memory cells is large, the density of the memory cells is insufficient, and the memory device is unfavorable for lightening and thinning and integrating.
The application provides a dynamic memory cell and a dynamic memory device, which aim to solve the technical problems in the prior art. The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments.
In a first aspect, embodiments of the present application provide a dynamic memory cell. Referring to fig. 1, fig. 1 is a schematic structural diagram of a dynamic memory cell according to an embodiment of the present application. The dynamic memory unit comprises a substrate 1, a first field effect transistor 2 and a second field effect transistor 3.
A first field effect transistor 2 disposed on one side of the substrate 1;
the second field effect tube 3 is arranged on one side of the first field effect tube 2 away from the substrate 1;
the first field effect transistor 2 comprises a first gate electrode 21, a first insulating layer 22 and a first metal oxide semiconductor layer 23 which are sequentially arranged from inside to outside, wherein the first insulating layer 22 surrounds the first gate electrode 21, the first metal oxide semiconductor layer 23 surrounds the first insulating layer 22, and the first metal oxide semiconductor layer 23 is perpendicular to the substrate 1;
the second field effect transistor 3 includes a second source 31, a second drain 32, a second metal oxide semiconductor layer 33, a second insulating layer 34, and a second gate 35, where the second source 31 is connected to the first gate 21, the second drain 32 is located at a side of the second source 31 away from the first gate 21, the second metal oxide semiconductor layer 33 is disposed between the second source 31 and the second drain 32, the second insulating layer 34 is a surrounding structure disposed between the second source 31 and the second drain 32, and the second gate 35 passes through the second insulating layer 34 and is perpendicular to the second metal oxide semiconductor layer 33.
In other embodiments of the present application, the first metal oxide semiconductor layer 23 is not absolutely perpendicular to the substrate 1, and the first metal oxide semiconductor layer 23 is substantially perpendicular to the substrate 1. It is understood that "substantially perpendicular" means that the plane in which the first metal oxide semiconductor layer 23 is located forms a first included angle with the plane in which the substrate 1 is located, and the first included angle is not less than 70 degrees and less than 90 degrees, which still meets the requirements of the present embodiment, and is within the scope of protection of the present application.
In further embodiments of the present application, the second gate electrode 35 is not absolutely perpendicular to the second metal oxide semiconductor layer 33, and the second gate electrode 35 is substantially perpendicular to the second metal oxide semiconductor layer 33. It is understood that "substantially perpendicular" means that the plane in which the second gate electrode 35 is located forms a second included angle with the plane in which the second metal oxide semiconductor layer 33 is located, and the second included angle is not less than 70 degrees and less than 90 degrees, which still meets the requirements of the present embodiment, and is within the scope of protection of the present application.
In the embodiment of the application, an upper field effect transistor and a lower field effect transistor which are respectively responsible for reading and writing are adopted to form a dynamic memory unit, the grid electrode of one field effect transistor is perpendicular to the substrate 1, the metal oxide semiconductor layer surrounds the grid electrode, and the grid electrode of the other field effect transistor is perpendicular to the metal oxide semiconductor layer. The cell using the design has very small occupied area, when the line width of the signal line is the Feature Size (F), a plurality of dynamic memory cells form an array, the signal line spacing of the same layer in two adjacent dynamic memory cells is 1F, and the minimum area of the dynamic memory cells is 4F 2 . Therefore, the area of a single dynamic memory unit is reduced, the density of the dynamic memory units in the dynamic memory device is improved, and the miniaturization, the light weight and the integration of the dynamic memory device are facilitated.
In the present embodiment, the first insulating layer 22 surrounds the first gate electrode 21, and the first metal oxide semiconductor layer 23 surrounds the first insulating layer 22. At least one of the first gate electrode 21, the first insulating layer 22, and the first metal oxide semiconductor layer 23 is perpendicular to the substrate 1.
In a specific embodiment, any two of the first gate electrode 21, the first insulating layer 22, and the first metal oxide semiconductor layer 23 are parallel to each other. The first gate electrode 21, the first insulating layer 22, and the first metal oxide semiconductor layer 23 are all perpendicular to the substrate 1.
In the present embodiment, when no external voltage is applied to the first gate electrode 21, free electrons or holes in the first metal oxide semiconductor layer 23 are in a state where no movement is required, and the conductivity of the first metal oxide semiconductor layer 23 is extremely low or in an insulating state. When an external voltage is applied to the first gate electrode 21, a potential difference exists between the first metal oxide semiconductor layer 23 and the first gate electrode 21, and free electrons or holes are accumulated in the first metal oxide semiconductor layer 23 due to the first insulating layer 22 being provided therebetween and not being conductive. When the applied external voltage is greater than or equal to the threshold voltage, free electrons or holes move directionally to turn on the first metal oxide semiconductor layer 23 to form a current.
When the first insulating layer 22 surrounds the first gate electrode 21, the first metal oxide semiconductor layer 23 surrounds the first insulating layer 22, and the first insulating layer 22 and the first metal oxide semiconductor layer 23 form an enclosing structure. In one embodiment, the top plan view contours of both form a closed circular pattern; in another embodiment, the top plan view contours of both form a closed rectangular pattern; in yet another embodiment, the top view profile of one is a closed rectangular pattern, the top view profile of one is a closed circular pattern, the first insulating layer 22 may be a rectangular pattern, the first metal oxide semiconductor layer 23 may be a circular pattern, the first insulating layer 22 may be a circular pattern, and the first metal oxide semiconductor layer 23 may be a rectangular pattern.
In this embodiment, the first metal oxide semiconductor layer 23 surrounds the first gate electrode 21, so that not only the plurality of dynamic memory cells are closely arranged when forming an array, but also the channel current in the dynamic memory cells can be uniform along the radial direction. Under the condition of the same occupied area, the area of the current channel is widened, so that the saturation current can be increased. The width of the annular channel region is consistent, so that the doping concentrations of the source electrode and the drain electrode are consistent, the threshold voltages among different memory cells are consistent, and the processing difficulty and the operation difficulty are reduced.
In some embodiments of the present application, the first field effect transistor 2 further includes a first source 24 and a first drain 25, and the first source 24 and the first drain 25 respectively surround the first metal oxide semiconductor layer 23.
In the present embodiment, the first source electrode 24 and the first drain electrode 25 are at different heights of the first metal oxide semiconductor layer 23. The first source electrode 24 and the first drain electrode 25 surround different portions of the first metal oxide semiconductor layer 23, respectively. The top view profile of the first source 24, the first drain 25 is a closed rectangular pattern or a closed circular pattern.
In some embodiments of the present application, the first source 24 is located on a side of the substrate 1, and the first drain 25 is located on a side of the first source 24 remote from the substrate 1.
In other embodiments, the first drain electrode 25 is located on a side of the substrate 1, and the first source electrode 24 is located on a side of the first drain electrode 25 remote from the substrate 1.
In the embodiment of the present application, the first field effect transistor 2 further includes a first word line 26 and a first bit line 27, where the first word line 26 and the first bit line 27 are electrically connected to the first source 24 and the first drain 25, respectively.
In one embodiment, the first word line 26 is electrically connected to the first source 24, and the first bit line 27 is electrically connected to the first drain 25.
In another embodiment, the first word line 26 is electrically connected to the first drain electrode 25, and the first word line 26 is electrically connected to the first source electrode 24.
In yet another embodiment, the first word line 26 is electrically connected to two opposite sides of the first source 24 or the first drain 25, and the first bit line 27 is electrically connected to two opposite sides of the first drain 25 or the first source 24. In the same dynamic memory cell, the first word line 26 and the first bit line 27 are each divided into two collinear line segments.
In one particular embodiment, first word line 26 and first bit line 27 are parallel to each other; in another embodiment, the first word line 26 and the first bit line 27 are perpendicular to each other.
In yet another embodiment, the first word line 26 is electrically connected to two sides of the first source 24 or the first drain 25, and the first bit line 27 is electrically connected to two sides of the first drain 25 or the first source 24. In the same dynamic memory cell, the first word line 26 and the first bit line 27 are each divided into two perpendicular line segments.
In the present embodiment, at least one of the first source 24, the first drain 25, the first word line 26, and the first bit line 27 is parallel to the substrate 1. In a specific embodiment, any two of the first source 24, the first drain 25, the first word line 26, and the first bit line 27 are parallel to each other, and the first source 24, the first drain 25, the first word line 26, and the first bit line 27 are perpendicular to the first gate 21. The first grid electrode 21 is perpendicular to the substrate 1, so that the dynamic memory cells are arranged closely when forming an array, and the occupied area of the dynamic memory cells is reduced.
In this embodiment, the first word line 26 is perpendicular to the first bit line 27. Specifically, when a plurality of dynamic memory cells are formed into an array, the planes of the first word lines 26 are parallel to the planes of the first bit lines 27, the first bit lines 27 of two adjacent dynamic memory cells in the first direction are communicated and collinear, the first word lines 26 of two adjacent dynamic memory cells are parallel to each other, and the space between the adjacent first word lines 26 is also 1F; similarly, the first direction is perpendicular to the second direction, and adjacent first bit lines 27 are parallel in the second direction with a pitch of 1F, and adjacent first word lines 26 are connected and collinear, so that the minimum area of one first FET 2 is 4F 2 。
In the embodiment of the present application, the second field effect transistor 3 further includes a second source 31 and a second drain 32, where the second source 31 is connected to the first gate 21 and the second drain 32, respectively, and the connection includes direct connection and indirect connection, where the second source 31 is collinear with the second drain 32.
In some embodiments of the present application, the second field effect transistor 3 further includes a second insulating layer 34 and a second metal oxide semiconductor layer 33, where the second metal oxide semiconductor layer 33 and the second insulating layer 34 are disposed between the second source electrode 31 and the second drain electrode 32, the second metal oxide semiconductor layer 33 is perpendicular to the substrate 1 and communicates with the second source electrode 31 and the second drain electrode 32, and the second source electrode 31 is indirectly connected to the second drain electrode 32 through the second metal oxide semiconductor layer 33.
In one embodiment, the second source 31 is directly connected to the second drain 32 or the first gate 21. In another embodiment, the second source 31 may also be indirectly connected to the second drain 32 or the first gate 21 through other conductors.
In some embodiments of the present application, the second metal oxide semiconductor is in partial contact with the second insulating layer 34, and the orthographic projection of the second metal oxide semiconductor layer 33 on the substrate 1 and the orthographic projection of the second insulating layer 34 on the substrate 1 do not coincide with each other.
In the present embodiment, at least part of the second insulating layer 34 and at least part of the second metal oxide semiconductor layer 33 are located between the second source electrode 31 and the second drain electrode 32. The second source electrode 31 is indirectly connected to the second drain electrode 32 through the second mos layer 33 to form a via. The orthographic projection area of the second metal oxide semiconductor layer 33 on the substrate 1 is smaller than the orthographic projection area of the second source electrode 31 or the second drain electrode 32 on the substrate 1, and the orthographic projection partial area of the second source electrode 31 and the second drain electrode 32 on the substrate 1 is located outside the orthographic projection of the second metal oxide semiconductor layer 33 on the substrate 1, and the partial area is covered by the orthographic projection of the second insulating layer 34 on the substrate 1. The second insulating layer 34 forms an enclosing structure and the second insulating layer 34 is simultaneously in contact with the second source electrode 31, the second drain electrode 32, and the second metal oxide semiconductor layer 33. The second gate electrode 35 passes through the second insulating layer 34 and is perpendicular to the second metal oxide semiconductor layer 33.
In the embodiment of the present application, the second field effect transistor 3 further includes a second word line 36 and a second bit line 37, where the second word line 36 and the second bit line 37 are electrically connected to the second gate 35 and the second drain 32, respectively.
In one embodiment, the second word line 36 is electrically connected to the second gate 35, and the second bit line 37 is electrically connected to the second drain 32.
In another embodiment, the second word line 36 is electrically connected to the second drain electrode 32, and the second word line 36 is electrically connected to the second gate electrode 35.
In one particular embodiment, the second word line 36 and the second bit line 37 are parallel to each other; in another embodiment, the second word line 36 and the second bit line 37 are perpendicular to each other.
In the present embodiment, at least one of the second gate 35, the second word line 36, and the second bit line 37 is parallel to the substrate 1. In a specific embodiment, any two of the second gate 35, the second word line 36 and the second bit line 37 are parallel to each other, and each of the second gate 35, the second word line 36 and the second bit line 37 is perpendicular to the second mos layer 33. The array is convenient for a plurality of dynamic memory cells to be closely arranged when forming the array, thereby reducing the occupied area of the dynamic memory cells. Two adjacent dynamic memory cells are connected to each other by at least one of a first word line 26, a first bit line 27, a second word line 36, and a second bit line 37 to form an array.
It should be noted that the drawings are schematic diagrams of the present embodiment. As shown in the figure, the cross-sectional profile of the connection lines such as the first gate 21, the second source 31, the second drain 32, the first word line 26, the first bit line 27, the second word line 36, and the second bit line 37 is rectangular. Indeed, in other embodiments, the cross-sectional profile of the connection lines of the first gate 21, the second source 31, the second drain 32, the first word line 26, the first bit line 27, the second word line 36, the second bit line 37, etc. may also be one of rounded rectangles, circles, and ovals.
In the present embodiment, the second word line 36 and the second bit line 37 are perpendicular to each other. Specifically, when a plurality of dynamic memory cells are arranged in an array, the second bit lines 37 of two adjacent dynamic memory cells in the first direction are connected and collinear, the second word lines 36 of two adjacent dynamic memory cells are parallel, and the distance between the adjacent second word lines 36 is1F; similarly, the first direction is perpendicular to the second direction, adjacent second bit lines 37 are parallel in the second direction, the pitch is 1F, adjacent second word lines 36 are mutually communicated and collinear, and the minimum area of one second FET 3 is 4F 2 。
In some embodiments, first word line 26 is perpendicular to first bit line 27, and at the same time, second word line 36 is perpendicular to second bit line 37.
In the present embodiment, the minimum area of one first fet 2 is 4F 2 The minimum area of the second field effect transistor 3 is 4F 2 . A dynamic memory cell comprising a first FET 2 and a second FET 3, the minimum area of the dynamic memory cell being 4F when the front projection of the first FET 2 onto the substrate 1 and the front projection of the second FET 3 onto the substrate 1 are fully coincident 2 。
In some embodiments of the present application, the first fet 2 is a read fet and the second fet 3 is a write fet; the first word line 26 and the first bit line 27 are read word lines and read bit lines, respectively, and the second word line 36 and the second bit line 37 are write word lines and write bit lines, respectively.
In other embodiments of the present application, the first fet 2 is a write fet and the second fet 3 is a read fet; the first word line 26 and the first bit line 27 are a write word line and a write bit line, respectively, and the second word line 36 and the second bit line 37 are a read word line and a read bit line, respectively.
In some embodiments of the present application, the first metal oxide semiconductor layer 23 and the second metal oxide semiconductor layer 33 are further included, and a material of at least one of the first metal oxide semiconductor layer 23 and the second metal oxide semiconductor layer 33 includes Indium Gallium Zinc Oxide (IGZO). In other embodiments, the metal oxide material may be ITO, IWO, or other materials, such as ZnOx, inOx, in O3, inWO, snO2, tiOx, inSnOx, znxOyNz, mgxZnyOz, inxZnyOz, inxGayZnzOa, zrxInyZnzOa, hfxInyZnzOa, snxInyZnzOa, alxZnO, alxSnyInzZnaOd, sixInyZnzOa, znxSnyOz, alxZnySnzOa, gaxZnySnzOa, zrxZnySnzOa, inGaSiO, or other materials.
In other embodiments, the first gate electrode 21 and the second gate electrode 35 are further included, and the material of at least one of the first gate electrode 21 and the second gate electrode 35 includes silicon dioxide or hafnium oxide.
In still other embodiments, the material further comprising at least one of the first source 24, the first drain 25, the second source 31, the second drain 32, the first word line 26, the first bit line 27, the second word line 36, and the second bit line 37 comprises tungsten.
Specifically, the substrate 1 is a silicon substrate 1. The first metal oxide semiconductor layer 23 and the second metal oxide semiconductor layer 33 may be made of the same material or different materials.
Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a dynamic storage device, where the dynamic storage device includes a dynamic storage unit in any one of the embodiments of the first aspect.
By applying the embodiment of the application, at least the following beneficial effects can be realized: in the embodiment of the application, an upper field effect transistor and a lower field effect transistor which are respectively responsible for reading and writing are adopted to form a dynamic memory unit, the grid electrode of one field effect transistor is perpendicular to the substrate 1, the metal oxide semiconductor layer surrounds the grid electrode, and the grid electrode of the other field effect transistor is perpendicular to the metal oxide semiconductor layer. The cell using the design has very small occupied area, when the line width of the signal line is the Feature Size (F), a plurality of dynamic memory cells form an array, the signal line spacing of the same layer in two adjacent dynamic memory cells is 1F, and the minimum area of the dynamic memory cells is 4F 2 . Therefore, the area of a single dynamic memory unit is reduced, the density of the dynamic memory units in the dynamic memory device is improved, and the miniaturization, the light weight and the integration of the dynamic memory device are facilitated.
In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is only a partial embodiment of the present application and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (12)
1. A dynamic memory cell, comprising:
a substrate;
the first field effect transistor is arranged on one side of the substrate;
the second field effect tube is arranged on one side, far away from the substrate, of the first field effect tube;
the first field effect transistor comprises a first grid electrode, a first insulating layer and a first metal oxide semiconductor layer which are sequentially arranged from inside to outside, wherein the first insulating layer surrounds the first grid electrode, the first metal oxide semiconductor layer surrounds the first insulating layer, and the first metal oxide semiconductor layer is basically vertical to the substrate;
the second field effect transistor comprises a second source electrode, a second drain electrode, a second metal oxide semiconductor layer, a second insulating layer and a second grid electrode, wherein the second source electrode is connected with the first grid electrode, the second drain electrode is positioned on one side, far away from the first grid electrode, of the second source electrode, the second metal oxide semiconductor layer is arranged between the second source electrode and the second drain electrode, the second insulating layer is an encircling structure arranged between the second source electrode and the second drain electrode, and the second grid electrode penetrates through the second insulating layer and is basically perpendicular to the second metal oxide semiconductor layer.
2. The dynamic memory cell of claim 1, wherein the first field effect transistor further comprises a first source and a first drain, the first source and the first drain surrounding the first metal oxide semiconductor layer, respectively.
3. The dynamic memory cell of claim 2, wherein the first source is located on a side of the substrate and the first drain is located on a side of the first source remote from the substrate; alternatively, the first drain electrode is located at a side of the substrate, and the first source electrode is located at a side of the first drain electrode away from the substrate.
4. The dynamic memory cell of claim 2, wherein the first field effect transistor further comprises a first word line and a first bit line, the first word line being electrically connected to the first source and the first bit line being electrically connected to the first drain.
5. The dynamic memory cell of claim 4, wherein the first word line and the first bit line are perpendicular to each other.
6. The dynamic memory cell of claim 1, wherein the second metal oxide semiconductor is in partial contact with the second insulating layer, and wherein an orthographic projection of the second metal oxide semiconductor layer on the substrate and an orthographic projection of the second insulating layer on the substrate do not coincide with each other.
7. The dynamic memory cell of claim 6, wherein the second field effect transistor further comprises a second word line and a second bit line, the second word line being electrically connected to the second gate, the second bit line being electrically connected to the second drain.
8. The dynamic memory cell of claim 7, wherein the second word line and the second bit line are perpendicular to each other.
9. The dynamic memory cell of claim 1, wherein the first fet is a read fet and the second fet is a write fet; alternatively, the first field effect transistor is a writing field effect transistor, and the second field effect transistor is a reading field effect transistor.
10. The dynamic memory cell of claim 1, wherein the material of at least one of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer comprises ITO, IWO, or IGZO.
11. The dynamic memory cell of claim 1, further comprising a first word line, a first bit line, a second word line, and a second bit line, wherein a material of at least one of the first word line, the first bit line, the second word line, and the second bit line comprises tungsten.
12. A dynamic memory device comprising a dynamic memory cell according to any one of claims 1-11.
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| CN202210273227.8A CN116234300B (en) | 2022-03-18 | 2022-03-18 | Dynamic memory cell and dynamic memory device |
| PCT/CN2022/113571 WO2023173679A1 (en) | 2022-03-18 | 2022-08-19 | Transistor and manufacturing method therefor, memory, and electronic device |
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| CN202210273227.8A CN116234300B (en) | 2022-03-18 | 2022-03-18 | Dynamic memory cell and dynamic memory device |
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