CN116203821A - Time-to-digital converter system based on gating single photon counting - Google Patents

Abstract

The present disclosure provides a time-to-digital converter system based on gated single photon counting, including: a phase-locked loop for multiplying the input system clock signal to generate a first clock signal; a global gating signal generation module responsive to Receive the first clock signal to generate M first gating signals and laser synchronous trigger signals, the first gating signal is configured to overlap with the next first gating signal P periods of the first clock signal, each first The signal width of the gating signal is M times the period of the first clock signal; the laser synchronous trigger signal is suitable for controlling the time when the first laser pulse is emitted, wherein M is a positive integer greater than 1, and P is a positive integer greater than or equal to 1; The time-to-digital converter array is suitable for gating and counting the second laser pulse signal according to the first gating signal and the first clock signal to obtain the first statistical distribution of single photons in time; the first laser pulse signal is reflected by the target Then the second laser pulse signal is obtained.

Description

Time-to-Digital Converter System Based on Gated Single Photon Counting

technical field

The present disclosure relates to the technical field of direct time-of-flight measurement three-dimensional imaging based on single-photon avalanche diodes, and in particular to a time-to-digital converter system based on gated single-photon counting.

Background technique

3D imaging can be used for object recognition, behavior recognition, scene modeling and other applications. Currently commonly used 3D imaging technologies include structured light, binocular stereo vision, and time-of-flight (TOF) measurement. Compared with traditional three-dimensional imaging methods, such as structured light, binocular vision, etc., direct time-of-flight (D-TOF) technology, which directly calculates the time difference between the laser pulse emitted by the light source and the reflected signal detected by the sensor, has a huge advantage. Image sensor technology based on the time-of-flight principle has attracted much attention due to its applications in face recognition, vehicle radar, 3-D games and other fields, and is gradually developing towards low-cost and high-performance with the promotion of CMOS technology.

The measurement of direct time-of-flight usually requires the use of a time-to-digital converter (TDC). The traditional time-to-digital converter is usually in a single-event trigger mode, that is, only one event can be recorded for a measurement, the conversion efficiency is low, and it will cause serious stacking distortion. effect, which affects the measurement accuracy; since the TDC circuit itself does not have the ability to distinguish signal from noise, and the distribution of detected laser signal echoes in time is random, in practical applications, multiple measurements are usually performed and passed through time Correlative Single Photon Counting (TCSPC) technology accumulates and counts the measurement results and generates a statistical histogram to obtain an effective time-of-flight. In order to reduce the limitation of the input and output (IO) of the chip on data transmission during the statistical process, and reduce the large power consumption caused by data transmission on the IO, it is an effective solution to integrate the statistical histogram inside the sensor.

However, in the prior art, the research on time-to-digital converters has the following deficiencies: TDC conversion efficiency is low, a large number of inputs cannot be effectively recorded during the measurement process, and on-chip histogram statistics require a large number of memory units, which require a large area overhead and are not Suitable for large array applications etc.

Contents of the invention

In order to solve at least one of the technical problems in the prior art, the present disclosure provides a time-to-digital converter system based on gated single photon technology. During measurement, by overlapping the gating signal with the next gating signal, avoiding The signal loss at the edge of the gating signal is eliminated, so that the input pulse can be effectively recorded, and the conversion efficiency of the time-to-digital converter is improved.

An aspect of the embodiments of the present disclosure provides a time-to-digital converter system based on gated single photon counting, including: a phase-locked loop, a global gating signal generation module, and a time-to-digital converter array. The phase-locked loop is used to multiply the frequency of the input system clock signal to generate the first clock signal. The global gating signal generation module generates M first gating signals and laser synchronization trigger signals in response to receiving the first clock signal, and the first gating signal is configured to overlap P with the next first gating signal period of the first clock signal, and make the signal width of each of the first gating signals M times that of the period of the first clock signal; the laser synchronous trigger signal is suitable for controlling the emission of the first laser pulse Time to obtain the time information of laser emission, where M is a positive integer greater than 1, and P is a positive integer greater than or equal to 1. an array of time-to-digital converters, comprising a plurality of time-to-digital converters, each of said time-to-digital converters being adapted to gate and count a second laser pulse signal based on a first gating signal and said first clock signal, so that The first statistical distribution of single photons in time is obtained. Wherein, the second laser pulse signal is obtained after the first laser pulse signal is reflected by the target.

According to an embodiment of the present disclosure, each time-to-digital converter includes: a buffer module and a configurable counter array. In response to the input of the first clock signal, the cache module retimes the input M first gating signals to obtain M second gating signals. The configurable counter array includes M counter components, and each of the counter components is adapted to receive one of the second gating signals and perform gating and counting of the second laser pulse signals.

According to an embodiment of the present disclosure, each of the time-to-digital converter arrays further includes:

The peak-seeking module is used to compare the values of the number of single photons obtained by the counter array to obtain the address of the gating signal where the maximum value of photons is located.

According to an embodiment of the present disclosure, each of the time-to-digital converters further includes: a digital control module, a first mode gating signal generating module, and a multi-level gating synchronization module. The digital control module is used for generating a mode selection signal according to an externally input sampling mode control instruction. The first mode gating signal generation module responds to the mode selection signal and generates 2M third gating signals according to the first maximum gating signal, and the width of each of the third gating signals is M/8 of the first The cycle of the clock signal, the adjacent third gating signal overlaps the cycle of the first clock of P/2, wherein the first maximum gating signal is obtained by comparing the first statistical distribution by the peak-finding module of. The multi-level gating synchronization module is adapted to reclock the second gating signal and the third gating signal according to the first clock signal in response to the mode selection signal so that the third gate The rising edge of the control signal is aligned with the rising edge of the second gating signal. Wherein, the counter component is suitable for counting the second laser pulse signal according to the aligned third gating signal to obtain the second statistical distribution.

According to an embodiment of the present disclosure, the above-mentioned time-to-digital converter system further includes: a delay-locked loop, in response to receiving the first clock signal, performing multi-stage delay on the first clock signal to output The control voltage for the delay unit to perform delay operation;

Each of the time-to-digital converters also includes: a second mode gating signal generation module, which inputs a second maximum gating signal to a 4M-level extended copy chain circuit in response to receiving the mode selection signal, and the 4M-level extended copy chain circuit The chain circuit outputs 4M delayed signals under the action of the control voltage, the rising edges of the 4M delayed signals sample the second laser pulse signal, detect the position of the rising edge of the second laser pulse signal, and generate 4M fourth laser pulse signals accordingly A gating signal, wherein the second maximum gating signal is obtained by comparing the second statistical distribution by the peak finding module. Wherein, the counter component is adapted to count according to the fourth gating signal and the rising edge of the delay signal, so as to obtain the third statistical distribution.

According to an embodiment of the present disclosure, the multi-level gating synchronization module is further adapted to generate a valid count gate signal;

Each of the counter components includes: a first data selector, a plurality of counters and a plurality of second data selectors. The first data selector is configured to receive the mode selection signal to select a count pulse signal including the second laser pulse signal or the delay signal. A plurality of counters are configured to count photons in combination with the valid count gate signal and the count pulse signal. The input end of each of the second data selectors is respectively connected with the output end of one of the counters and the output end of the first data selector, and the output end of the second data selector is connected with the input end of the next counter connected, the trigger pulse signal is input to the next counter in combination with the mode selection signal.

According to an embodiment of the present disclosure, each of the counters includes: a plurality of counting D flip-flops and a counting data selector. The clock signal input end of the first counting D flip-flop is configured to be connected to the output end of the first data selector to receive the counting pulse signal. The counting data selector uses the output signal of the first output terminal or the second output terminal of the first counting D flip-flop as the data input signal of the first counting D flip-flop according to the counting type signal, and the data input terminals of other counting D flip-flops The output signals of the respective second output terminals are respectively received. Wherein, the second output end of the previous counting D flip-flop is connected to the clock signal input end of the next counting D flip-flop, the output end of the first counting D flip-flop outputs the lowest bit of the count value, and the last counting D flip-flop The output terminal outputs the most significant bit of the count value.

According to an embodiment of the present disclosure, each of the time-to-digital converters further includes: a data readout module, adapted to read the count value generated by the counter component or the peak address generated by the peak-seeking module according to the mode selection signal out the data.

According to an embodiment of the present disclosure, the global gating signal generation module includes: a frequency division unit, a generation unit and a laser synchronization unit. The frequency division unit is adapted to divide the frequency of the first clock signal to obtain a third clock signal. The generating unit is adapted to generate a plurality of first gating signals according to the third clock signal and the first clock signal, and the generating unit includes M generating D flip-flops and M generating OR gates respectively arranged at the output terminals, so that The first gating signal overlaps with the next first gating signal by P periods of the first clock signal. The laser synchronization unit is adapted to emit a laser synchronization trigger signal under the action of the first gating signal and the first clock signal.

According to an embodiment of the present disclosure, the above-mentioned time-to-digital converter system further includes: a clock tree, adapted to convert the first clock signal generated by the phase-locked loop and the first gating signal generated by the global gating signal to sent to each time-to-digital converter.

According to an embodiment of the present disclosure, the present disclosure provides a time-to-digital converter system based on gated single-photon technology. In the measurement, by overlapping the gating signal with the next gating signal, the edge of the gating signal is avoided. signal loss, so that the input pulse can be effectively recorded, improving the conversion efficiency of the time-to-digital converter.

Description of drawings

FIG. 1 schematically shows a measurement principle diagram of a time-to-digital converter system based on gated single photon technology according to an embodiment of the present disclosure;

2 schematically shows a system diagram of a time-to-digital converter system based on gated single photon technology according to an embodiment of the present disclosure;

FIG. 3 schematically shows a pulse timing diagram of a first gating signal and a second gating signal under a first clock according to an exemplary embodiment of the present disclosure;

Fig. 4 schematically shows a circuit diagram of a buffer module and a digital control module according to an exemplary embodiment of the present disclosure;

Fig. 5 schematically shows a circuit diagram of a first mode gating signal generation module according to an exemplary embodiment of the present disclosure;

Fig. 6 schematically shows a circuit diagram of a second mode gating signal generation module according to an exemplary embodiment of the present disclosure;

Fig. 7 schematically shows a statistical pulse timing diagram of a third statistical distribution according to an exemplary embodiment of the present disclosure;

Fig. 8 schematically shows a circuit diagram of a multi-level gating synchronization module according to an exemplary embodiment of the present disclosure;

Fig. 9 schematically shows a circuit diagram of a counter assembly according to an exemplary embodiment of the present disclosure;

Fig. 10 schematically shows a circuit diagram of a data readout module according to an exemplary embodiment of the present disclosure;

Fig. 11 schematically shows a circuit diagram of a global gating signal generation module according to an exemplary embodiment of the present disclosure; and

Fig. 12 schematically shows a statistical distribution diagram according to an exemplary embodiment of the present disclosure.

Explanation of reference signs:

1 - PLL;

2-Global gating signal generation module;

21-frequency division unit;

22 - generating unit;

23 - laser synchronization unit;

3 - Time-to-digital converter array;

31-cache module;

32 - configurable counter array;

33-peak finding module;

34-the first mode gating signal generating module;

35-Multi-level gating synchronization module;

36-the second mode gating signal generating module;

361-extended copy chain circuit;

37-data readout module;

38 - digital control module;

4- Delay locked loop; and

5- Clock tree.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and like reference numerals designate like elements throughout.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present disclosure. The terms "comprising", "comprising", etc. used herein indicate the presence of stated features, steps, operations and/or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

All terms (including technical and scientific terms) used herein have the meaning commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have a meaning consistent with the context of this specification, and not be interpreted in an idealized or overly rigid manner.

In order to facilitate those skilled in the art to understand the technical solution of the present disclosure, the following technical terms are now explained.

Where expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted as those skilled in the art would normally understand the expression (for example, "having A, B, and C A system of at least one of "shall include, but not be limited to, systems with A alone, B alone, C alone, A and B, A and C, B and C, and/or A, B, C, etc. ). Where expressions such as "at least one of A, B, or C, etc." are used, they should generally be interpreted as those skilled in the art would normally understand the expression (for example, "having A, B, or C A system of at least one of "shall include, but not be limited to, systems with A alone, B alone, C alone, A and B, A and C, B and C, and/or A, B, C, etc. ).

FIG. 1 schematically shows a measurement principle diagram of a time-to-digital converter system based on gated single photon technology according to an embodiment of the present disclosure.

As shown in Figure 1, the laser emits a first laser pulse in response to a transmit signal. The distance from the first laser pulse to the target is D. The laser emits the first pulse laser at the START moment. After the first pulse laser is reflected by the target, the reflected laser signal is detected by the detector at the STOP moment. The time difference from the START moment to the STOP moment The travel time of the first laser is t. The reflected laser signal is converted by an external pixel array to obtain a second pulse signal, and the second pulse signal is an electrical pulse signal. TDC in Fig. 1 represents a time-to-digital converter system.

In an exemplary embodiment, the external pixel arrays are avalanche diode arrays (SPADs).

The time-to-digital converter system TDC obtains the statistical distribution histogram of photons in time according to the detected second pulse signal and the propagation time t of the laser.

FIG. 2 schematically shows a system diagram of a time-to-digital converter system based on gated single photon technology according to an embodiment of the present disclosure. Fig. 3 schematically shows a pulse timing diagram of a first gating signal and a second gating signal under a first clock according to an exemplary embodiment of the present disclosure.

One aspect of the present disclosure provides a time-to-digital converter system based on gated single photon counting, as shown in FIG. The phase-locked loop 1 is used to multiply the frequency of the input system clock signal to generate the first clock signal. The global gating signal generation module 2 generates M first gating signals and laser synchronization trigger signals in response to receiving the first clock signal, and the first gating signal is configured to overlap P first gating signals with the next first gating signal The period of the clock signal, and making the signal width of each first gating signal M times the period of the first clock signal. The laser synchronization trigger signal is suitable for controlling the time when the first laser pulse is emitted, so as to obtain the time information of the laser emission, wherein M is a positive integer greater than 1, and P is a positive integer greater than or equal to 1. The time-to-digital converter array 3 includes a plurality of time-to-digital converters, and each time-to-digital converter is suitable for gating and counting the second laser pulse signal SiPM according to the first gating signal and the first clock signal, so as to obtain single photons First statistical distribution over time. Wherein, the second laser pulse signal SiPM is obtained after the first laser pulse signal is reflected by the target.

According to an embodiment of the present disclosure, the present disclosure provides a time-to-digital converter system based on gated single-photon technology. In the measurement, by overlapping the gating signal with the next gating signal, the edge of the gating signal is avoided. The signal loss is reduced to obtain a complete echo signal, so that the input pulse can be effectively recorded, and the conversion efficiency of the time-to-digital converter is improved.

According to an embodiment of the present disclosure, in an electronic circuit, the frequency of the generated output signal is an integer multiple of the frequency of the input signal, which is called frequency multiplication.

In an exemplary embodiment, the PLL 1 multiplies the frequency of the input system clock signal by 4 to generate a first clock signal whose frequency is 4 times that of the system clock.

In an exemplary embodiment, the phase-locked loop multiplies the frequency of the input system clock signal by 8 to generate the first clock signal whose frequency is 8 times that of the system clock.

According to an embodiment of the present disclosure, the laser emits a first laser pulse signal in response to a rising edge of the laser synchronization trigger signal.

According to an embodiment of the present disclosure, the first laser pulse signal detected by the external detector and reflected by the target is converted by an external pixel array to obtain a second pulse signal, and the second pulse signal is an electrical pulse signal.

In some exemplary embodiments, the signal width of the first gating signal is any one of 16 times, 20 times, 32 times, etc. of the period of the first clock signal.

In some exemplary embodiments, the first gating signal overlaps with the next first gating signal by 4 periods of the first clock signal.

In an exemplary embodiment, the first gating signal overlaps with the next first gating signal by 3 cycles of the first clock signal.

In an exemplary embodiment, the first gating signal overlaps with the next first gating signal by 2 periods of the first clock signal.

Preferably, as shown in FIG. 3 , CK represents the first clock signal, C1_GATE<n> represents the first gate control signal, n is a positive integer, and M>n≥0. The signal width T1 of the first gate control signal C1_GATE<n> is 8 times the period T0 of the first clock signal, and the first gate control signal C1_GATE<0> overlaps with the next first gate control signal C1_GATE<1> by 1 clock cycle.

Fig. 4 schematically shows a circuit diagram of a cache module and a digital control module according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in FIG. 2 , each time-to-digital converter includes: a cache module 31 and a configurable counter array 32 . As shown in FIG. 4 , SYS_RST_N is an externally input system reset signal, and the buffer module 31 retimes the input M first gating signals in response to the input of the first clock signal to obtain M second gating signals. The configurable counter array 32 includes M counter components, and each counter component is adapted to receive a second gating signal to gate and count the second laser SiPM pulse signal.

According to an embodiment of the present disclosure, the second gating signal is the first gating signal aligned with the rising edge of the first clock signal.

According to an embodiment of the present disclosure, as shown in FIG. 2 , each time-to-digital converter array further includes: a peak-seeking module 33, which is used to compare the values of the single photon numbers obtained by the counter array, and obtain the gate where the maximum photon value is located. The address of the control signal.

Fig. 5 schematically shows a circuit diagram of a first mode gating signal generation module according to an exemplary embodiment of the present disclosure

According to an embodiment of the present disclosure, as shown in FIG. 2 , each time-to-digital converter further includes: a digital control module, a first mode gating signal generating module, and a multi-level gating synchronization module. As shown in FIG. 4 , the digital control module 38 is configured to generate a mode selection signal DIG_Control_OUT according to an externally input sampling mode control command DIG_Control. As shown in Figure 5, the first mode gating signal generation module responds to the mode selection signal and generates 2M third gating signals F_GATE according to the first maximum gating signal, and the signal width of each third gating signal F_GATE is M/ 8 periods of the first clock signal, the adjacent third gating signal overlaps the period of P/2 of the first clock, wherein the first maximum gating signal is obtained by comparing the first statistical distribution of the peak finding module of. The multi-level gating synchronization module is adapted to reclock the second gating signal and the third gating signal according to the first clock signal so that the rising edge of the third gating signal is consistent with the second gating signal in response to the mode selection signal The rising edge of the control signal is aligned. Wherein, the counter component is suitable for counting the pulse signals of the second laser SiPM according to the aligned third gate signal to obtain the second statistical distribution.

In an exemplary embodiment, the third gating signal overlaps with the next third gating signal by one period of the first clock signal.

Preferably, as shown in FIG. 3 , CK represents the first clock signal, C2_GATE<n> represents the third gate control signal, n is a positive integer, and 2M>n≥0. The signal width of the third gate control signal C2_GATE<n> is 1 time of the period T0 of the first clock signal, and the third gate control signal C2_GATE<0> overlaps with the next third gate control signal C2_GATE<1> by 1/2 clock cycle.

According to the embodiment of the present disclosure, both the first gating signal and the third gating signal are overlapping, which avoids the problem of omission generated at the edges of non-overlapping gating signals.

According to an embodiment of the present disclosure, in the first statistical distribution and the second statistical distribution, a multi-level gating signal is directly generated to act on the counter array for gating counting, and its maximum counting rate depends on the maximum operating frequency of the D flip-flop.

Fig. 6 schematically shows a circuit diagram of a second mode gating signal generating module according to an exemplary embodiment of the present disclosure. Fig. 7 schematically shows a statistical pulse timing diagram of a third statistical distribution according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in FIG. 2 , the time-to-digital converter system further includes: a delay-locked loop 4, which responds to receiving the first clock signal and performs multi-stage delay on the first clock signal to output the first clock signal for control The control voltage VCTRL for the delay unit to perform the delay operation.

As shown in FIG. 2 , each time-to-digital converter further includes: a second mode gating signal generation module 36 . As shown in FIG. 6, the second mode gating signal generation module 36 inputs the second maximum gating signal to the 4M-level extended copy chain circuit 361 in response to the receiving mode selection signal, and the 4M-level extended copy chain circuit 361 is at the control voltage VCTRL. Under the action, 4M delayed signals delay<31:0> are output, as shown in Figure 7, the rising edges of the 4M delayed signals sample the second laser pulse signal SiPM, detect the position of the rising edge of the second laser pulse signal SiPM, and Correspondingly generate 4M fourth gate control signals F_GATE, wherein the second largest gate control signal is obtained by comparing the second statistical distribution by the peak finding module. Wherein, the counter component is adapted to count according to the rising edge of the fourth gating signal and the delay signal, so as to obtain the third statistical distribution.

According to an embodiment of the present disclosure, the delay-locked loop 4 delays the first clock signal by N levels in response to receiving the first clock signal, so as to output a control voltage for controlling the delay unit to perform a delay operation, where N is positive integer, and 4M>N>2M.

In an exemplary embodiment, the delay-locked loop delays the first clock signal by 20 levels in response to receiving the first clock signal, so as to output a control voltage for controlling the delay unit to perform a delay operation.

According to an embodiment of the present disclosure, in the third statistical distribution, the rising edge of the second laser pulse is detected by extending the multi-phase clock delay signal generated by the replication chain circuit 361, and the gate corresponding to the delayed clock that detects the rising edge is used to The enable signal is set to 1, and its maximum detection rate depends on the frequency of the input pulse signal.

According to an embodiment of the present disclosure, the delay chain circuit for generating multi-phase clocks by the second mode gating signal generation module is an extended and replicated delay chain circuit, by extending and replicating the N-level delay chain in the delay-locked loop into a 4M-level delay chain , to avoid the impact of the mismatch on the replica delay chain circuit due to process-voltage-temperature (PVT) changes, and ensure that the transition time width (detectable time interval width) in the third statistical distribution is slightly larger than the third gating signal width.

In an exemplary embodiment, the switching time width is greater than the third gating signal width difference by a period of the first clock signal.

Fig. 8 schematically shows a circuit diagram of a multi-level gating synchronization module according to an exemplary embodiment of the present disclosure. Fig. 9 schematically shows a circuit diagram of a counter component according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in FIG. 8, the multi-level gating synchronization module is also adapted to generate an effective count gating signal according to the mode selection signal, the second gating signal, the third gating signal and the fourth gating signal CNT_EN.

As shown in FIG. 9 , each counter component includes: a first data selector, a plurality of counters, and a plurality of second data selectors. The first data selector is configured to receive a mode selection signal to select the count pulse signal cnt_tregger including the second laser pulse signal SiPM or the delay signal. The plurality of counters are configured to count photons in combination with the active count gate signal CNT_EN and the count pulse signal cnt_tregger. The input end of each second data selector is respectively connected with the output end of a counter and the output end of the first data selector, and the output end of the second data selector is connected with the input end of the next counter, combined with the mode selection signal Input the trigger pulse signal to the next counter. In FIG. 9, Fine_En is the enabling signal of the third statistical distribution mode. RN is an external input counter reset signal.

According to an embodiment of the present disclosure, as shown in FIG. 9 , each counter includes: a plurality of counting D flip-flops and a counting data selector. The clock signal input terminal of the first counting D flip-flop is configured to be connected to the output terminal of the first data selector to receive the counting pulse signal. The counting data selector uses the output signal of the first output terminal or the second output terminal of the first counting D flip-flop as the data input signal of the first counting D flip-flop according to the counting type signal, and the data input terminals of other counting D flip-flops respectively receive The output signals of the respective second output terminals. Wherein, the second output end of the previous counting D flip-flop is connected to the clock signal input end of the next counting D flip-flop, the output end of the first counting D flip-flop outputs the lowest bit of the count value, and the last counting D flip-flop The output terminal outputs the most significant bit of the count value.

According to the embodiments of the present disclosure, the configurable counter array has flexible configuration modes in different statistical modes to meet the requirements of different modes for the counting range. The configurable counter array adjusts the bit width of the counter according to the width of the gate control signal, which can not only meet the bit width requirement of the counter, but also reduce the area.

In an exemplary embodiment, in the first statistical distribution mode, the counter array is configured as 8 20-bit asynchronous counter arrays; in the second statistical distribution mode, the counter array is configured as 16 10-bit asynchronous counter arrays; In the third statistical distribution mode, the counter array is configured as 32 5-bit asynchronous counter arrays.

According to an embodiment of the present disclosure, the configurable counter array has an overflow prevention function in each distribution mode, and once any counter reaches the maximum value, all counters in the array stop counting.

In an exemplary embodiment, in the first statistical distribution mode, if any counter reaches 1048575 (2 ²⁰ -1), all 8 counters in the array stop counting; in the second statistical distribution mode, if any counter reaches 1023 (2 ¹⁰ -1), all 16 counters in the array stop counting; in the third statistical distribution mode, if any counter counts up to 31 (2 ⁵ -1), all 32 counters in the array stop counting.

Fig. 10 schematically shows a circuit diagram of a data readout module according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in FIG. 2 , each time-to-digital converter further includes: a data readout module 37 . As shown in FIG. 10 , the data readout module 37 is adapted to read out data from the count value generated by the counter component or the peak address generated by the peak finding module according to the mode selection signal.

According to an embodiment of the present disclosure, the data readout module 37 outputs the count value of the counter array or the peak address generated by the peak seeking module to the outside of the array through the multiplexer and the tri-state gate readout buffer for data processing.

According to the embodiment of the present disclosure, the data readout module adopts a multiplexer plus a three-state gate column bus to reduce the bit width of the data bus, and supports two readouts of peak address readout and counter array count value readout mode to meet the different requirements for reading data in different modes. Fig. 11 schematically shows a circuit diagram of a global gating signal generating module according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, as shown in FIG. 11 , the global gating signal generation module includes: a frequency division unit, a generation unit and a laser synchronization unit. The frequency dividing unit is adapted to divide the frequency of the first clock signal to obtain the third clock signal. The generating unit is adapted to generate a plurality of first gating signals according to the third clock signal and the first clock signal, and the generating unit includes M generating D flip-flops and M generating OR gates respectively arranged at the output terminals, so that the first gate The control signal overlaps with the next first gating signal for P periods of the first clock signal. The laser synchronization unit is adapted to emit a laser synchronization trigger signal under the action of the first gate signal and the first clock signal.

According to an embodiment of the present disclosure, the frequency division unit is adapted to divide the first clock signal by M-1 times to obtain a third clock signal, and the frequency of the third clock signal is 1/(M-1) times that of the first clock signal .

In an exemplary embodiment, the frequency dividing unit is adapted to divide the frequency of the first clock signal by 15 times to obtain the third clock signal.

According to the embodiment of the present disclosure, in order to compensate the propagation delay from the generation of the first gating signal to the action on the configurable counter array, the C1_GATA<0> signal is delayed by three periods of the first clock signal to generate the laser synchronization signal laser_sync.

According to an embodiment of the present disclosure, as shown in FIG. 2 , the time-to-digital converter system further includes: a clock tree, adapted to respectively send the first clock signal generated by the phase-locked loop and the first gating signal generated by the global gating signal to each time-to-digital converter.

According to an embodiment of the present disclosure, the time-to-digital conversion system based on the gated single photon technology provided by the present disclosure provides at least three modes of time-to-digital conversion outputs.

In the first statistical distribution mode, output the result of the first statistical distribution. In the second statistical distribution mode, the first maximum gating signal is determined according to the first statistical distribution result, and the second statistical result is output. In the third statistical distribution mode, the second maximum gating signal is determined according to the second statistical distribution result, and the third statistical result is output. According to actual needs, a sampling mode control command can be input to the time-to-digital converter system to select the desired output result. The counter array in each exposure mode can be flexibly configured to meet the requirements of the counter counting range under different gating signal widths, thereby reducing the overall requirement for the counter bit width and reducing the required area of the counter array. The anti-overflow design of the counter array can avoid the distortion of the counting statistics due to the long exposure time.

According to an embodiment of the present disclosure, the time-to-digital converter system provided by the present disclosure can locate the address of the gate control signal where the laser echo signal is located by means of peak detection, and refine the gate control signal into a gate control signal of a smaller window To approximate the position of the laser echo, and finally generate a histogram of only 32 bins.

According to the embodiment of the present disclosure, in the third statistical distribution mode, a certain redundancy is also made by extending the delay chain to avoid signal loss, and multiple rising edges of the input signal SiPM within the detection time can be identified , to realize a multi-event detection, the conversion efficiency of the time-to-digital converter is high, it is not easy to lose events, and it is beneficial to perform efficient time distribution statistics on the events input into the time-to-digital converter completely and without distortion.

In an exemplary embodiment, as shown in FIG. 2 , the time-to-digital converter system based on gated single photon technology includes: a phase-locked loop 1, a delay-locked loop 4, a global gating signal generation module 2, a clock Tree 5 and Time-to-Digital Converter Array 3 .

The phase-locked loop 1 is used for multiplying the input low frequency into the system clock SYS_CK to generate a high frequency first clock signal CK.

The delay-locked loop 4 is used to pass the input first clock signal CK through 28-stage delay units to generate 28-phase delay clocks, and output the delay chain control voltage VCTRL that controls the delay of the delay units to the time-to-digital converter array 3 , as the control voltage of the extended copy delay chain circuit in the second mode gating signal generation module.

As shown in Fig. 2 and Fig. 3, the global gating signal generating module 2 is used to generate 8-level overlapping first gating signal, the width of the first gating signal is eight first clock periods, and is connected with the next first clock cycle respectively. The gating signals overlap by a first clock cycle. As shown in FIG. 6 , the global gating signal generation module 2 includes a frequency division unit 21 , a generation unit 22 and a laser synchronization trigger unit 23 .

As shown in FIG. 6 , the frequency dividing unit 21 divides the frequency of the first clock signal CK by seven to obtain the third clock signal CK_7 .

As shown in FIG. 6 , the generating unit 22 includes 8 generating D flip-flops and 8 generating OR gates respectively arranged at the output terminals. The generating unit 22 generates eight first gate control signals C1_GATE<n> according to the third clock signal CK_7 and the first clock signal CK. CK_7 and CK work together on the global gating signal generation module 2 . When the external input enable signal EXP_EN changes from low level to high level, a pulse signal STA with a width of 7 CK clock cycles is generated. The STA signal propagates in the D flip-flop delay chain circuit and is controlled by the first clock signal CK Sampling and generating D flip-flops and OR gates are respectively performed, and the pulse width is extended to 8 first clock cycles. When the STA signal propagates to the end of the D flip-flop delay chain circuit, the feedback signal FB will be generated and re-introduced to the D flip-flop delay chain circuit to generate the first gating signal in a loop until the externally input enable signal EXP_EN is powered by a high voltage. Turning to a low level, cut off the feedback loop of the feedback signal FB, and stop generating new gating signals.

As shown in FIG. 6 , the laser synchronization unit 23 generates a laser synchronization signal laser_sync after delaying the C1_GATA<0> signal by three periods of the first clock signal.

The clock tree 5 distributes the first clock signal and the 8-level overlapping gating signal C1_GATE<n> generated by the global gating signal generating module 2 to the entire time-to-digital converter array 3 .

As shown in FIG. 2 , the time-to-digital converter array 3 includes at least one time-to-digital converter HTDC. Each time-to-digital converter HTDC includes: a cache module 31, a digital control module 38, a first mode gating signal generating module 34, a second mode gating signal generating module 36, a multi-level gating synchronization module 35, and a configurable counter Array 32 , peak finding module 33 and data readout module 37 .

As shown in FIG. 4 , the buffer module 31 is used to process the input single-phase first clock signal CK into a differential clock pair CK/KCN and increase its driving capability. The first clock signal CK retimes the input first gating signal to obtain the second gating signal.

The digital control module 38 generates a mode selection signal DIG_Control_OUT according to the sampling mode control command DIG_Control input from the outside.

As shown in FIG. 8 , the multi-level gating synchronization module 35 responds to the mode selection signal, and retimes the second gating signal and the third gating signal according to the first clock signal so that the rising edge of the third gating signal Aligned with the rising edge of the second gating signal. The multi-level gating synchronization module 35 can also generate a valid counting gating signal according to the mode selection signal, the second gating signal, the third gating signal and the fourth gating signal.

The configurable counter array 32 is used to count the second laser pulse signal SiPM under the second gating signal. By configuring each counter in the configurable counter array with a corresponding second gating signal, after multiple counting and statistics, The first statistical distribution of the input second laser pulse signal SiPM in time can be obtained. The configurable counter array 32 includes 8 counter elements.

As shown in FIG. 9 , each counter component includes: a first data selector, 4 counters CNT_5b and 3 second data selectors. The first data selector receives the mode selection signal to select the count pulse signal. The four counters count photons in combination with effective counting gate signals and counting pulse signals. The input end of each second data selector is respectively connected with the output end of a counter and the output end of the first data selector, and the output end of the second data selector is connected with the input end of the next counter, combined with the mode selection signal Input the trigger pulse signal to the next counter. A data selector is connected between two adjacent counters, which is controlled by the chain<2:0> signal. The chain<2:0> signal is the value of the mode selection signal. If the chain<0>, chain<1> and chain<2> signals are all = 1, then it is configured as a 20-bit counter; if they are all 0, it is four 5-bit counters, if chain<1> = 0 , chain<0>, chain<2>=1, then it is configured as two 10bit counters.

The peak-seeking module 33 compares the count value of the first statistical distribution of the configurable counter array, obtains the first maximum gating signal address where the maximum count value is located, and returns to the first mode gating signal generation module as the first The mode gating signal generates a control signal for the block's selector.

As shown in FIG. 10 , the data readout module reads data from the address of the first maximum gating signal generated by the peak hunting module according to the mode selection signal.

As shown in FIG. 5 , the first mode gating signal generation module 34 refines the first maximum gating signal C1_ADDR whose address is counted to the peak value of the first gating signal, that is, under the first maximum gating signal C1_ADDR, generates There are 16 overlapping third gate control signals C2_GATE, the width of each third gate control signal is one period of the first clock signal, and adjacent third gate control signals overlap by half of the period of the first clock signal. The one-of-eight selector selects the corresponding C1_GATE signal from C1_ADDR, and acts on the pulse generation module to generate a pulse Wind_In with a width of 1 CK period when the control signal MODE_EN is 1, and respectively under the action of the differential clock pair CK/CKN in Generate D flip-flops to propagate in the propagation chain to generate the required gating signals.

The configurable counter array 32 is used to count the second laser pulses under the third gating signal. By configuring each counter in the configurable counter array with a corresponding third gating signal, after multiple counting and statistics, it can be obtained A second statistical distribution of the second laser pulses over time is input.

As shown in FIG. 10 , the data readout module 37 reads out data from the address of the second maximum gating signal generated by the peak hunting module 33 according to the mode selection signal.

The peak-seeking module 33 compares the count value of the second statistical distribution of the configurable counter array, obtains the second maximum gating signal address where the maximum count value is located, and returns to the first mode gating signal generating module as the first The mode gating signal generates a control signal for the block's selector.

As shown in Figure 6, the second mode gating signal generation module receives the mode selection signal and inputs the second maximum gating signal to the 4M-level extended copy chain circuit, and the 4M-level extended copy chain circuit outputs 4M under the action of the control voltage VCTRL For the delay signal, the rising edges of the 4M delayed signals sample the second laser pulse signal, detect the position of the rising edge of the second laser pulse signal, and correspondingly generate 4M fourth gate signals.

As shown in FIG. 9 , the counter component counts according to the fourth gating signal and the rising edge of the delay signal, so as to obtain the third statistical distribution.

Fig. 12 schematically shows a statistical distribution diagram according to an exemplary embodiment of the present disclosure.

As shown in FIG. 12 , in the first statistical distribution mode, the first statistical distribution result is output, and the first statistical distribution result is eight 20-bit counters. In the second statistical distribution mode, the first maximum gating signal is determined according to the first statistical distribution result, the first maximum gating signal is refined, and the second statistical distribution result is output. The second statistical distribution result is 16 10-bit counters. In the third statistical distribution mode, the second maximum gating signal is determined according to the second statistical distribution result, and the second maximum gating signal is input to the 4M-level extended copy chain circuit, and the 4M-level extended copy chain circuit is under the action of the control voltage Output 4M delayed signals, the rising edge of the 4M delayed signals samples the second laser pulse signal, detects the position of the rising edge of the second laser pulse signal, and generates 4M fourth gate control signals accordingly, the counter component is based on the fourth gate The control signal cooperates with the rising edge of the delay signal to count to obtain the third statistical result, and the third statistical distribution result is 32 5-bit counters.

The workflow of the time-to-digital converter system for gated single photon counting described above is as follows:

When the power is turned on and started, the phase-locked loop starts to work, and locks the system clock to the required frequency to generate the first clock signal.

After the phase-locked loop is powered on and locked, the delay-locked loop starts to work, and locks the delay chain control voltage VCTRL to the corresponding voltage value, and outputs it as a control voltage to the extended copy delay chain circuit in the time-to-digital converter array.

The digital control unit or off-chip input enable signal EXP_EN to the global gate control signal generation module, when the EXP_EN signal is high level, the global gate control signal generation module generates the first gate control signal C1_GATE and the laser synchronization trigger signal LASER_SYNC. Among them, LASER_SYNC is output to off-chip, which is used to trigger the laser synchronously. The first gating signal and the phase-locked loop output clock (the first clock signal) are distributed to the time-to-digital converter array through the clock tree.

The time-to-digital converter array performs gated counting statistics under the first gating signal. After the first gating signal C1_GATE is retimed by the multi-level gating synchronization module, the second gating signal is generated and input to the configurable counter array for gating counting statistics, until the EXP_EN signal turns to low level, the global gating signal generation module stops When C1_GATE is generated cyclically, the counting and statistics will stop. After waiting for the counting of the counter array to be stable, start the peak-seeking module to obtain the gating signal address C1_ADDR where the counting peak is located.

The statistical mode is changed to the second statistical distribution mode, and after the enable signal EXP_EN is changed to a high level, gated counting statistics are performed in the second statistical distribution mode. The first mode gating signal generation module selects the corresponding C1_GATE signal under the control of C1_ADDR, and subdivides it into 16-level overlapping gating signal C2_GATE, which is retimed by the multi-level gating synchronization module and then input to the configurable counter array for gate Control the counting and statistics until the EXP_EN signal turns to low level, the global gating signal generation module stops generating C1_GATE in a loop, and then stops the counting and statistics. After waiting for the counting of the counter array to be stable, start the peak-seeking module to obtain the gating signal address C2_ADDR where the counting peak is located.

The statistical mode is changed to the third statistical distribution mode, and after the enable signal EXP_EN is changed to a high level, gated counting statistics are performed in the third statistical distribution mode. The second mode gating signal generation module selects the corresponding C2_GATE signal under the control of C2_ADDR, and generates a 32-phase delay signal delay<31:0> through a 28-stage delay chain, and the multi-phase delay signal delay<31:0> rises Sampling flip-flops are respectively triggered on the edge to sample the input pulse, and the position of its rising edge is detected by combinational logic, and the gate control signal corresponding to the delayed signal of the rising edge of the input pulse is set to 1, and input to the multi-level gate synchronization module. After the rising edge trigger sampling of the 32-phase delay signal delay<31:0> is completed, the trigger pulse generated by the gating signal generating module in the second mode will trigger and count the counter whose gating signal is 1. After the counting is completed, the second mode gating signal generating module will generate a reset signal to reset the rising edge sampling D flip-flop of the delayed signal. When EXP_EN is at a high level, the process of the third statistical distribution mode will be repeated multiple times until the EXP_EN signal turns to a low level, the global gating signal generation module stops generating C1_GATE in a loop, and the third statistical distribution mode ends, and it can be started at this time The peak-seeking module obtains the gating signal address F_ADDR where the counting peak value is located.

According to the input digital control signal, the data readout module selects output peak address ({C1_ADDR, C2_ADDR, F_ADDR}) or counter array count value (CNT[159:0]).

According to specific requirements, the first statistical distribution mode, the second statistical distribution mode or the third statistical distribution mode may be repeated, and corresponding data may be output.

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that, in the accompanying drawings or in the text of the specification, implementations that are not shown or described are forms known to those of ordinary skill in the art, and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those skilled in the art can easily modify or replace them.

Based on the above description, those skilled in the art should have a clear understanding of the time-to-digital conversion system based on gated single photon counting provided by the present disclosure.

In summary, the present disclosure provides a time-to-digital converter system based on gated single-photon technology, in which the signal at the edge of the gated signal is avoided by overlapping the gated signal with the next gated signal. Loss, to obtain a complete echo signal, so that the input pulse can be effectively recorded, improving the conversion efficiency of the time-to-digital converter. The counter array in each exposure mode can be flexibly configured to meet the requirements of the counter counting range under different gating signal widths, thereby reducing the overall requirement for the counter bit width and reducing the required area of the counter array. The anti-overflow design of the counter array can avoid the distortion of the counting statistics due to the long exposure time. The address of the gating signal where the laser echo signal is located can be located by means of peak detection, and the position of the laser echo can be approximated by refining the gating signal into a gating signal of a smaller window, and finally a histogram of only 32 bins is generated. In the third statistical distribution mode, multiple input pulses can be measured at the same time for time-to-digital conversion. The conversion efficiency is high, and events are not easy to be lost, which is conducive to efficient time distribution statistics of events input into the TDC completely and without distortion.

It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referring to the directions of the drawings, not Used to limit the protection scope of this disclosure. Throughout the drawings, the same elements are indicated by the same or similar reference numerals. Where it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted, and the shapes and sizes of components in the drawings do not reflect real sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.

Unless known to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties obtained from the teachings of the present disclosure. Specifically, all numbers used in the specification and claims to indicate the content of components, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. In general, the expressed meaning is meant to include a variation of ±10% in some embodiments, a variation of ±5% in some embodiments, a variation of ±1% in some embodiments, a variation of ±1% in some embodiments, and a variation of ±1% in some embodiments ±0.5% variation in the example.

Words such as "first", "second", "third" and the like used in the description and claims to modify the corresponding elements do not in themselves mean that the elements have any ordinal numbers, nor The use of these ordinal numbers to represent the sequence of an element with respect to another element, or the order of manufacturing methods, is only used to clearly distinguish one element with a certain designation from another element with the same designation.

In addition, unless specifically described or steps that must occur sequentially, the order of the above steps is not limited to that listed above and may be changed or rearranged according to the desired design. Moreover, the above-mentioned embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, technical features in different embodiments can be freely combined to form more embodiments.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above descriptions are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Within the spirit and principles of the present disclosure, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present disclosure.

Claims (10)

1. A time-to-digital converter system based on gating single photon counting, comprising:

a phase-locked loop for multiplying the input system clock signal to generate a first clock signal;

a global gating signal generation module that generates M first gating signals and a laser synchronization trigger signal in response to receiving the first clock signals, the first gating signals being configured to overlap periods of P first clock signals with a next first gating signal, and to make a signal width of each of the first gating signals M times the period of a first clock signal; the laser synchronous trigger signal is suitable for controlling the time of the first laser pulse to emit so as to obtain the time information of the laser emission, wherein M is a positive integer greater than 1, and P is a positive integer greater than or equal to 1;

a time digitizer array comprising a plurality of time digitizers, each adapted to gate count a second laser pulse signal according to a first gate signal and the first clock signal so as to obtain a first statistical distribution of single photons over time;

the first laser pulse signal is reflected by a target to obtain the second laser pulse signal.

2. The time-to-digital converter system of claim 1, each of the time-to-digital converters comprising:

the buffer module is used for responding to the input of the first clock signal and retiming the input M first gating signals to obtain M second gating signals;

a configurable counter array comprising M counter assemblies, each of said counter assemblies being adapted to receive one of said second gating signals for gating counting said second laser pulse signal.

3. The time-to-digital converter system of claim 2, each of the time-to-digital converter arrays further comprising:

and the peak searching module is used for comparing the numerical value of the single photon number obtained by the counter array to obtain the address of the gating signal where the maximum photon numerical value is located.

4. The time-to-digital converter system of claim 3, each of the time-to-digital converters further comprising:

the digital control module is used for generating a mode selection signal according to a sampling mode control instruction input from the outside;

a first mode gating signal generation module, configured to generate 2M third gating signals according to a first maximum gating signal in response to the mode selection signal, where a signal width of each third gating signal is M/8 cycles of the first clock signal, and adjacent third gating signals overlap the cycles of the first clock of P/2, where the first maximum gating signal is obtained by comparing the first statistical distribution by the peak searching module;

A multi-stage gating synchronization module adapted to clock retiming the second gating signal and the third gating signal according to the first clock signal in response to the mode selection signal to align a rising edge of the third gating signal with a rising edge of the second gating signal;

the counter component is adapted to count the second laser pulse signals according to the aligned third gating signals, so as to obtain a second statistical distribution.

5. The time-to-digital converter system of claim 4, further comprising:

a delay phase-locked loop for performing multistage delay on the first clock signal in response to receiving the first clock signal, so as to output a control voltage for controlling a delay unit to perform delay operation;

each of the time-to-digital converters further comprises:

the second mode gating signal generation module is used for inputting a second maximum gating signal to the 4M-stage extended replication chain circuit in response to receiving the mode selection signal, the 4M-stage extended replication chain circuit outputs 4M delay signals under the action of the control voltage, rising edges of the 4M delay signals sample the second laser pulse signal, the position of the rising edge of the second laser pulse signal is detected, and 4M fourth gating signals are correspondingly generated, wherein the second maximum gating signal is obtained by comparing the second statistical distribution through the peak searching module;

The counter component is adapted to count according to a fourth gating signal in coordination with a rising edge of the delay signal to obtain a third statistical distribution.

6. The time to digital converter system of claim 5, wherein the multi-stage gating synchronization module is further adapted to generate a valid count gating signal from the mode selection signal, the second gating signal, the third gating signal, and the fourth gating signal;

each of the counter assemblies includes:

a first data selector configured to receive the mode selection signal to select a count pulse signal including the second laser pulse signal or the delay signal;

a plurality of counters configured to count photons in combination with the active count gating signal and the count pulse signal; and

and the input end of each second data selector is respectively connected with the output end of one counter and the output end of the first data selector, the output end of the second data selector is connected with the input end of the next counter, and the trigger pulse signal is input to the next counter in combination with the mode selection signal.

7. The time-to-digital converter system of claim 6, each of the counters comprising:

a plurality of count D flip-flops, a clock signal input of a first count D flip-flop being configured to be connected to an output of the first data selector to receive the count pulse signal;

the counting data selector takes the output signals of the first output end or the second output end of the first counting D trigger as the data input signals of the first counting D trigger according to the counting type signals, and the data input ends of other counting D triggers respectively receive the output signals of the second output ends;

the second output end of the previous counting D trigger is connected with the clock signal input end of the next counting D trigger, the output end of the first counting D trigger outputs the lowest bit of the counting value, and the output end of the last counting D trigger outputs the highest bit of the counting value.

8. The time-to-digital converter system of claim 3, each of the time-to-digital converters further comprising:

and the data reading module is used for reading out data from the count value generated by the counter assembly or the peak address generated by the peak searching module according to the mode selection signal.

9. The time-to-digital converter system of claim 1, the global gating signal generation module comprising:

the frequency dividing unit is suitable for dividing the first clock signal to obtain a third clock signal;

the generating unit is suitable for generating a plurality of first gating signals according to the third clock signal and the first clock signal, and comprises M generating D flip-flops and M generating OR gates which are respectively arranged at the output end, so that the first gating signals overlap with the next first gating signals for P periods of the first clock signal;

and the laser synchronization unit is suitable for transmitting a laser synchronization trigger signal under the action of the first gating signal and the first clock signal.

10. The time-to-digital converter system of claim 1, further comprising:

and the clock tree is suitable for respectively sending the first clock signal generated by the phase-locked loop and the first gating signal generated by the global gating signal to each time digital converter.

Images