CN116208574A - Message processing method, device, electronic equipment and computer readable storage medium - Google Patents

Abstract

Embodiments of the present invention propose a message processing method, device, electronic equipment, and computer-readable storage medium, which belong to the field of communication technology. In the case of congestion, write the received data packet into the double-rate synchronous dynamic random access memory, and write the header data in the received data packet directly to the central processing unit when the current receiving packet is not in a congested state In the high-speed cache, other data other than the header data are written into the double-rate synchronous dynamic random access memory, so that when the central processing unit processes the service message, the header data is already in the cache, and there is no need to go to the Accessing the double-rate synchronous DRAM to obtain the packet header data can effectively reduce the memory access pressure of the central processing unit on the double-rate synchronous DRAM, thereby improving the overall performance of soft forwarding.

Description

Message processing method, device, electronic device, and computer-readable storage medium

technical field

The present invention relates to the technical field of communications, and in particular, to a message processing method, device, electronic equipment, and computer-readable storage medium.

Background technique

When a network device receives a message, it will store the message information, then identify it based on the stored message information, and perform table lookup and forwarding based on the identification result.

The processing flow of the traditional message soft forwarding is: DMA (Direct Memory Access, direct memory access) controller first writes the packet to DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory), and writes the corresponding After the message, update the DMA descriptor or update the DMA descriptor and provide an interrupt at the same time, the CPU (central processing unit, central processing unit) receives the message by polling the DMA descriptor or the interrupt awareness message provided by the DMA, and then the CPU presses the DMA descriptor Obtain the message data address, read the message data from the DDR, parse and forward the message data. However, due to the long delay for the CPU to read the DDR, the CPU cannot continue to process the received packets before retrieving the data, resulting in CPU resource consumption and a significant drop in overall performance.

Contents of the invention

In view of this, the object of the present invention is to provide a message processing method, device, electronic equipment, and computer-readable storage medium, which can improve the CPU resource consumption caused by the traditional message soft forwarding method and the overall performance is greatly reduced. question.

In order to achieve the above object, the technical solution adopted in the embodiment of the present invention is as follows:

In the first aspect, an embodiment of the present invention provides a message processing method, which is applied to a network device. The network device includes a central processing unit and a double-rate synchronous dynamic random access memory. The method includes:

When it is detected that the external device starts to send data packets of service messages, it is judged whether the current receiving packet is in a congested state;

If not, then receive the data packet, extract the message header data of the service message from the data packet, write the message header data into the cache memory of the central processing unit, and remove all Writing the data packets other than the header data into the double rate synchronous dynamic random access memory;

If yes, the data packet is received, and the data packet is written into the double rate synchronous dynamic random access memory.

Further, the step of receiving the data packet includes:

Using direct memory access, receiving a data packet of a service message sent by an external device, and updating a state value of a DMA descriptor from a first state value to a second state value;

Wherein, the first status value indicates that the message data is in an unfinished state, and the second status value indicates that the message data is received in a completed state;

Before the step of writing the data packet except the header data into the double-rate synchronous DRAM, or before the step of writing the data packet into the double-rate synchronous Before the step of DRAM, the method also includes:

In the double rate synchronous dynamic random access memory, determine the data address of the storage area for storing the data packet.

Further, the step of judging whether the current packet receiving is in a congested state includes:

From all the DMA descriptors, determine the total number of descriptors that represent the completion of message data reception;

Judging whether the total number of descriptors exceeds a preset threshold, if yes, then judging that the current packet receiving is in a congested state, if not, then judging that the current packet receiving is not in a congested state.

Further, the step of writing the header data into the cache of the central processing unit includes:

Sending the header data and the data address to the bus; wherein the data address is the address of the storage area for storing the data packet in the double rate synchronous dynamic random access memory;

Through the bus, according to the data address, the header data is stored in the allocated specific area in the cache memory of the central processing unit.

Further, before the step of sending the header data and data address to the bus, the method includes:

A free specific area is allocated for the packet header data from the cache memory of the central processing unit.

Further, the step of extracting the header data of the service message from the data packet includes:

Taking the start field of the data packet as the starting point of the message header, extracting data with a preset length from the data packet as the message header data.

In a second aspect, an embodiment of the present invention provides a message processing method, which is applied to a network device, where the network device includes a central processing unit and a double-rate synchronous dynamic random access memory, and the method includes:

Polling the DMA descriptor, if the currently polled DMA descriptor is the second state value, then obtain the data address from the DMA descriptor, and determine the service message corresponding to the DMA descriptor; wherein, the The second status value indicates that it is in the status of message data receiving completion;

Identify whether the header data of the service message exists in the cache of the central processing unit, if so, analyze and identify the header data in the cache, and perform table lookup based on the identification result to determine forwarding information;

Obtaining the remaining data of the service message from the storage area corresponding to the data address in the double-rate synchronous dynamic random access memory, editing the remaining data, and obtaining the message to be forwarded;

Based on the forwarding information, forward the message to be forwarded to a next-hop device, set the DMA descriptor to a first state value, and release the data address in the DMA descriptor.

In the third aspect, the embodiment of the present invention provides a message processing device, which is applied to network equipment, and the network device includes a central processing unit and a double-rate synchronous dynamic random access memory, and the message processing device includes a congestion judging module and a memory module;

The congestion judging module is used to judge whether the current receiving packet is in a congested state when it detects that the external device starts to send the data packet of the service message;

The storage module is configured to, if not, receive the data packet, extract the header data of the service message from the data packet, and write the header data into the central processing unit cache, writing the data packet except the header data into the double rate synchronous dynamic random access memory;

The storage module is further configured to receive the data packet if yes, and write the data packet into the double rate synchronous dynamic random access memory.

In a fourth aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory, the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions In order to realize the packet processing method described in the first aspect or the second aspect.

In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the message processing method as described in the first aspect or the second aspect is implemented.

In the message processing method, device, electronic device, and computer-readable storage medium provided by the embodiments of the present invention, when the network device detects that the external device starts to send the data packet of the service message, when the current receiving packet is in a congested state, Write the data packet into the double-rate synchronous dynamic random access memory. When the current packet receiving is not in a congested state, write the header data in the packet directly into the cache memory of the central processing unit, and write the header data into the cache of the central processing unit. Write other data other than the double-rate synchronous dynamic random access memory, so that when the central processor processes the service message, the header data is already in the cache, and there is no need to access the double-rate synchronous dynamic random access memory to obtain The packet header data can effectively reduce the memory access pressure of the central processing unit on the double-rate synchronous dynamic random access memory, thereby improving the overall performance of soft forwarding.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

FIG. 1 shows a schematic block diagram of a packet processing system provided by an embodiment of the present invention.

FIG. 2 shows one of the schematic flowcharts of the message processing method provided by the embodiment of the present invention.

FIG. 3 shows the second schematic flowchart of the message processing method provided by the embodiment of the present invention.

FIG. 4 shows a schematic flowchart of some sub-steps of step S12 in FIG. 2 or FIG. 3 .

FIG. 5 shows one of the schematic flowcharts of some sub-steps of step S14 in FIG. 2 or FIG. 3 .

FIG. 6 shows a schematic structural diagram of packet processing by a network device provided by an embodiment of the present invention.

FIG. 7 shows the second schematic flowchart of some sub-steps of step S14 in FIG. 2 or FIG. 3 shown in FIG. 5 .

FIG. 8 shows the third schematic flowchart of the packet processing method provided by the embodiment of the present invention.

FIG. 9 shows a schematic block diagram of a packet processing device provided by an embodiment of the present invention.

Fig. 10 shows a schematic block diagram of an electronic device provided by an embodiment of the present invention.

Reference signs: 100-message processing system; 110-network equipment; 120-external equipment; 130-message processing device; 140-congestion judgment module; 150-storage module; 160-polling module; 170-identification module; 180-editing module; 190-forwarding module; 200-electronic equipment.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that relative terms such as the terms "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

In the soft forwarding scenario of packets, due to the complexity of services, software is usually used to identify, search, process, edit, and forward service packets.

Due to the complex software processing of service packets (ie soft forwarding) and the huge number of service entries, the soft forwarding process usually includes the following processes: receiving and sending packets on the line side through hardware; storing the packets in storage devices, such as DRAM ;Software-aware message reception; software parses the message stored in the storage device; according to the analysis result, perform business lookup table, and perform business processing and editing on the message, such as flow learning, statistics, in-depth analysis, security policy and processing Decryption; according to the table lookup result, forward the processed and edited message according to the forwarding decision, and complete the message sending.

In the current soft forwarding method of service messages, the DMA controller first writes the data packet of the message to the DDR. After writing the message, it updates the DMA descriptor or updates the DMA descriptor and provides an interrupt at the same time. The CPU polls the DMA The interrupt-aware message provided by the descriptor or DMA is received, and then the CPU obtains the address of the message data according to the DMA descriptor, reads the message data from the DDR, and then parses and forwards the message data. However, due to the long delay for the CPU to read the DDR, the CPU cannot continue to process the received packets before retrieving the data, resulting in CPU resource consumption and a significant drop in overall performance.

In another existing method, part of the key business is usually offloaded to the hardware for execution, and the table lookup message is parsed and edited. However, the router has a large service specification, so hardware entries need to be stored in the SRAM, so the hardware cost is relatively high. In addition, this method can only offload a part of the business, and a large number of business entries are still stored on the DDR, so that the entries on the DDR can easily reach the M level, or even the G level, while most of the services stored in the DDR are still It can only be sent to the CPU for processing. Therefore, there is still the problem of empty CPU resources and a sharp drop in overall performance.

Based on the above considerations, an embodiment of the present invention provides a packet processing method, which can improve the problems of CPU resource consumption and overall performance degradation caused by the current packet soft forwarding method. Hereinafter, this plan will be introduced.

The message processing method provided by the embodiment of the present invention can be applied to the message processing system shown in FIG. 1. The message processing system 100 can include a network device 110 and a plurality of external devices 120. A plurality of external devices 120 are connected in communication, and the network device 110 may include a central processing unit and a double-rate synchronous dynamic random access memory.

The external device 120 may be configured to send a data packet of a service message to the network device 110 .

The network device 110 is used to determine whether the current receiving packet is in a congested state when it detects that the external device 120 starts to send the data packet of the service message, if not, then receives the data packet, and extracts the message of the service message from the data packet header data, write the message header data into the cache memory of the central processing unit, and write the data packets except the message header data into the double-rate synchronous dynamic random access memory.

Wherein, the network device 110 includes, but is not limited to: a switch, a gateway, a terminal device, a server, and the like. Similarly, the external device 120 may include, but is not limited to: an independent server, a server cluster, a terminal device, a wearable portable device, a personal computer, a notebook computer, a mobile terminal, a switch, a gateway, and the like.

In a possible implementation manner, an embodiment of the present invention provides a packet processing method. Referring to FIG. 2 , the packet processing method may include the following steps. In this implementation manner, it is described by taking the packet processing method applied to the network device 110 in FIG. 1 as an example.

S12. When it is detected that the external device starts to send the data packet of the service message, it is judged whether the current receiving packet is in a congested state. If not, execute step S14, and if yes, execute step S16.

It should be noted that, in this embodiment, the data packet has been received means that the data packet has been received but not stored in any storage device. The current packet receiving refers to a series of processing procedures of packet receiving, packet storage, and packet forwarding.

S14, receiving the data packet, extracting the message header data of the service message from the data packet, writing the message header data into the cache memory of the central processing unit, and writing the data packets other than the message header data into double rate synchronous DRAM.

S16, receiving the data packet, and writing the data packet into the double rate synchronous dynamic random access memory.

When the network device 110 detects that any external device 120 starts to send a data packet of a service message, and the data packet has not been received and stored, if the current packet receiving service of the network device 110 is not in a congested state, the Extract the message header data in the packet, write the message header data directly in the cache memory of the central processing unit, and write the message body data (in this embodiment, the message body) except the message header data in the data packet The data refers to the data except the header data in the data packet) written into the double-rate synchronous dynamic random access memory. If the current packet receiving service of the network device 110 is in a congested state, all data packets are written into the double-rate synchronous DRAM.

Compared with the traditional message soft forwarding method, the message processing method provided by the embodiment of the present invention directly writes the message header data of the received service message into the central processing unit when the current packet receiving is not in a congested state High-speed cache, so that when the central processor processes the service message, the header data is already in the cache, and there is no need to access the double-speed synchronous dynamic random access memory to obtain the header data, which can effectively reduce the central processor's double Double rate synchronous DRAM access pressure, which can improve the overall performance of soft forwarding.

In order to implement soft forwarding of packets more efficiently, in a possible implementation manner, direct memory access and DMA descriptors are introduced, and a certain number of DMA descriptors are preset in the network device 110 . The DMA descriptor may include, but is not limited to: a status value used to represent the processing status of the service message, and a data address of a storage area used to record the data packet of the service message.

For example, the state value may include a first state value "0" and a second state value "1". Data receiving completion status. When the status value is the first status value "0", the data address in the DMA descriptor is empty. When the state value is the second state value "1", the data address in the DMA descriptor is not empty, which means that the packet data corresponding to the data address is in the state of waiting to be processed, edited and forwarded.

It should be noted that all DMA descriptors in the network device 110 may have a sequence relationship, and may be in a circular order, and each DMA descriptor may record the identifier or address of the subsequent descriptor. Take a total of three DMA descriptors with serial numbers 1, 2, and 3 as an example. The DMA descriptor with serial number 1 records the identifier or address of the DMA descriptor with serial number 2, and the DMA descriptor with serial number 2 records The identifier or address of the DMA descriptor with the sequence number 3, and the identifier or address of the DMA descriptor with the sequence number 1 is recorded in the DMA descriptor with the sequence number 3, so as to form a circular sequence.

Further, referring to FIG. 3, in steps S14 and S16, receiving the data packet may be further implemented as: using direct memory access, receiving the data packet of the service message sent by the external device, and changing the state value of a DMA descriptor from the first The state value is updated to the second state value.

In this embodiment, the first status value indicates that the message data is in an unfinished state, and the second status value indicates that the message data reception is completed. Moreover, step S14 may include step S141 and step S142, and step S16 may include step S161 and step S162.

S141. Using direct memory access, receive a data packet of a service message sent by an external device, and update a state value of a DMA descriptor from a first state value to a second state value.

S142, extracting the message header data of the service message from the data packet, writing the message header data into the cache memory of the central processing unit, and writing the data packets other than the message header data into the double-rate synchronous dynamic random memory.

S161. Using direct memory access, receive a data packet of a service message sent by an external device, and update a state value of a DMA descriptor from a first state value to a second state value.

S162, writing the data packet into the double rate synchronous dynamic random access memory.

Direct memory access (Direct Memory Access, DMA), that is, the network device 110 receives a data packet of a service message sent by the external device 120 through the DMA RING.

It should be understood that the DMA descriptor selected in step S141 and step S161 is a DMA descriptor with a state value of the first state value. The way to select the DMA descriptor can be flexibly selected. For example, it can be a DMA descriptor with the first state value after the DMA descriptor whose state value is the second state value, or a DMA descriptor whose state value is the first state value. A DMA descriptor randomly selected from all DMA descriptions of a state value is not specifically limited in this embodiment.

Further, in the above-mentioned step S142, before the data packets other than the header data are written into the double-rate synchronous dynamic random access memory, and in step S16, the data packets are written into the double-rate synchronous dynamic random access memory Before, it may also include: determining the data address of the storage area for storing the data packet in the double rate synchronous dynamic random access memory.

The network device 110 can determine the free storage area in the double-rate synchronous DRAM by means of monitoring or recording, so that all storage areas in the double-rate synchronous DRAM can be obtained from any storage method such as length matching and sequential storage. The free storage area determines the storage area used to store the entire data packet or the message body data in the data packet.

It should be noted that the DMA descriptor in step S141 and step S161 may include the data address of the storage area for storing the data packet or the header data in the data packet, and the storage area may be the data address of the storage area determined , it is written into the DMA descriptor by the hardware in real time, or it can be written into the DMA descriptor in advance. For the case where the data address is written into the DMA descriptor in advance, it can be that when the DMA descriptor is switched from the second state value to the first state value, all idle storage of the DRAM is synchronized from the double rate by the CPU or hardware After a storage area is randomly determined in the area, the data address of the storage area is filled in the DMA descriptor.

For each service message sent by the external device 120, there is a corresponding DMA descriptor to record information such as the storage area and status value of the service message.

In a possible implementation manner, in order to quickly and accurately determine the current state of receiving packets, a threshold is introduced, and the DMA RING may be pre-configured with a threshold, that is, Threshold. On this basis, referring to FIG. 4 , it can be judged whether the current packet receiving is in a congested state through the following steps.

S121. From all the DMA descriptors, determine the total number of descriptors indicating that the message data reception is completed.

S122. Determine whether the total number of descriptors exceeds a preset threshold. If yes, execute step S123; if not, execute step S124.

S123. Determine that the current packet receiving is in a congested state.

S124. Determine that the current packet receiving is not in a congested state.

From all DMA descriptors configured on the network device 110, determine the total number of DMA descriptors whose state value is the second state value as the total number of descriptors. When the total number of descriptors is less than or equal to the threshold threshold, the current packet receiving is not in a congestion state (burst state), that is, the central processing unit has not yet reached the upper limit of memory access to the double-rate synchronous dynamic random access memory, otherwise, the current receiving packet is a congestion state, that is, the central processing unit accesses the double-rate synchronous dynamic random access memory The memory access limit has been reached.

For step S14, the method of extracting the header data from the data packet can be flexibly selected. For example, the specified field can be used as the header data, or a field with a preset length can be used as the header data. In this embodiment , without specific limitations.

In a possible implementation manner, extracting the message header data of the service message from the data packet can be further implemented as: taking the start field of the data packet as the starting point of the message header, and extracting Set the length of the data as the header data.

The data in the data packet except the message header is the message body data of the service message.

Further, for step S142, referring to FIG. 5 , writing the packet header data into the cache memory of the central processing unit may be implemented through the following steps.

S1422. Send the packet header data and data address to the bus.

It should be noted that the data address is an address of a storage area in the double-rate synchronous DRAM for storing the data packet.

S1424. Store the packet header data in the allocated specific area in the cache memory of the central processing unit according to the data address through the bus.

After the bus receives the data address and the packet header data, according to the data address, the packet header data is stored in the allocated specific area in the cache memory of the central processing unit.

Referring to FIG. 6 , the central processing unit may include multiple cores, and each core may include multiple cache areas (also called cache lines, Cache Lines), and each cache line may store data of a certain length.

For step S1422, for the message header data of each service message, when the length of the message header data exceeds the length of a cache line, the DMA controller can divide the message header data into multiple pieces of data, thereby sending one section at a time In the way of data, the DMA controller sends the data address and header data to the bus through multiple transfers. For example, the DMA controller can send the data address and header data to the bus through the typical entity of ARM, that is, the ACE5-LiteACP Master interface.

After the bus receives the data address and the header data, the header data is written into the CPU's cache ( Cache) in the allocated specific area.

Further, referring to FIG. 7, before step S142, step S141 may also be included.

S1421. Allocate a free specific area for the packet header data from the cache memory of the central processing unit.

The method of allocating a free specific area for the header data can be flexibly set, for example, the central processor can randomly select from the area where no data is stored in the cache, or the data of the service message can be received in the DMA RING DMA RING can allocate a specific area from the area where data is not stored in the cache according to the monitoring results of the cache. In this embodiment, it is not specifically limited.

In a possible implementation, when the DMA RING or the central processor determines that a free specific area is allocated for the header data, the cache address of the specific area can be paired with the data address of the storage area for storing the message body data The relationship is notified to the bus, so that when the bus receives the data address and message header data, it can determine the cache address paired with the data address according to the data address, and write the message header data into the cache corresponding to the cache address cache area.

In the above message processing method provided by the embodiment of the present invention, according to the backlog of unprocessed DMA descriptors of DMA RING and the pre-configured threshold threshold, it is determined whether the current received packet is in a congested state, and then in a non-congested state, through the bus The instruction writes the corresponding packet header data directly into the CPU cache when receiving the packet, so that when the CPU perceives that the packet is received, the packet header data is already in the CPU cache, and there is no need to access the DDR to Obtaining the packet header is the data, which can effectively reduce the memory access delay when the CPU processes the packet, thereby greatly improving the soft forwarding efficiency and improving the overall forwarding bandwidth and forwarding performance.

In a possible implementation manner, an embodiment of the present invention further provides a packet processing method, referring to FIG. 8 , which may include the following steps. In this implementation manner, the packet processing method may be applied to the network device 110 in FIG. 1 . Moreover, the network device 110 at this time stores the data packets of the service messages sent by the external device 120 by using the message processing method provided in the above-mentioned embodiment.

S21. Poll the DMA descriptor. If the currently polled DMA descriptor is the second state value, obtain a data address from the DMA descriptor, and determine a service packet corresponding to the DMA descriptor.

Wherein, the second status value indicates that it is in the status of receiving the message data. After the data address is obtained, the service message corresponding to the DMA descriptor can be determined.

S23. Identify whether the header data of the service message exists in the cache of the central processing unit. If yes, analyze and identify the header data in the cache, and perform table lookup based on the identification result to determine forwarding information.

S25. Obtain the remaining data of the service message from the storage area corresponding to the data address in the double-rate synchronous DRAM, edit the remaining data, and obtain the message to be forwarded.

It should be noted that the remaining data refers to the message body data in the data packet of the service message except the message header data. Step S25 and step S23 may be executed simultaneously, or may be executed successively.

S27. Based on the forwarding information, forward the packet to be forwarded to the next-hop device, set the DMA descriptor as the first state value, and release the data address in the DMA descriptor.

In this embodiment, the first status value indicates that the message data reception is not completed.

For step S23, if not, then obtain the data packet of the service message from the storage area corresponding to the data address in the double-rate synchronous dynamic random access memory (DDR), analyze, identify, look up and edit the data packet, and obtain the data packet to be processed. Forward the message and the forwarding information, and then forward the message to be forwarded to the next-hop device based on the forwarding information.

Through the above steps S21-S27, when the state value of the currently polled DMA descriptor indicates that it is in the state of message data reception completion, and the message header data of the message described by the DMA descriptor is in the cache of the CPU , the network device 110 can directly process the packet header data in the cache to obtain the forwarding information, and then based on the forwarding information, edit the remaining data to obtain the packet to be forwarded, so that during the packet forwarding process, the network When the device 110 accesses the DDR, it only needs to obtain the remaining data, which can effectively reduce the access pressure on the DDR, thereby greatly improving the soft forwarding efficiency, overall forwarding bandwidth and forwarding performance of the network device 110 .

Based on the same inventive concept as the packet processing method above, in a possible implementation manner, an embodiment of the present invention further provides a packet processing apparatus 130, which may be applied to the network device 110 in FIG. 1 . Referring to FIG. 9 , the packet processing device 130 may include a congestion judging module 140 and a storage module 150 .

The congestion judging module 140 is configured to judge whether the current packet receiving is in a congested state when it detects that the external device starts to send data packets of service messages.

The storage module 150 is used to receive the data packet when the current packet receiving is not in a congested state, extract the header data of the service message from the data packet, and write the header data into the cache memory of the central processing unit , writing the data packets except the packet header data into the double-rate synchronous dynamic random access memory.

The storage module 150 is also configured to receive data packets and write the data packets into the double-rate synchronous dynamic random access memory (DRAM) when the current packet receiving is in a congested state.

Further, the packet processing device 130 may further include a polling module 160 , an identification module 170 , an editing module 180 and a forwarding module 190 .

The polling module 160 is configured to poll the DMA descriptor, if the currently polled DMA descriptor is the second state value, obtain the data address from the DMA descriptor, and determine the service message corresponding to the DMA descriptor. Wherein, the second status value indicates that it is in the status of receiving the message data.

The identification module 170 is used to identify whether the header data of the service message exists in the cache of the central processing unit, if so, analyze and identify the header data in the cache, and perform table lookup based on the identification result , to determine the forwarding information.

The editing module 180 is configured to acquire the remaining data of the service message from the storage area corresponding to the data address in the double-rate synchronous dynamic random access memory, edit the remaining data, and obtain the message to be forwarded.

The forwarding module 190 is configured to forward the packet to be forwarded to the next-hop device based on the forwarding information, set the DMA descriptor to the first state value, and release the data address in the DMA descriptor. Wherein, the first status value indicates that it is in a status of receiving unfinished message data.

In the above message processing device 130, through the synergistic effect of the congestion judging module 140, the storage module 150, the polling module 160, the identification module 170, the editing module 180 and the forwarding module 190, when the current received packet is not in a congested state, directly send the The message header data of the received service message is written into the cache of the central processor, so that when the central processor processes the service message, the message header data is already in the cache, and there is no need to access the double-rate synchronous dynamic random Using the memory to obtain the packet header data can effectively reduce the memory access pressure of the central processing unit on the double-rate synchronous dynamic random access memory, thereby improving the overall performance of soft forwarding.

For specific limitations of the packet processing device 130, reference may be made to the foregoing limitations on the packet processing method, which will not be repeated here. Each module in the above-mentioned packet processing device 130 may be fully or partially implemented by software, hardware or a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the electronic device in the form of hardware, and can also be stored in the memory of the electronic device in the form of software, so that the processor can invoke and execute the corresponding operations of the above-mentioned modules.

In one implementation manner, an electronic device 200 is provided. The electronic device 200 may be a terminal, and its internal structure may be as shown in FIG. 10 . The electronic device 200 includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Wherein, the processor of the electronic device 200 is used to provide calculation and control capabilities. The memory of the electronic device 200 includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the electronic device 200 is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, operator network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, the packet processing method provided in the foregoing implementation manner is implemented.

The structure shown in FIG. 10 is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation on the electronic device 200 to which the solution of the present invention is applied. The specific electronic device 200 may include More or fewer components are shown, or certain components are combined, or have different component arrangements.

In an implementation manner, the message processing apparatus 130 provided by the present invention may be implemented in the form of a computer program, and the computer program may run on the electronic device 200 shown in FIG. 10 . The memory of the electronic device 200 can store the various program modules that make up the message processing device 130, such as the congestion judgment module 140, storage module 150, polling module 160, identification module 170, editing module 180 and forwarding module shown in FIG. Module 190. The computer program constituted by each program module causes the processor to execute the steps in the message processing method described in this specification.

For example, the electronic device 200 shown in FIG. 10 may execute step S12 through the congestion judging module 140 in the packet processing apparatus 130 shown in FIG. 8 . The electronic device 200 may perform steps S14 and S16 through the storage module 150 . The electronic device 200 may execute step S21 through the polling module 160 . The electronic device 200 may execute step S23 through the identification module 170 . The electronic device 200 may execute step S25 through the editing module 180 . The electronic device 200 may execute step S27 through the forwarding module 190 .

In one embodiment, an electronic device 200 is provided, including a memory and a graphics processor, the memory stores machine-executable instructions, and the processor implements the following steps when executing the machine-executable instructions: it is detected that the external device starts to send When receiving a data packet of a business message, it is judged whether the current receiving packet is in a congested state; if not, the data packet is received, the header data of the business message is extracted from the data packet, and the header data is written into the central processing unit cache, write the data packet except the header data into the double-rate synchronous DRAM; if so, receive the data packet and write the data packet into the double-rate synchronous DRAM.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a graphics processor, the following steps are implemented: when it is detected that an external device starts to send a data packet of a service message, Determine whether the current receiving packet is in a congested state; if not, receive the data packet, extract the header data of the service message from the data packet, write the header data into the cache of the central processing unit, and delete the packet The data packet other than the header data is written into the double-rate synchronous dynamic random access memory; if so, the data packet is written into the double-rate synchronous dynamic random access memory.

In one embodiment, an electronic device 200 is provided, including a memory and a graphics processor, the memory stores machine-executable instructions, and the processor implements the following steps when executing the machine-executable instructions: polling the DMA descriptor, If the DMA descriptor of current polling is the second state value, then obtain the data address from the DMA descriptor, and determine the corresponding business message of the DMA descriptor; identify whether there is a business message in the cache memory of the central processing unit Message header data, if yes, then analyze and identify the message header data in the cache, and look up the table based on the identification result to determine the forwarding information; from the storage area corresponding to the data address in the double rate synchronous dynamic random access memory Obtain the remaining data of the service message, edit the remaining data, and obtain the message to be forwarded; based on the forwarding information, forward the message to be forwarded to the next hop device, set the DMA descriptor to the first state value, and release the DMA The address of the data in the descriptor.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a graphics processor, the following steps are implemented: polling DMA descriptors, if the currently polled DMA descriptor is the second state value, then obtain the data address from the DMA descriptor, and determine the corresponding service message of the DMA descriptor; identify whether the message header data of the service message exists in the cache memory of the central processing unit, if so, then Analyze and identify the message header data in the cache, and look up the table based on the identification result to determine the forwarding information; obtain the remaining data of the service message from the storage area corresponding to the data address in the double-rate synchronous dynamic random access memory, Edit the remaining data to obtain the message to be forwarded; based on the forwarding information, forward the message to be forwarded to the next hop device, set the DMA descriptor to the first state value, and release the data address in the DMA descriptor.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functions and possible implementations of devices, methods and computer program products according to multiple embodiments of the present invention. operate. In this regard, each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. It should also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.

In addition, each functional module in each embodiment of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device 110, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. The message processing method is characterized by being applied to network equipment, wherein the network equipment comprises a central processing unit and a double-rate synchronous dynamic random access memory, and the method comprises the following steps:

when the data packet of the service message is monitored to be sent by the external equipment, judging whether the current received packet is in a congestion state or not;

if not, receiving the data packet, extracting the message header data of the service message from the data packet, writing the message header data into a cache of the central processing unit, and writing the data packet except the message header data into the double-rate synchronous dynamic random access memory;

if yes, the data packet is received, and the data packet is written into the double-rate synchronous dynamic random access memory.

2. The method of claim 1, wherein the step of receiving the data packet comprises:

adopting direct memory access, receiving a data packet of a service message sent by external equipment, and updating a state value of a DMA descriptor from a first state value to a second state value;

the first state value represents that the message data receiving state is not completed, and the second state value represents that the message data receiving state is completed;

Before the step of writing the data packet except the header data into the double rate synchronous dynamic random access memory, or before the step of writing the data packet into the double rate synchronous dynamic random access memory, the method further comprises:

and determining the data address of the storage area for storing the data packet in the double-rate synchronous dynamic random access memory.

3. The method for processing a packet according to claim 1 or 2, wherein the step of determining whether the currently received packet is in a congestion state comprises:

determining the total number of descriptors representing the completion state of receiving the message data from all DMA descriptors;

and judging whether the total number of the descriptors exceeds a preset threshold value, if so, judging that the current received packet is in a congestion state, and if not, judging that the current received packet is not in the congestion state.

4. The method according to claim 1 or 2, wherein the step of writing the header data into the cache of the central processing unit comprises:

transmitting the message header data and the data address to a bus; the data address is an address of a storage area storing the data packet in the double-rate synchronous dynamic random access memory;

And storing the header data into the allocated specific area in the cache of the central processing unit through the bus according to the data address.

5. The message processing method according to claim 4, wherein before the step of sending the header data and the data address to the bus, the method comprises:

and allocating a free specific area for the message header data from the cache of the central processing unit.

6. The method for processing a packet according to claim 1 or 2, wherein the step of extracting header data of the service packet from the data packet includes:

and extracting data with the length of a preset length from the data packet by taking the initial field of the data packet as a message header starting point.

7. A method for processing a message, the method being applied to a network device, the network device including a central processing unit and a double rate synchronous dynamic random access memory, the method comprising:

polling a DMA descriptor, if the currently polled DMA descriptor is a second state value, acquiring a data address from the DMA descriptor, and determining a service message corresponding to the DMA descriptor; wherein, the second state value representation is in a message data receiving completion state;

Identifying whether the message header data of the service message exists in a cache of the central processing unit, if so, analyzing and identifying the message header data in the cache, and looking up a table based on an identification result to determine forwarding information;

obtaining the residual data of the service message from a storage area corresponding to the data address in the double-rate synchronous dynamic random access memory, and editing the residual data to obtain a message to be forwarded;

and forwarding the message to be forwarded to next-hop equipment based on the forwarding information, setting the DMA descriptor as a first state value, and releasing a data address in the DMA descriptor.

8. The message processing device is characterized by being applied to network equipment, wherein the network equipment comprises a central processing unit and a double-rate synchronous dynamic random access memory, and the message processing device comprises a congestion judging module and a storage module;

the congestion judging module is used for judging whether the current received packet is in a congestion state or not when the data packet of the service message is monitored to be sent by the external equipment;

the storage module is used for receiving the data packet, extracting the message header data of the service message from the data packet, writing the message header data into the cache of the central processing unit, and writing the data packet except the message header data into the double-rate synchronous dynamic random access memory if not;

And the storage module is also used for receiving the data packet if yes, and writing the data packet into the double-rate synchronous dynamic random access memory.

9. An electronic device comprising a processor and a memory, the memory storing machine executable instructions executable by the processor to implement the message processing method of any of claims 1 to 7.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the message processing method according to any of claims 1 to 7.

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