CN116190371A - Layout pattern of static random access memory - Google Patents

Abstract

A layout pattern of a static random access memory (static random-access memory, SRAM), including a substrate, PL1 (first pull-up transistor), PD1 (first pull-down transistor), PL2 (second pull-up transistor) and PD2 (second pull-down transistor) is located on the substrate, and also includes PG1A (first access transistor), PB1B (second access transistor), PG2A (third access transistor) and PG2B (fourth access transistor), PG1A includes the same first fin structure as PG1B, PG2A and PG2B include the same second fin structure, the first local interconnect layer is located between PG1A and PG1B and on the fin structure included in PL1 and PD1, and The second local interconnect layer is located between PG2A and PG2B and on the fin structures included in PL2 and PD2.

Description

Layout pattern of static random access memory

technical field

The present invention relates to a static random access memory (static random access memory, SRAM), in particular to a layout pattern of the static random access memory (SRAM) with increased yield and improved reading speed.

Background technique

An embedded static random access memory (embedded static random access memory, embedded SRAM) includes a logic circuit and the static random access memory connected to the logic circuit. The SRAM itself is a volatile memory cell, that is, when the power supplied to the SRAM disappears, the stored data will be erased at the same time. Static random access memory stores data by using the conductive state of the transistor in the storage unit. The design of static random access memory is based on mutual coupling transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep the data. Loss, that is, the action of not needing to update the memory, is different from that of the dynamic random access memory (DRAM), which is also a volatile memory, by using the charged state of the capacitor to store data. The access speed of the static random access memory is quite fast, so it is used as a cache memory in a computer system.

However, with the shrinking of the manufacturing process line width and the exposure pitch, it is difficult to use the existing structure to expose the desired pattern in the manufacture of SRAM devices. Therefore, how to improve the structure of the existing SRAM device to improve the quality of exposure is an important issue nowadays.

Contents of the invention

The present invention provides a static random-access memory (static random-access memory, SRAM) layout pattern, including a substrate, a first inverter includes a PL1 (first pull-up transistor) and a PD1 (first pull-up transistor) pull transistor) on the substrate, a second inverter includes a PL2 (second pull-up transistor) and a PD2 (second pull-down transistor) on the substrate, wherein the first inverter and the second inverter The phasers are coupled to each other, a PG1A (the first access transistor) and a PG1B (the second access transistor) are connected to the output of the first inverter, a PG2A (the third access transistor) and a PG2B (the fourth Access transistor) is connected to the output terminal of the second inverter, wherein a gate of the PG1A and a gate of the PG2A are connected to a first word line, a gate of the PG1B and a gate of the PG2B Connected to a second word line, a plurality of transistors, including the PL1, the PD1, the PL2, the PD2, the PG1A, the PG1B, the PG2A, and the PG2B, each of the transistors includes a gate structure spanning at least one fin structure, wherein the PG1A and the PG1B include a same first fin structure, the PG2A and the PG2B include a same second fin structure, a first local interconnect layer, located between the PG1A and the PG1B , located on the first fin structure included in the PG1A and the PG1B, and located on the fin structure included in the PL1 and the PD1, wherein the first local interconnect layer is an integrally formed structure, and a A second local interconnection layer located between the PG2A and the PG2B, on the second fin structure included in the PG2A and the PG2B, and on the fin structure included in the PL2 and the PD2, wherein The second local interconnect layer is an integrally formed structure.

The present invention also provides a static random-access memory (static random-access memory, SRAM) layout pattern, including a substrate, a first inverter including a PL1 (first pull-up transistor) and a PD1 (first pull-up transistor) pull-down transistor) on the substrate, a second inverter includes a PL2 (second pull-up transistor) and a PD2 (second pull-down transistor) on the substrate, wherein the first inverter and the second The inverters are coupled to each other, a PG1A (the first access transistor) and a PG1B (the second access transistor) are connected to the output of the first inverter, a PG2A (the third access transistor) and a PG2B (the second access transistor) Four access transistors) are connected to the second inverter output, wherein a gate of the PG1A and a gate of the PG2A are connected to a first word line, a gate of the PG1B and a gate of the PG2B pole is connected to a second word line, a plurality of transistors, including the PL1, the PD1, the PL2, the PD2, the PG1A, the PG1B, the PG2A, and the PG2B, each of which includes a gate structure spanning at least one Diffusion regions, wherein the PG1A and the PG1B include a same first diffusion region, the PG2A and the PG2B include a same second diffusion region, a first local interconnection layer between the PG1A and the PG1B, at On the first diffusion region included in the PG1A and the PG1B, and on the diffusion region included in the PL1 and the PD1, wherein the first local interconnect layer is an integrally formed structure, and a second local interconnect a connecting layer located between the PG2A and the PG2B, on the second diffusion region included in the PG2A and the PG2B, and on the diffusion region included in the PL2 and the PD2, wherein the second local interconnect Layers are a monolithic structure.

One of the features of the present invention is that the first access transistor and the second access transistor share the same fin structure. Likewise, the third access transistor and the fourth access transistor PG2B share the same fin structure. The applicant found that, through the above configuration, the symmetry of the arrangement of each element is high, and when a signal is generated, the length of the signal path passing through each access transistor is approximately equal. Therefore, when the static random access memory is operated, errors caused by different lengths of signal paths can be reduced, and the yield rate of the static random access memory can be improved.

Description of drawings

Fig. 1 is a circuit diagram of a group of eight-transistor SRAM (eight-transistor SRAM, 8T-SRAM) memory cells in the SRAM of the present invention;

FIG. 2 is a layout diagram of a static random access memory according to the first preferred embodiment of the present invention;

Fig. 3 is the sectional view obtained along the sectional line A-A ' of Fig. 2;

FIG. 4 is a schematic diagram of when each signal flows from each bit line to the voltage source Vss;

FIG. 5 is a layout diagram of a SRAM according to the first preferred embodiment of the present invention;

FIG. 6 is a layout diagram of a static random access memory according to another preferred embodiment of the present invention;

Fig. 7 is a sectional view taken along the section line B-B' of Fig. 6 .

Description of main component symbols

10: Eight-transistor static random access memory cell

10': Eight-transistor static random access memory cell

24: storage node

26: storage node

28: Series connection circuit

30: Series connection circuit

50: area

50': area

52: base

54: fin structure

54A: first fin structure

54B: First fin structure

56: Gate structure

56A: First gate structure

56B: Second gate structure

56C: Third gate structure

56D: Fourth gate structure

56E: Fifth gate structure

56F: sixth gate structure

60: The first local interconnect layer

60A: Part I

60B: Part Two

61:Second local interconnection layer

61A: Part 1

61B: Part Two

62: contact column

63: Contact layer

63A: Contact structure

63B: Contact structure

63C: Contact structure

63D: Contact Structures

64A: Dummy contact structure

64B: Dummy contact structure

65A: Dummy layer

65B: Dummy layer

70: The first dielectric layer

70A: signal

70B: signal

70C: signal

70D: signal

72: Second dielectric layer

74: The third dielectric layer

75: Through hole plug

76: The fourth dielectric layer

80: metal wire

80A: metal wire

80B: metal wire

80C: metal wire

80D: metal wire

82A: virtual line

82B: Dotted line

90: Diffusion zone

90A: First Diffusion Zone

90B: second diffusion area

PL1: first pull-up transistor

PL2: Second pull-up transistor

PD1: first pull-down transistor

PD2: second pull-down transistor

PG1A: first access transistor

PG1B: second access transistor

PG2A: third access transistor

PG2B: fourth access transistor

Vcc: voltage source

Vss: voltage source

WL1: character line

WL2: character line

BL1: bit line

BL2: bit line

BL3: bit line

BL4: bit line

G1: First Gap

G2: Second Gap

G3: third gap

G4: Fourth Gap

Detailed ways

In order to enable those skilled in the art who are familiar with the present invention to further understand the present invention, the preferred embodiments of the present invention are specifically listed below, together with the accompanying drawings, to describe in detail the composition and desired effects of the present invention.

For the convenience of description, the drawings of the present invention are only schematic diagrams for easier understanding of the present invention, and the detailed proportions thereof can be adjusted according to design requirements. Those skilled in the art should be able to understand the upper and lower relationships of relative elements in the figures described in the text to refer to the relative positions of objects, so they can be turned over to present the same components, which should all be disclosed in this specification The range is described here.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of a group of eight-transistor SRAM (8T-SRAM) memory cells in the SRAM of the present invention, and FIG. 2 is a preferred implementation of the present invention. A layout diagram of an example static random access memory.

As shown in FIG. 1 and FIG. 2, the SRAM of the present invention preferably includes at least one group of SRAM cells, wherein each SRAM cell includes an eight-transistor SRAM cell ( eight-transistor SRAM, 8T-SRAM) 10.

Please refer to FIG. 1, in this embodiment, each 8T-SRAM memory cell 10 is preferably composed of a first pull-up transistor (pull-up transistor) PL1, a second pull-up transistor PL2, a first pull-up transistor ( pull-down transistor) PD1, a second pull-down transistor PD2, a first access transistor (pass gate transistor) PG1A, a second access transistor PG1B, a third access transistor PG2A and a fourth access transistor PG2B Flip-flop, wherein the first pull-up transistor PL1 and the second pull-up transistor PL2, the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit (latch), so that data can be latched in Storage Node (storage Node) 24 or 26 . In addition, the first pull-up transistor PL1 and the second pull-up transistor PL2 are used as active loads, and they can also be replaced by general resistors as pull-up transistors. In this case, it is a four-transistor SRAM (four -transistor SRAM, 4T-SRAM). In addition, in this embodiment, each source region of the first pull-up transistor PL1 and the second pull-up transistor PL2 is electrically connected to a voltage source Vcc, and each source region of the first pull-down transistor PD1 and the second pull-down transistor PD2 The pole region is electrically connected to a voltage source Vss.

In one embodiment, the first pull-up transistor PL1 and the second pull-up transistor PL2 of the 8T-SRAM memory unit 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, and the second pull-up transistor PL2 The first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A and the fourth access transistor PG2B are made of N-type metal oxide semiconductor (NMOS) -type metaloxide semiconductor, NMOS) transistors, but the present invention is not limited thereto. Wherein, the first pull-up transistor PL1 and the first pull-down transistor PD1 together form an inverter, and the two terminals of the series circuit 28 formed by the two are respectively coupled to a voltage source Vcc and a voltage source Vss; similarly, the second pull-up transistor PL2 and the second pull-down transistor PD2 form another inverter, and the two terminals of the series circuit 30 formed by the two are also coupled to the voltage source Vcc and the voltage source respectively Vss. The above access transistors (including the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A and the fourth access transistor PG2B) are respectively connected to the output ends of the two mutually coupled inverters, Each of the pull-up transistors, each of the pull-down transistors and each of the access transistors includes a gate structure spanning at least one fin structure, and forms a fin transistor (FinFET).

In addition, at the storage node 24, the gates of the second pull-down transistor PD2 and the second pull-up transistor PL2, as well as the first pull-down transistor PD1, the first pull-up transistor PL1 and the first access The drains (Drain) of the transistor PG1A and the second access transistor PG1B; similarly, on the storage node 26, the gates of the first pull-down transistor PD1 and the first pull-up transistor PL1 are also electrically connected respectively, and the second The drains of the pull-down transistor PD2, the second pull-up transistor PL2, the third access transistor PG2A, and the fourth access transistor PG2B. The gates of the first access transistor PG1A and the third access transistor PG2A are respectively coupled to a word line (Word Line) WL1, and the gates of the second access transistor PG1B and the fourth access transistor PG2B are respectively coupled to connected to a word line (Word Line) WL2, and the source (Source) of the first access transistor PG1A is coupled to the corresponding bit line (Bit Line) BL1, and the source of the second access transistor PG1B is coupled to To the corresponding bit line BL2, the source of the third access transistor PG2A is coupled to the corresponding bit line BL3, and the source of the fourth access transistor PG2B is coupled to the corresponding bit line BL4.

Please refer to FIG. 2, in the present embodiment, the 8T-SRAM memory cell 10 is located in a region 50, and is arranged on a substrate 52, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and the substrate 52 is provided with multiple The fin structures 54 are arranged parallel to each other, and shallow trench isolation (not shown) is provided around each fin structure 54 .

In addition, the substrate 52 includes a plurality of gate structures 56, and each of the above-mentioned transistors (including the first pull-up transistor PL1, the first pull-down transistor PD1, the second pull-up transistor PL2, the second pull-down transistor PD2, the first access The transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, and the fourth access transistor PG2B) all include a gate structure 56 spanning at least one fin structure 54 to form each transistor.

As shown in FIG. 2, in order to clearly define the position of each gate structure 56, the gate structure 56 is divided into a first gate structure 56A, a second gate structure 56B, a third gate structure 56C, and a fourth gate structure. 56D, a fifth gate structure 56E and a sixth gate structure 56F. The first gate structure 56A straddles the fin structure 54 to form the first access transistor PG1A; the second gate structure 56B spans the fin structure 54 to form the second access transistor PG1B; the third gate structure 56C spans The third access transistor PG2A is formed on the fin structure 54; the fourth gate structure 56D straddles the fin structure 54 to form the fourth access transistor PG2B; the fifth gate structure 56E straddles at least two different fin structures On the structure 54, the second pull-up transistor PL2 and the second pull-down transistor PD2 are formed; the sixth gate structure 56F spans at least two different fin structures 54 to form the first pull-up transistor PL1 and the first pull-down transistor PD1. It can be understood that, the first gate structure 56A to the sixth gate structure 56F all belong to the gate structure 56 .

In the present invention, each gate structure 56 is arranged along a first direction (for example, X axis), and each fin structure 54 is arranged along a second direction (for example, Y axis). Preferably, the first direction and the second direction are perpendicular to each other.

In addition, when fabricating the first gate structure 56A to the sixth gate structure 56F, at least one long gate structure (not shown) is firstly formed, and then the long gate structure is formed by photolithography, etching and other steps. The strip-shaped gate structure is divided into multi-segment gate structures. As shown in FIG. 2, the first gate structure 56A, the third gate structure 56C and the fifth gate structure 56E are divided from the same gate structure; the second gate structure 56F, the fourth gate structure 56D and The sixth gate structure 56F is divided from the same gate structure. In addition, different elongated gate structures may be partially removed simultaneously by the same etch step, so the removed portions may be aligned with each other. For example, there is a first gap G1 between the first gate structure 56A and the fifth gate structure 56E; there is a second gap G2 between the second gate structure 56B and the sixth gate structure 56F, the first The gap G1 and the second gap G2 are aligned with each other in the Y-axis direction. Similarly, there is a third gap G3 between the third gate structure 56C and the fifth gate structure 56E; there is a fourth gap G4 between the fourth gate structure 56D and the sixth gate structure 56F, and the third gap G3 and the fourth gap G4 are aligned with each other in the Y-axis direction.

In addition, the substrate 52 includes a plurality of contact columns 62 and contact layers 63, which are connected to different transistors (such as connecting the gate of the second pull-up transistor PL2 to the drain of the first pull-up transistor PL1), or connecting each transistor to other components (eg connect the source of the first pull-up transistor PL1 to the voltage source Vcc). In addition, in FIG. 2, directly connect the elements corresponding to each contact structure (for example, the voltage source Vcc, the voltage source Vss, the first word line WL1, the second word line WL2, the first bit line BL1, the second bit line BL, the first bit line The third bit line BL3 and the fourth bit line BL4 ) are marked on each contact pillar 62 or contact layer 63 to clearly express the corresponding elements of each contact pillar 62 and contact layer 63 .

The present invention also includes a first local interconnection layer 60 and a second local interconnection layer 61, wherein the first local interconnection layer 60 includes a first part 60A and a second part 60B, and the second local interconnection layer 61 It also includes the first part 61A and the second part 61B. From the top view, the first local interconnection layer 60 and the second local interconnection layer 61 are L-shaped structures respectively. Wherein the first part 60A of the first local interconnection layer 60 extends along the X-axis, and spans each of the first pull-up transistor PL1, the first pull-down transistor PD1, the first access transistor PG1A, and a second access transistor PG1B. The second part 60B is arranged on the fin structure 54 and is arranged along the Y axis, and is connected to the drain of the first pull-up transistor PL1 and the gate of the second pull-up transistor PL2 . The first portion 61A of the second local interconnection layer 61 extends along the X-axis direction, and spans the respective regions of the second pull-up transistor PL2, the second pull-down transistor PD2, the third access transistor PG2A, and the fourth access transistor PG2B. On the fin structure 54 , the second portion 61B is arranged along the Y axis and connected to the drain of the second pull-up transistor PL2 and the gate of the first pull-up transistor PL1 . In the actual manufacturing process, the first local interconnection layer 60 and the second local interconnection layer 61 can be formed by double patterning (double patterning), that is to say, they can be matched in two exposure steps in the dielectric layer. Two photomasks are used to form grooves on the long and short sides of the L-shaped structure (as shown in Figure 2, where the grooves on the long and short sides of the L-shaped structure are separated by a dotted line), and then filled with the conductive layer at the same time In the groove, the first local interconnection layer 60 or the second local interconnection layer 61 is completed. Therefore, although the first local interconnection layer 60 and the second local interconnection layer 61 are formed by double patterning, the first local interconnection layer 60 or the second local interconnection layer 61 is still an integrated structure.

In addition, please refer to FIG. 3 , which shows a cross-sectional view taken along the section line A-A' of FIG. 2 . In the present invention, the first local interconnection layer 60 and the second local interconnection layer 61 are respectively integrally formed structures (for example, monolithic structures or monolithic molded structures). Taking the first local interconnection layer 60 as an example, as shown in FIG. 3 , the fin structure 54A and the fin structure 54 are disposed on the substrate and disposed in the first dielectric layer 70 . The first local interconnect layer 60 is disposed in the second dielectric layer 72 on the first dielectric layer 70 , and the first local interconnect layer 60 directly contacts the fin structure 54A and the fin structure 54 . Similarly, the second local interconnect layer 61 is also disposed in the second dielectric layer 72 directly contacting the fin structure 54B and the fin structure 54 .

One of the features of the present invention is that the first access transistor PG1A and the second access transistor PG1B share the same fin structure (herein defined as the first fin structure 54A). Likewise, the third access transistor PG2A and the fourth access transistor PG2B share the same fin structure (defined as the first fin structure 54B herein).

The applicant found that, through the above configuration, the symmetry of the arrangement of each element is high, and when a signal is generated, the length of the signal path passing through each access transistor is approximately equal. For more details, please refer to FIG. 4 , which shows a schematic diagram of each signal flowing from each bit line to the voltage source Vss. Signal 70A is generated from the first bit line BL1, flows to the voltage source Vss after passing through the first access transistor PG1A; signal 70B is generated from the second bit line BL2, flows to the voltage source Vss after passing through the second access transistor PG1B; signal 70C It is generated from the third bit line BL3 and flows to the voltage source Vss after passing through the third access transistor PG2A; the signal 70D is generated from the fourth bit line BL4 and flows to the voltage source Vss after passing through the fourth access transistor PG2B. It can be seen from FIG. 3 that the lengths of the paths passed by the signals 70A, 70B, 70C and 70D are approximately equal. Therefore, when the static random access memory is operated, errors caused by different lengths of signal paths can be reduced, and the yield rate of the static random access memory can be improved.

In addition, please refer to FIG. 2 or FIG. 4, the contact structure connecting the second pull-up transistor PL2 and the voltage source Vcc is defined as a contact structure 63A, and the contact structure connecting the first access transistor PG1A and the first bit line BL1 is defined as Contact structure 63B. The contact structure connecting the first pull-up transistor PL1 and the voltage source Vcc is defined as a contact structure 63C, and the contact structure connecting the fourth access transistor PG2B and the fourth bit line BL4 is defined as a contact structure 63D. In the present invention, since each contact structure is also divided by a strip-shaped contact structure, it includes a dummy contact structure 64A located between the contact structure 63A and the contact structure 63B, and a dummy contact structure 64B located between the contact structure 63C and contact structure 63D. The existence of the dummy contact structure helps to balance the density of components in the area.

The structures shown in FIG. 2 are formed in the same layer (eg, a dielectric layer). Next, on the dielectric layer, continue to form other dielectric layers, and form a plurality of contact structures or wiring structures in the upper dielectric layer. FIG. 5 is a layout diagram of the upper layer structure in FIG. 2 . In FIG. 5 , a plurality of metal lines 80 are included, which are connected to each contact layer 63 in the lower layer through a plurality of contact structures (via structure, not shown in the figure). It should be noted that the connection to the first bit line BL1 is defined as a metal line 80A, the connection to the second bit line BL2 is defined as a metal line 80B, the connection to the third bit line BL3 is defined as a metal line 80C, and the connection to the fourth bit line BL4 is defined as metal line 80D. In addition, a dummy line 82A is included between the metal line 80A and the metal line 80B, and a dummy line 82B is located between the metal line 80C and the metal line 80D. The existence of dummy lines helps to reduce cross talk between metal lines.

In subsequent steps, other dielectric layers, contact structures, metal layers, etc. will be formed to be stacked on the above-mentioned components. Since the present invention does not limit the shape, quantity, etc. of the subsequent contact structure and the metal layer, no further details are given here.

In addition, in the above embodiments, each transistor is a fin transistor, and the gate structure is formed on the fin structure. However, in the present invention, each transistor may also include a planar transistor, that is, a plurality of diffusion regions are formed instead of the above-mentioned fin structures. As shown in FIG. 6, the 8T-SRAM memory cell 10' is located in a region 50' and is arranged on a substrate 52, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a plurality of diffusion regions are arranged on the substrate 52. 90 and a plurality of gate structures 56, the gate structure 56 spans over the diffusion region 90 to form a plurality of transistors, such as the first pull-up transistor PL1, the first pull-down transistor PD1, the second pull-up transistor PL2, the second pull-down transistor The transistor PD2, the first access transistor PG1A, the second access transistor PG1B, the third access transistor PG2A, and the fourth access transistor PG2B (refer to FIG. 1 at the same time). Other unmentioned components, such as a plurality of contact pillars 62, a contact layer 63, a plurality of metal lines (not shown) and dummy lines (not shown), etc. (refer to FIG. 2 and FIG. 5 ), are the same as those described above. The first preferred embodiment is the same and will not be repeated here. In addition, in this embodiment, the dummy layer 65A is located between the contact structure 62 connected to the bit line BL1 and the contact structure 62 connected to the voltage source Vcc; the dummy layer 65B is located between the contact structure 62 connected to the bit line BL4 and the voltage source Vcc between contact structures 62 . The existence of the dummy layer can reduce the difference in device density.

In this embodiment, the first access transistor PG1A and the second access transistor PG1B share a diffusion region 90, which is defined as the first diffusion region 90A; the third access transistor PG2A and the fourth access transistor PG2B share A diffusion region 90 is defined as a second diffusion region 90B.

This embodiment includes a first local interconnection layer 60, and the first local interconnection layer 60 spans the diffusion region 90 of the first pull-up transistor PL1, the diffusion region 90 of the first pull-down transistor PD1, and the first access transistor PG1A. The diffusion region 90 of the second access transistor PG1B and the diffusion region 90 of the second access transistor PG1B. A second local interconnection layer 61, the second local interconnection layer 61 spans the diffusion region 90 of the second pull-up transistor PL2, the diffusion region 90 of the second pull-down transistor PD2, the diffusion region 90 of the third access transistor PG2A and The diffusion region 90 of the fourth access transistor PG2B. In addition, from a top view, the first local interconnection layer 60 or the second local interconnection layer 61 is an integrally formed L-shaped structure respectively.

Please refer to FIG. 7 , which shows a cross-sectional view taken along the section line B-B' in FIG. 6 . In the present invention, the first local interconnection layer 60 and the second local interconnection layer 61 are respectively integrally formed structures (for example, monolithic structures or monolithic molded structures). Taking the first local interconnection layer 60 as an example, as shown in FIG. Layer 60A is disposed in third dielectric layer 74 . Each via plug 75 is electrically connected to and directly contacts the diffusion region 90 , for example, three via plugs 75 shown in FIG. 7 are electrically connected to the first local interconnection layer 60 . In addition, a fourth dielectric layer 76 is formed on the third dielectric layer 74 . Similarly, the second local interconnect layer 61 is also disposed in the third dielectric layer 74 directly contacting the plurality of via plugs 75 .

One of the features of the present invention is that the first access transistor and the second access transistor share the same fin structure. Likewise, the third access transistor and the fourth access transistor PG2B share the same fin structure. The applicant found that, through the above configuration, the symmetry of the arrangement of each element is high, and when a signal is generated, the length of the signal path passing through each access transistor is approximately equal. Therefore, when the static random access memory is operated, errors caused by different lengths of signal paths can be reduced, and the yield rate of the static random access memory can be improved.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (24)

1. A layout pattern of a static random-access memory (SRAM), comprising:

a substrate;

a first inverter including a first pull-up transistor (PL 1) and a first pull-down transistor (PD 1) on the substrate;

a second inverter comprising a second pull-up transistor (PL 2) and a second pull-down transistor (PD 2) on the substrate, wherein the first inverter and the second inverter are coupled to each other;

a first access transistor (PG 1A) and a second access transistor (PG 1B) are connected with the output end of the first inverter, a third access transistor (PG 2A) and a fourth access transistor (PG 2B) are connected with the output end of the second inverter, wherein the grid electrode of the PG1A and the grid electrode of the PG2A are connected to a first character line, and the grid electrode of the PG1B and the grid electrode of the PG2B are connected to a second character line;

a plurality of transistors including the PL1, the PD1, the PL2, the PD2, the PG1A, the PG1B, the PG2A, and the PG2B, each of the transistors including a gate structure spanning at least one fin structure, wherein the PG1A and the PG1B include the same first fin structure, and the PG2A and the PG2B include the same second fin structure;

a first local interconnection layer located between the PG1A and the PG1B, located on the first fin structure included in the PG1A and the PG1B, and located on the fin structure included in the PL1 and the PD1, wherein the first local interconnection layer is an integrally formed structure; and

and a second local interconnection layer located between the PG2A and the PG2B, located on the second fin structure contained in the PG2A and the PG2B, and located on the fin structure contained in the PL2 and the PD2, wherein the second local interconnection layer is an integrated structure.

2. The layout pattern of claim 1 wherein said PG1A comprises a first gate structure, said PG1B comprises a second gate structure, said PG2A comprises a third gate structure, said PG2B comprises a fourth gate structure, said PL2 and said PD2 comprise a fifth gate structure, and said PL1 and said PD1 comprise a sixth gate structure.

3. The layout pattern of claim 2, wherein the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure and the sixth gate structure are arranged along a first direction.

4. The sram layout pattern of claim 3 further comprising a first pitch between said first gate structure and said fifth gate structure, a second pitch between said second gate structure and said sixth gate structure, said first pitch aligned with said second pitch in a second direction, and said second direction being perpendicular to said first direction.

5. The layout pattern of claim 4, further comprising a third pitch between the third gate structure and the fifth gate structure, a fourth pitch between the fourth gate structure and the sixth gate structure, the third pitch aligned with the fourth pitch in the second direction.

6. The layout pattern of claim 3, wherein the first local interconnect layer and the second local interconnect layer are aligned along the first direction.

7. The sram layout pattern of claim 4 further comprising:

a first bit line connected to the PG1A, wherein the first bit line is arranged along the second direction;

a second bit line connected to the PG1B, wherein the second bit line is arranged along the second direction;

the first dummy line is arranged along the second direction and is positioned between the first bit line and the second bit line.

8. The sram layout pattern of claim 4 further comprising:

a third bit line connected to the PG2A, wherein the third bit line is arranged along the second direction;

a fourth bit line connected to the PG2B, wherein the fourth bit line is arranged along the second direction;

the second dummy line is arranged along the second direction and is positioned between the third bit line and the fourth bit line.

9. The sram layout pattern of claim 1 further comprising a plurality of contacts on said substrate, said plurality of contacts comprising a first Vcc contact connected to said source of PL2, a first bitline contact connected to said source of PG1A, and a first dummy layer between said first Vcc contact and said first bitline contact.

10. The sram layout pattern of claim 9 further comprising a second Vcc contact structure connected to a source of said PL1, a fourth bitline contact structure connected to a source of said PG2B, and a second dummy layer between said second Vcc contact structure and said fourth bitline contact structure.

11. The sram layout pattern of claim 1 wherein said first local interconnect layer contacts said first fin structure of said PG1A, said first fin structure of said PG1B, and said fin structures comprised by said PL1 and said PD1 simultaneously, and said first local interconnect layer is an integrally formed L-shaped structure from a top view.

12. The layout pattern of claim 11, wherein the fin structure, the first fin structure, and the second fin structure are located in a first dielectric layer, and wherein the first local interconnect layer and the second local interconnect layer are located in a second dielectric layer that is located on the first dielectric layer.

13. A layout pattern of a static random-access memory (SRAM), comprising:

a substrate;

a first inverter including a first pull-up transistor (PL 1) and a first pull-down transistor (PD 1) on the substrate;

a second inverter comprising a second pull-up transistor (PL 2) and a second pull-down transistor (PD 2) on the substrate, wherein the first inverter and the second inverter are coupled to each other;

a first access transistor (PG 1A) and a second access transistor (PG 1B) are connected with the output end of the first inverter, a third access transistor (PG 2A) and a fourth access transistor (PG 2B) are connected with the output end of the second inverter, wherein the grid electrode of the PG1A and the grid electrode of the PG2A are connected to a first character line, and the grid electrode of the PG1B and the grid electrode of the PG2B are connected to a second character line;

a plurality of transistors including the PL1, the PD1, the PL2, the PD2, the PG1A, the PG1B, the PG2A, and the PG2B, each of the transistors including a gate structure crossing at least one diffusion region, wherein the PG1A and the PG1B include the same first diffusion region, and the PG2A and the PG2B include the same second diffusion region;

a first local interconnection layer located between the PG1A and the PG1B, located on the first diffusion region contained in the PG1A and the PG1B, and located on the diffusion region contained in the PL1 and the PD1, wherein the first local interconnection layer is an integrally formed structure; and

and a second local interconnection layer located between the PG2A and the PG2B, located on the second diffusion region contained in the PG2A and the PG2B, and located on the diffusion region contained in the PL2 and the PD2, wherein the second local interconnection layer is an integrated structure.

14. The layout pattern of claim 13 wherein said PG1A comprises a first gate structure, said PG1B comprises a second gate structure, said PG2A comprises a third gate structure, said PG2B comprises a fourth gate structure, said PL2 and said PD2 comprise a fifth gate structure, and said PL1 and said PD1 comprise a sixth gate structure.

15. The layout pattern of claim 14, wherein the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure and the sixth gate structure are arranged along a first direction.

16. The sram layout pattern of claim 15 further comprising a first pitch between said first gate structure and said fifth gate structure, a second pitch between said second gate structure and said sixth gate structure, said first pitch aligned with said second pitch in a second direction, and said second direction being perpendicular to said first direction.

17. The sram layout pattern of claim 16 further comprising a third pitch between said third gate structure and said fifth gate structure, a fourth pitch between said fourth gate structure and said sixth gate structure, said third pitch aligned with said fourth pitch in said second direction.

18. The sram layout pattern of claim 15 wherein said first local interconnect layer and said second local interconnect layer are aligned along said first direction.

19. The sram layout pattern of claim 16, further comprising:

a first bit line connected to the PG1A, wherein the first bit line is arranged along the second direction;

a second bit line connected to the PG1B, wherein the second bit line is arranged along the second direction;

the first dummy line is arranged along the second direction and is positioned between the first bit line and the second bit line.

20. The sram layout pattern of claim 16, further comprising:

a third bit line connected to the PG2A, wherein the third bit line is arranged along the second direction;

a fourth bit line connected to the PG2B, wherein the fourth bit line is arranged along the second direction;

the second dummy line is arranged along the second direction and is positioned between the third bit line and the fourth bit line.

21. The sram layout pattern of claim 13 further comprising a plurality of contact structures on said substrate, said plurality of contact structures comprising a first Vcc contact structure connected to said source of PL2, a first bitline contact structure connected to said source of PG1A, and a first dummy layer between said first Vcc contact structure and said first bitline contact structure.

22. The sram layout pattern of claim 20 further comprising a second Vcc contact structure connected to a source of said PL1, a fourth bitline contact structure connected to a source of said PG2B, and a second dummy layer between said second Vcc contact structure and said fourth bitline contact structure.

23. The sram layout pattern of claim 13 wherein said first local interconnect layer contacts said first diffusion region of said PG1A, said first diffusion region of said PG1B, and said diffusion regions comprised by said PL1 and said PD1 simultaneously, and is an integrally formed L-shaped structure from a top view.

24. The layout pattern of claim 23, wherein the diffusion region, the first diffusion region, and the second diffusion region are located in the substrate, and wherein the first local interconnect layer and the second local interconnect layer are located in a dielectric layer that is located on the substrate.

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