CN116187224B - A process design kit device library and design migration method - Google Patents

Abstract

The application provides a process design kit device library and a design migration method. The device library of the process design kit includes: a first device library, including a plurality of first devices, predetermined based on a general process and a general process layer; a second device library, including at least one second device, the structure of the second device library and the first The second device can be configured to correspond to a specified process and can be mapped to a specified process layer. For the process to be developed, at least a part of the process to be developed is provided through the first device library and the remaining part of the process to be developed is provided through the second device library, and the at least part of the process to be developed is compared with the process to be developed and The general process is determined. This helps to drastically reduce development and verification cycles.

Description

A process design kit device library and design migration method

technical field

The present application relates to the field of computer technology, in particular to a process design kit device library and a design migration method.

Background technique

In chip design such as large-scale mixed-signal circuit and analog circuit design, it is generally necessary to use Process Design Kit (PDK) to complete the design and verification work. However, with the improvement of the integration level and design complexity of integrated circuits, as well as the development of various new processes and new device structures, the development and verification cycle has also increased significantly. In addition, in front-end circuit design and back-end layout design, and from one process node to another process node, it is necessary to carry out design migration to speed up circuit design, and with the increase in design complexity and process development, The labor consumption invested in design migration has also increased significantly.

Therefore, the application provides a process design kit device library and a design migration method, which can effectively reduce the development and verification cycle of using the process design kit device library, and can effectively reduce the time and resources invested in design migration.

Contents of the invention

In a first aspect, the present application provides a process design kit device library. The process design kit device library includes: a first device library, wherein the first device library includes a plurality of first devices, and the plurality of first devices are predetermined based on a general process and a general process layer; the second device A library, wherein the second device library includes at least one second device, and the structure of the second device library and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer. Wherein, for the process to be developed, at least a part of the process to be developed is provided through the first device library of the process design kit device library and provided through the second device library of the process design kit device library For the remaining part of the process recipe to be developed, the at least a part of the process recipe to be developed is determined by comparing the process recipe to be developed with the general process recipe.

Through the first aspect of the present application, the general device library is realized through the first device library predetermined based on the general process and the general process layer and the second device library that can be configured to correspond to the specified process and can be mapped to the specified process layer Decoupling of sections and configurable sections. In this way, through the configurable part of the process design kit device library, that is, the second device library, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized, and at the same time, the general device library part of the process design kit device library can also be That is, the first device library to make full use of semiconductor devices with a large number of available models and design rules and mature semiconductor processes that can be applied on a large scale, thereby helping to greatly reduce the development and verification cycle.

In a possible implementation of the first aspect of the present application, for the design to be migrated, by comparing the pre-migration process and the post-migration process corresponding to the design to be migrated, determine the The first device library and the second device library determining the process design kit device library use the process design kit device library to complete the migration of the design to be migrated.

In a possible implementation manner of the first aspect of the present application, the plurality of first devices include transistors, contact holes, and interconnection lines suitable for the general process, and the first device library further includes the The electrical characteristics and design rules of each of the plurality of first devices are described.

In a possible implementation of the first aspect of the present application, the at least one second device includes basic elements suitable for the specified process, and the second device library further includes the at least one second device The electrical characteristics and design rules associated with the specified process.

In a possible implementation manner of the first aspect of the present application, the first device library further includes design rules, electrical rules, and layout verification rules associated with the general process.

In a possible implementation manner of the first aspect of the present application, the structure of the second device library may also be configured to correspond to a metal layer structure associated with the process to be developed.

In a possible implementation manner of the first aspect of the present application, the process design kit device library includes a general view for displaying the first device library and the general process layer.

In a possible implementation manner of the first aspect of the present application, the at least part of the process to be developed is an overlapping part between the process to be developed and the general process, and the process to be developed The remaining part of the process recipe is a non-overlapping part between the process recipe to be developed and the general process recipe.

In a possible implementation of the first aspect of the present application, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively the previous process for the circuit design node and the next process node.

In a possible implementation of the first aspect of the present application, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively the previous process for the layout design node and the next process node.

In a possible implementation of the first aspect of the present application, the first device library of the process design kit device library is a reusable part, the second device library of the process design kit device library is a non-reusable part between the pre-migration process and the post-migration process.

In a possible implementation of the first aspect of the present application, the process design kit device library is used for design migration between multiple process nodes, and for any of the multiple process nodes For adjacent paired process nodes, by comparing the process process of the previous process node and the process process of the next process node in the pair of process nodes, based on the first device library and by configuring the second The device library thus completes the design migration between the paired process nodes.

In a possible implementation of the first aspect of the present application, the first device library of the process design kit device library provides at least A portion and through said second device library of said process design kit device library provides the remainder of the process flow of a subsequent process node of the pair of process nodes.

In a possible implementation of the first aspect of the present application, the first device library of the process design kit device library is the process process of the previous process node and the subsequent process node in the paired process nodes. The reusable part between the process steps of the process node, the second device library of the process design kit device library is the process process of the previous process node and the subsequent process process in the pair of process nodes A non-reusable part between process steps of a node.

In the second aspect, the embodiment of the present application provides a design migration method. The design migration method includes: providing a process design kit device library including a first device library and a second device library, wherein the first device library includes a plurality of first devices, and the plurality of first devices are based on a common process The process and general process layer are predetermined, the second device library includes at least one second device, the structure of the second device library and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer, the first device library is used to provide at least a part of the process to be developed and the second device library is used to provide the remaining part of the process to be developed, and the at least a part of the process to be developed is passed Comparing the process process to be developed and the general process process to determine; for the design to be migrated, by comparing the process process before migration and the process process after migration corresponding to the design to be migrated, determine all the components of the process design kit device library The first device library and determining the second device library of the process design kit device library; and using the process design kit device library to complete the migration of the design to be migrated.

Through the second aspect of the present application, the general device library is realized through the first device library predetermined based on the general process and the general process layer and the second device library that can be configured to correspond to the specified process and can be mapped to the specified process layer Decoupling of sections and configurable sections. In this way, through the configurable part of the process design kit device library, that is, the second device library, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized, and at the same time, the general device library part of the process design kit device library can also be That is, the first device library to make full use of semiconductor devices with a large number of available models and design rules and mature semiconductor processes that can be applied on a large scale, thereby helping to greatly reduce the development and verification cycle.

In a possible implementation of the second aspect of the present application, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively the previous process for the circuit design node and the next process node.

In a possible implementation of the second aspect of the present application, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively the previous process for the layout design node and the next process node.

In a possible implementation of the second aspect of the present application, the first device library of the process design kit device library is a reusable part, the second device library of the process design kit device library is a non-reusable part between the pre-migration process and the post-migration process.

In a possible implementation of the second aspect of the present application, the process design kit device library is used for design migration between multiple process nodes, and for any of the multiple process nodes For adjacent paired process nodes, by comparing the process process of the previous process node and the process process of the next process node in the pair of process nodes, based on the first device library and by configuring the second The device library thus completes the design migration between the paired process nodes.

In a possible implementation of the second aspect of the present application, the first device library of the process design kit device library provides at least A portion and through said second device library of said process design kit device library provides the remainder of the process flow of a subsequent process node of the pair of process nodes.

In a possible implementation of the second aspect of the present application, the first device library of the process design kit device library is the process process of the previous process node and the next process node in the pair of process nodes. The reusable part between the process steps of the process node, the second device library of the process design kit device library is the process process of the previous process node and the subsequent process process in the pair of process nodes A non-reusable part between process steps of a node.

In the third aspect, the embodiment of the present application also provides a computer device, the computer device includes a memory, a processor, and a computer program stored in the memory and operable on the processor, and the processor executes The computer program implements the method according to any implementation manner of any of the above aspects.

In the fourth aspect, the embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores computer instructions, and when the computer instructions are run on the computer equipment, the computer equipment executes the above-mentioned A method of any implementation of any aspect.

In the fifth aspect, the embodiment of the present application also provides a computer program product, the computer program product includes instructions stored on a computer-readable storage medium, and when the instructions are run on a computer device, the computer device executes A method according to any implementation manner of any of the foregoing aspects.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

FIG. 1 is a schematic diagram of a process design kit device library provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a design migration based on a process design kit device library provided by an embodiment of the present application;

FIG. 3 is a schematic flow chart of a design migration method provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a computing device provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

It should be understood that in the description of the present application, "at least one" means one or more than one, and "plurality" means two or more. In addition, words such as "first" and "second", unless otherwise specified, are only used for the purpose of distinguishing and describing, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

FIG. 1 is a schematic diagram of a process design kit device library provided by an embodiment of the present application. As shown in FIG. 1 , the process design kit device library A 100 includes a first device library 110 and a second device library 120 . Wherein, the first device library 110 includes a plurality of first devices. A first device A 112 , a first device B 114 and a first device C 116 are exemplarily shown in FIG. 1 . The first device library 110 may include any number of first devices. The multiple first devices are predetermined based on the common process recipe 130 and the common process layer 132 . The second device library 120 includes at least one second device. A second device A 122 and a second device B 124 are exemplarily shown in FIG. 1 . The second device library 120 may include any number of second devices. The structure of the second device library 120 and the at least one second device (eg, the second device A 122 and the second device B 124 ) may be configured to correspond to a specified process recipe 140 and may be mapped to a specified process layer 142 . Wherein, for the process to be developed, the first device library 110 of the process design kit device library A 100 provides at least a part of the process to be developed and the first device library A 100 of the process design kit The second device library 120 provides the remaining part of the process recipe to be developed, the at least a part of the process recipe to be developed is determined by comparing the process recipe to be developed with the general process recipe 130 . The process design kit device library A 100 is used to provide a process design kit (Process Design Kit, PDK), which is used to build communication between chip design companies, foundries and electronic design automation (EDA) companies bridge. Generally, the process design kit device library A 100 and the provided process design kit include a technical file package for chip design and verification work. In some embodiments, the process design kit includes basic elements reflecting the manufacturing process, such as transistors, contact holes, interconnection lines, and the like. In some embodiments, the content of the process design kit also includes design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters, etc. The process design kit device library A 100 and the provided process design kit are closely related to the semiconductor process, which contains a set of files describing the details of the semiconductor process for chip design EDA tools. Before the chip is put into production, the process design kit provided by the fab is generally used to ensure that the fab can produce chips based on the chip design, thereby ensuring the expected function and performance of the chip. When it is necessary to develop a new semiconductor process, for example, for the process to be developed, it is necessary to develop a supporting process design kit, which defines a set of document materials reflecting the semiconductor process of the foundry in the language of the foundry, which can be used for chip design. The physical verification at the time is also the key factor that determines the success or failure of the chip. Exemplary and non-limiting, the process design kit device library A 100 and the provided process design kit may include one or more of the following contents, including but not limited to: device model (Device Model), provided by the foundry The simulation model file; the symbol used for schematic design, in which the parameterized design unit has passed the simulation verification; the component description format (Component Description Format, CDF), the attribute description file of the device, which defines the type, name, Parameters and parameter call relationship function sets, device models, device view formats, etc.; parameterized cells (Parameterized Cell, Pcell), which describe possible customization methods for transistors and other devices; technical documents, process documents for layout design and verification, Including the definition of the mapping relationship between the design data layer and the process layer, the attribute definition of the design data layer, online design rules, electrical rules, display color definition and graphic format definition, etc.; physical verification rule files, including layout verification files, etc.

Continue to refer to Figure 1. As mentioned above, the process design kit PDK is closely related to the relevant details of the semiconductor process. On the one hand, it must reflect the basic elements of the semiconductor manufacturing process such as transistors, contact holes, and interconnection lines. Macro information such as rules and models, such as design rule files, electrical rule files, layout level definition files, SPICE simulation models, device layout and period customization parameters, etc. Therefore, as a bridge for communication between chip design companies, foundries and EDA companies, the process design kit PDK must not only adapt to the specific semiconductor process used by the foundry (for example, provided by the fab and foundry to reflect its semiconductor process) Documentation materials, etc.), and to adapt to the relevant characteristics of the EDA tools provided by the EDA company (for example, the EDA tools developed by the EDA company may have improvements in device models, parameterized units, and verification rules, etc.), and it is also necessary to consider the chip The design company's requirements on circuit design and layout design, such as realizing specific chip functions, using specific devices, or using specific semiconductor processes, etc. This means that for a newly developed semiconductor process, for example, for the process to be developed, it is necessary to comprehensively consider the communication and collaboration between the chip design company, the foundry and the EDA company, and the process design kit serves as the cornerstone of the chip design and physical verification process It is also a key factor in the success or failure of chip manufacturing. With the development of semiconductor devices and semiconductor processes, new processes, new device structures such as metal layer structures, new device electrical characteristics and design rules, etc., all of these need to be passed in the chip design and development process. Shown. For example, the process design kit device library A 100 needs to provide technical details of its metal layer structure, electrical characteristics, related design rules, and physical verification rules for new semiconductor devices, and it also needs to target new semiconductor processes such as new process processes. A technical document describing the details of an associated semiconductor process. With the increasing scale and design complexity of integrated circuits, it is necessary to use high-quality and high-efficiency process design kit device libraries to shorten the chip development and verification cycle as much as possible, improve chip design efficiency and reduce costs as much as possible. In addition, in the entire process of chip development, it involves front-end circuit diagram design and back-end layout design, and may also involve process differences and differences between different design databases. Sometimes it is necessary to transfer from one process node to another. A process manufacturing node performs process manufacturing-level design migration, which also relies on high-quality and high-efficiency process design kit device libraries to shorten the labor input and time required for design migration.

Continuing to refer to FIG. 1 , the process design kit device library A 100 includes a first device library 110 and a second device library 120 . The multiple first devices included in the first device library 110 are predetermined based on the common process recipe 130 and the common process layer 132 . The structure of the second device library 120 and the at least one second device included in the second device library 120 may be configured to correspond to a specified process recipe 140 and may be mapped to a specified process layer 142 . Here, the general process 130 corresponds to a general, common or large-scale mature application process in the semiconductor process. The general process layer 132 corresponds to the metal layer structure, process manufacturing layer, etc. associated with the general process 130 . As mentioned above, the process design kit is closely related to the process and device structure information such as metal layer structure. Therefore, the multiple first devices are predetermined based on the general process flow 130 and the common process layer 132, which means that the multiple first devices, such as the first device A112, etc., are general-purpose semiconductor devices, which correspond to General semiconductor process and general device structure information, such as general process manufacturing layer and general metal layer structure, etc. Therefore, the plurality of first devices included in the first device library 110 also reflect relevant basic elements of the general semiconductor manufacturing process, such as transistors, contact holes, interconnection lines, etc. associated with the general process 130 and the general process layer 132 . The multiple first devices included in the first device library 110 also reflect relevant macro factors of the general semiconductor manufacturing process, such as design rule files, electrical rule files, and layout level definition files associated with the general process flow 130 and the general process layer 132 , SPICE simulation model, device layout and period custom parameters, etc. Therefore, the first device library and its structure are conducive to the rapid use of common device list and process manufacturing layer information as well as device electrical characteristics and design rules, thereby facilitating the efficient and high-quality construction of the process design kit device library A100. In contrast, the structure of the second device library 120 and the at least one second device included in the second device library 120 may be configured to correspond to a specified process 140 and may be mapped to a specified process layer 142 . The designated process 140 is relative to the general process 130 , and may correspond to a relatively uncommon process, such as a newly developed process or a process with narrow application. The specified process layer 142 is relative to the general process layer 132 , and corresponds to the metal layer structure, process manufacturing layer, etc. associated with the specified process 140 . As mentioned above, the process design kit is closely related to the process and device structure information such as metal layer structure. Therefore, the structure of the second device library 120 and the at least one second device included in the second device library 120 can be configured to correspond to the specified process recipe 140 and can be mapped to the specified process layer 142, which means that the at least one first The second device, such as the second device A122, is a semiconductor device for a specified process 140, which corresponds to the specified process 140 and device structure information associated with the specified process 140, such as process manufacturing layer and metal layer structure. The at least one second device included in the second device library 120 also reflects transistors, contact holes, interconnection lines, etc. associated with the specified process 140 . The structure of the second device library 120 and the at least one second device also reflect macro factors, such as design rule files, electrical rule files, layout level definition files, and SPICE simulation models associated with the specified process 140 and the specified process layer 142 , device layout and period customization parameters, etc. Moreover, the structure of the second device library 120 and the at least one second device included in the second device library 120 are configurable, that is to say, the structure of the second device library 120 and the at least one second device can be configured. The devices are configured jointly or separately so that they can correspond to the specified process 140 and can be mapped to the specified process layer 142, which means that the specified process 140 and/or the specified process layer 142 can be flexibly changed (for example, introducing a new semiconductor process process or a new process manufacturing layer, etc.), and then reflect the changes made to the specified process recipe 140 and/or the specified process layer 142 by reconfiguring the structure of the second device library 120 and the at least one second device. The first device library 110 can be understood as a general device library part of the process design kit device library A 100 , and the second device library 120 can be understood as a configurable part of the process design kit device library A 100 . In this way, the general device library is realized through the first device library 110 predetermined based on the general process 130 and the general process layer 132 and the second device library 120 that can be configured to correspond to the specified process 140 and can be mapped to the specified process layer 142 Decoupling of sections and configurable sections. In this way, the second device library 120, which is the configurable part of the process design kit device library A 100, can flexibly realize the adaptation to new semiconductor devices and new semiconductor processes, and at the same time, the process design kit device library A 100 can The common device library part, ie, the first device library 110, makes full use of semiconductor devices with a large number of available models and design rules and mature semiconductor processes that can be applied on a large scale, thereby helping to greatly reduce the development and verification cycle. Therefore, for a specific process, through the division of labor and combination between the first device library 110 and the second device library 120, a matching process design kit device library A 100 can be quickly and efficiently constructed to realize the use of the specific process. Process chip design and verification.

Continuing to refer to FIG. 1 , it should be understood that there is a gap between the common device library part of the process design kit device library A 100, that is, the first device library 110, and the configurable part of the process design kit device library A 100, that is, the second device library 120 is a relative concept. A specific device or a specific process may be divided into the first device library 110 in some business scenarios, but may be divided into the second device library 120 in other business scenarios. This may be because in some business scenarios, the specific device or the specific process is common, common or large-scale application type, but in other business scenarios, the specific device or the specific process is rare , non-universal or less applicable types. For example, key devices used in high-speed digital communication circuits, such as certain specially designed transistors, may occupy a considerable part of the chip design scheme in communication-related business scenarios (such as chip design for communication), such as belonging to At this time, the key chip function design may be suitable to be divided into the first device library 110, that is to say, it is pre-determined based on the general process 130 and the common process layer 132, which helps to reduce the development cycle and reduce the cost by utilizing the mature process. However, such specially designed transistors may only take up a small part of the chip design in other business scenarios such as storage-related business scenarios (such as memory chip design). It may be suitable to be divided into the second device library 120, that is to say, it can be configured to correspond to the specified process process 140 and can be mapped to the specified process layer 142, which helps to quickly build a business scenario suitable for memory chip design using configurable features Process Design Kit Library A 100. In addition, some device models or process iterations have a high iteration frequency and a fast iteration speed, and may also be suitable for being divided into the second device library 120, so that configurable features can be better used to better implement new semiconductor devices and new Adaptation of semiconductor process. Therefore, various factors such as specific chip design purposes, customer needs, business scenarios, and technology iteration speed determine the general device library part of the process design kit device library A 100, that is, the first device library 110 and the process design kit device library A 100 The configurable part of , that is, the division between the second device library 120 . The process design kit device library A 100 shown in Figure 1 not only realizes the decoupling of the general device library part and the configurable part, but also can be customized according to specific business scenarios, chip design purposes, customer needs, business scenarios, technology iteration speed, etc. to flexibly adjust the division between the common device library part and the configurable part, and help to quickly and efficiently build a matching process design kit device library A 100 .

Continuing to refer to FIG. 1, taking the capacitor as an example to illustrate the common device library part of the process design kit device library A 100, that is, the first device library 110 and the configurable part of the process design kit device library A 100, that is, the second device partition between libraries 120 . Assuming that the first device library 110 includes a device such as a field effect transistor capacitor, for example, it may be assumed that the first device A112 shown in FIG. 1 is a field effect transistor capacitor. Field-effect transistor refers to metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and field-effect transistor capacitor is a capacitor based on MOSFET, referred to as MOS capacitor. Field effect tube capacitors use MOSFETs as capacitors. The principle is to use the gate oxide between the gate (gate) and the channel of the MOSFET as the insulating medium, and use the gate as the upper plate to short-circuit the source, drain and substrate. Connect together to form the lower plate. Field effect tube capacitors, also known as MOS capacitors and their related semiconductor processes, are common, general-purpose or large-scale application types. Therefore, in general, MOS capacitors are suitable to be divided into the first device library 110, that is to say predetermined based on the general process 130 and the common process layer 132, which helps to reduce the development cycle and reduce costs by using mature processes. In contrast, metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitors are also called MIM capacitors, which refer to the use of metal insulator metal components to build capacitors. Among them, MIM is a sandwich structure composed of metal, insulator, and metal three-layer film. MIM capacitors are generally composed of the top two layers of metal and a special metal layer in the middle. The MIM capacitor is equivalent to a parallel plate capacitor, and the distance between the two layers of metal on the top layer is relatively large, resulting in a small capacitance value. The dielectric layer in the middle of the MIM capacitor is relatively thin, and the formed capacitance density is relatively high. The MIM capacitor has the characteristics of small parasitic capacitance and high precision. The certainty and stability of the capacitance value of MOS capacitors is not as good as that of MIM capacitors. Compared with MOS capacitors, the capacitance values of MIM capacitors are more accurate, and the capacitance value will not change with the change of bias voltage. It is also called plate capacitance. However, in the related semiconductor process, the MIM capacitor requires additional processes and additional masks compared with the MOS capacitor, and because of the characteristics of the MIM capacitor, it is also necessary to use a dielectric layer material with a high dielectric constant. The chip design using the MIM capacitor needs to face such difficulties as the reduced linearity of the integrated capacitor and the reduced stability of the linear system. Therefore, by dividing the MOS capacitors into the first device library 110, for example, setting the first device A112 as a MOS capacitor, and dividing the MIM capacitors into the second device library 120, for example, setting the second device A122 as a MIM capacitor, this can be based on the general process 130 and common process layer 132 to predetermine MOS capacitors, thereby reducing the development cycle and utilizing mature processes to reduce costs; characteristics and design problems, better adapt to the electrical characteristics, design rules and related semiconductor process of the device model of MIM capacitors, and can also more flexibly adopt the process optimization made for MIM capacitors, and finally fast and efficient A matching process design kit device library A 100 is constructed in a timely manner.

Continue to refer to Figure 1. As mentioned above, the process design kit device library A 100 shown in Figure 1 not only realizes the decoupling of the general device library part and the configurable part, but also can Requirements, business scenarios, technology iteration speed, etc. to flexibly adjust the division between the general device library part and the configurable part, that is, refactoring can be performed on the basis of decoupling, that is, decoupling refactoring, which is helpful for fast and efficient A matching process design kit device library A 100 is constructed in a timely manner. Therefore, for the process to be developed, the first device library 110 of the process design kit device library A 100 provides at least a part of the process to be developed and the process design kit device library A 100. The second device library 120 provides the remaining part of the process recipe to be developed, the at least a part of the process recipe to be developed is determined by comparing the process recipe to be developed with the general process recipe 130 . This means that the general process 130 and the first device library 110 in the process design kit device library A 100 shown in FIG. Considering the process difference between the process to be developed and the general process 130, using the second device library 120 in the process design kit device library A 100 shown in FIG. 1 to adapt the process to be developed will help In order to quickly and efficiently build a process design kit device library A 100 matching the process to be developed. Moreover, by decoupling the PDK device library into a general-purpose device library and a configurable structure part, the general-purpose device library can be displayed through a general-purpose view, and the reconstructed general-purpose device library can be used to quickly complete the PDK of a specified process The development and verification of the device library, and the development efficiency of the PDK device library is greatly improved by reusing and merging the configurable parts. Therefore, using the decoupling and reconfiguration scheme of the process design kit device library A 100 shown in Figure 1 can greatly improve the development and verification efficiency of the PDK device library. The similarities and differences between the processes can provide more direct and effective help in the design migration process.

Continue to refer to Figure 1. In the entire process of chip development, it involves front-end circuit diagram design and back-end layout design. It may also involve differences in process and different design databases. Sometimes it is necessary to start from a process. Process-manufacturing-level design migration from a node to another process-manufacturing node. Through the process design kit device library A 100 shown in Figure 1, by using the decoupling of the general device library part and the configurable part, it can be flexible according to specific business scenarios, chip design purposes, customer needs, business scenarios, technology iteration speed, etc. The division between the common device library part and the configurable part can be adjusted accurately, so as to meet the needs of design migration and shorten the labor input and time required for design migration.

In a possible implementation manner, for the design to be migrated, the first device of the process design kit device library A 100 is determined by comparing the pre-migration process and the post-migration process corresponding to the design to be migrated. Library 110 and the second device library 120 determining the process design kit device library A 100 , using the process design kit device library A 100 to complete the migration of the design to be migrated. This helps to meet the needs of design migration and shorten the labor input and time required for design migration.

In a possible implementation manner, the plurality of first devices include transistors, contact holes, and interconnection lines suitable for the general process 130, and the first device library 110 further includes the plurality of first The electrical characteristics and design rules of each device. In a possible implementation manner, the at least one second device includes basic elements suitable for the specified process 140, and the second device library 120 further includes the at least one second device and the specified The electrical characteristics and design rules associated with the process recipe 140 . In a possible implementation manner, the first device library 110 further includes design rules, electrical rules, and layout verification rules associated with the general process 130 . In a possible implementation manner, the structure of the second device library 120 may also be configured to correspond to a metal layer structure associated with the process to be developed. In this way, the decoupling of the general device library part and the configurable part is realized, and the general device library part and the configurable part can be flexibly adjusted according to specific business scenarios, chip design purposes, customer needs, business scenarios, technology iteration speed, etc. The division among them helps to quickly and efficiently build a matching process design kit device library A100.

In a possible implementation manner, the process design kit device library A 100 includes a general view for displaying the first device library 110 and the general process layer 132 . In this way, the first device library 110 and the common process layer 132 can be better displayed by using a common view, which helps to improve development efficiency.

In a possible implementation manner, the at least part of the process to be developed is an overlapping part between the process to be developed and the general process 130, and the remaining part of the process to be developed A part is a non-overlapping part between the process recipe to be developed and the general process recipe 130 . In this way, it is helpful to quickly and efficiently build the process design kit device library A 100 matching the process to be developed.

In a possible implementation manner, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively the previous process node and the next process node of the circuit design . In this way, it is helpful to meet the requirements of design migration, and shorten the labor input and time required for design migration.

In a possible implementation manner, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively the previous process node and the next process node of the layout design . In this way, it is helpful to meet the requirements of design migration, and shorten the labor input and time required for design migration.

In a possible implementation manner, the first device library 110 of the process design kit device library A 100 is a reusable part between the pre-migration process and the post-migration process, the The second device library 120 of the process design kit device library A 100 is a non-reusable part between the pre-migration process and the post-migration process. In this way, it is helpful to meet the requirements of design migration, and shorten the labor input and time required for design migration.

In a possible implementation manner, the process design kit device library A 100 is used for design migration between multiple process nodes, for any adjacent paired process between the multiple process nodes Process node, by comparing the process process of the previous process node and the process process of the next process node in the pair of process nodes, based on the first device library 110 and by configuring the second device library 120 so that Design migration between the paired process nodes is completed. In some embodiments, through the first device library 110 of the process design kit device library A 100, at least a part of the process recipe of the next process node in the pair of process nodes is provided and through the process design The second device library 120 of the kit device library A 100 provides the rest of the process flow of the next process node in the pair of process nodes. In some embodiments, the first device library 110 of the process design kit device library A100 is between the process process of the previous process node and the process process of the next process node in the pair of process nodes. The second device library 120 of the process design kit device library A 100 is one of the process flow of the previous process node and the process flow of the next process node in the pair of process nodes. The non-reusable part between. In this way, it is helpful to meet the requirements of design migration, and shorten the labor input and time required for design migration.

FIG. 2 is a schematic diagram of design migration based on a process design kit device library provided by an embodiment of the present application. As shown in FIG. 2 , the process design kit component library B 200 is used for design migration from the first design database 210 to the second design database 212 . Wherein, the process design kit device library B 200 includes a first device library and a second device library. The first device library includes a plurality of first devices, the plurality of first devices are predetermined based on a general process and a general process layer, the second device library includes at least one second device, and the second device library The structure and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer. Through the process design kit device library B 200, the first device library is used to provide at least a part of the process to be developed and the second device library is used to provide the remaining part of the process to be developed, and the process to be developed The at least a portion of the recipe is determined by comparing the process recipe to be developed with the general recipe. The design to be migrated needs to be migrated from the first design database 210 to the second design database 212 . For the design to be migrated, by comparing the pre-migration process 220 and the post-migration process 222 corresponding to the design to be migrated, determine the first device library of the process design kit device library B 200 and determine the process The second device library of the design kit device library B 200 . Finally, the process design kit device library B 200 is used to complete the migration of the design to be migrated. It should be understood that, in some embodiments, the pre-migration process flow 220 may correspond to one process design suite, and the post-migration process flow 222 may correspond to another process design suite, and the process design is generated by integrating the two process design suites Kit Parts Library B 200. In the entire process of chip development, it involves front-end circuit diagram design and back-end layout design, and may also involve process differences and differences between different design databases. Sometimes it is necessary to transfer from one process node to another. The manufacturing node performs process manufacturing level design migration, for example, the first design database 210 shown in FIG. 2 performs design migration to the second design database 212 . Here, the first design database 210 can be regarded as an old design database and is associated with the pre-migration process 220 , and the second design database 212 can be regarded as a new design database and is associated with the post-migration process 222 . The relevant details and technical effects of the process design kit device library B200 can refer to the process design kit device library A 100 shown in FIG. According to specific business scenarios, chip design purposes, customer needs, business scenarios, technology iteration speed, etc., the division between the general device library part and the configurable part can be flexibly adjusted, so as to meet the needs of design migration and shorten the time required for design migration. labor input and time. Therefore, the process design kit device library B 200 shown in FIG. 2 can not only complete the design migration of the front-end circuit diagram, but also can complete the rapid design migration of the back-end layout design. Further, using the process design kit device library B200 shown in Figure 2, that is, the general PDK device library solution, can achieve fast and high-quality design migration of circuit diagrams and layouts, and only need to establish a general PDK on the basis of PDKs of multiple processes The device library, taking FIG. 2 as an example, by comparing the pre-migration process 220 and the post-migration process 222 corresponding to the design to be migrated, determine the first device library of the process design kit device library B 200 and determine The second device library of the PDS device library B 200 .

FIG. 3 is a schematic flowchart of a design migration method provided by an embodiment of the present application. As shown in Figure 3, the design migration method includes the following steps.

Step S310: Provide a process design kit device library including a first device library and a second device library, wherein the first device library includes a plurality of first devices, and the plurality of first devices are based on a general process and a general process The layer is predetermined, the second device library includes at least one second device, the structure of the second device library and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer, the The first device library is used to provide at least a part of the process to be developed and the second device library is used to provide the remaining part of the process to be developed, and the at least a part of the process to be developed is compared with the process to be developed The development process and the determination of the general process.

Step S320: For the design to be migrated, by comparing the pre-migration process and the post-migration process corresponding to the design to be migrated, determine the first device library of the process design kit device library and determine the process design kit The second device library of the device library.

Step S330: complete the migration of the design to be migrated by using the process design kit device library.

Referring to the above steps, for the process to be developed, at least a part of the process to be developed is provided through the first device library of the process design kit device library and the second device library is provided through the process design kit device library. The device library provides the remainder of the process recipe to be developed, the at least a portion of the process recipe to be developed is determined by comparing the process recipe to be developed with the general process recipe. This means that the general process and the first device library in the device library of the process design kit can be fully utilized, thereby reducing the development cycle and utilizing the mature process to reduce costs, while also taking into account the relationship between the process to be developed and the described Process differences between general processes, use the second device library in the process design kit device library to adapt to the process to be developed, which helps to quickly and efficiently build process design kit devices that match the process to be developed library. In this way, the general device library part and the configurable part are realized through the first device library predetermined based on the general process and general process layer and the second device library 120 that can be configured to correspond to the specified process process and can be mapped to the specified process layer decoupling. In this way, through the configurable part of the process design kit device library, that is, the second device library, the adaptation to new semiconductor devices and new semiconductor processes can be flexibly realized, and at the same time, the general device library part of the process design kit device library can also be That is, the first device library to make full use of semiconductor devices with a large number of available models and design rules and mature semiconductor processes that can be applied on a large scale, thereby helping to greatly reduce the development and verification cycle. Therefore, for a specific process, through the division of labor and combination between the first device library and the second device library, a matching process design kit device library can be quickly and efficiently constructed to implement chips using this specific process. design and verification. Moreover, in the entire process of chip development, it involves front-end circuit diagram design and back-end layout design, and may also involve process differences and differences between different design databases. Sometimes it is necessary to transfer from one process node to another. A process manufacturing node performs design migration at the process manufacturing level. Through the device library of the process design kit, using the decoupling of the general device library part and the configurable part, the general device library part and the configurable part can be flexibly adjusted according to specific business scenarios, chip design purposes, customer needs, business scenarios, technology iteration speed, etc. The division between parts can be configured to meet the needs of design migration and reduce the manual investment and time required for design migration.

The design migration method shown in Figure 3 provides a process-level design migration method. The process design kit device library is applied to the design migration between multiple process nodes, and the circuit diagram can be quickly completed on multiple process processes. Design migration, and can also quickly complete layout design migration as convenient as circuit diagram design migration on multi-process processes.

In a possible implementation manner, the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively the previous process node and the next process node of the circuit design . In this way, the rapid completion of design migration of circuit diagrams on multiple manufacturing processes is realized.

In a possible implementation manner, the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively the previous process node and the next process node of the layout design . In this way, the rapid completion of the layout design migration on the multi-process process is realized.

In a possible implementation manner, the first device library of the process design kit device library is a reusable part between the pre-migration process and the post-migration process, and the process design kit The second device library of the device library is a non-reusable part between the pre-migration process and the post-migration process. This helps to meet the needs of design migration and shorten the labor input and time required for design migration.

In a possible implementation manner, the process design kit device library is used for design migration between multiple process nodes, for any adjacent pair of process nodes between the multiple process nodes , by comparing the process flow of the previous process node and the process flow of the next process node in the paired process node, based on the first device library and by configuring the second device library, the paired Design migration between process nodes. In some embodiments, at least a part of the process recipe of the next process node in the pair of process nodes is provided through the first device library of the process design kit device library and through the process design kit device library The second device library provides the rest of the process flow of the next process node in the pair of process nodes. In some embodiments, the first device library of the process design kit device library is the possible relationship between the process flow of the previous process node and the process flow of the next process node in the pair of process nodes. For the reuse part, the second device library of the process design kit device library is a non-reusable process between the process process of the previous process node and the process process of the next process node in the pair of process nodes part. This helps to meet the needs of design migration and shorten the labor input and time required for design migration.

FIG. 4 is a schematic structural diagram of a computing device provided by an embodiment of the present application. The computing device 400 includes: one or more processors 410 , a communication interface 420 and a memory 430 . The processor 410 , communication interface 420 and memory 430 are connected to each other through a bus 440 . Optionally, the computing device 400 may further include an input/output interface 450 connected with an input/output device for receiving parameters set by a user and the like. The computing device 400 can be used to implement part or all of the functions of the device embodiment or the system embodiment in the above-mentioned embodiment of the present application; the processor 410 can also be used to realize part or all of the method embodiment in the above-mentioned embodiment of the present application Steps. For example, the specific implementation of various operations performed by the computing device 400 may refer to the specific details in the above-mentioned embodiments, for example, the processor 410 is used to perform some or all of the steps in the above-mentioned method embodiments or some or all of the operations in the above-mentioned method embodiments . For another example, in the embodiment of the present application, the computing device 400 can be used to realize some or all of the functions of one or more components in the above-mentioned device embodiments, and the communication interface 420 can be specifically used for communication necessary to realize the functions of these devices and components functions, etc., and the processor 410 can specifically be used for processing functions and the like necessary to realize the functions of these devices and components.

It should be understood that the computing device 400 in FIG. 4 may include one or more processors 410, and the multiple processors 410 may cooperate in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner. Provide processing capability, or a plurality of processors 410 can form a processor sequence or a processor array, or a plurality of processors 410 can be divided into main processors and auxiliary processors, or a plurality of processors 410 can have different Architecture such as heterogeneous computing architecture. In addition, the computing device 400 shown in FIG. 4 , the relevant structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, computing device 400 may include more or fewer components than shown in FIG. 4 , or combine certain components, or separate certain components, or have a different arrangement of components.

The processor 410 may have various specific implementation forms. For example, the processor 410 may include a central processing unit (central processing unit, CPU), a graphics processing unit (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processing unit (tensor processing unit, TPU) or a data processing unit (data processing unit, DPU) and a combination of one or more, which are not specifically limited in this embodiment of the present application. Processor 410 may also be a single-core processor or a multi-core processor. The processor 410 may be a combination of a CPU and a hardware chip. The aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. The processor 410 may also be implemented solely by a logic device with built-in processing logic, such as an FPGA or a digital signal processor (digital signal processor, DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or use Wireless LAN interface, etc.

The memory 430 may be a non-volatile memory, for example, a read-only memory (read-only memory, ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), Electrically Erasable Programmable Read-Only Memory (electrically EPROM, EEPROM) or flash memory. The memory 430 can also be a volatile memory, and the volatile memory can be a random access memory (random access memory, RAM), which is used as an external cache. By way of illustration and not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhancedSDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) And direct memory bus random access memory (direct rambus RAM, DR RAM). The memory 430 can also be used to store program codes and data, so that the processor 410 calls the program codes stored in the memory 430 to perform some or all of the operation steps in the above method embodiments, or perform corresponding functions in the above device embodiments. Additionally, computing device 400 may contain more or fewer components than shown in FIG. 4 , or have components arranged in a different manner.

The bus 440 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer fast link (compute express link, CXL), cache coherent interconnect for accelerators (CCIX), etc. The bus 440 can be divided into an address bus, a data bus, a control bus, and the like. In addition to the data bus, the bus 440 may also include a power bus, a control bus, a status signal bus, and the like. However, for the sake of clarity, only one thick line is used in FIG. 4 , but it does not mean that there is only one bus or one type of bus.

The methods and devices provided in the embodiments of the present application are based on the same inventive concept. Since the methods and devices have similar problem-solving principles, the embodiments, implementations, examples or implementations of the methods and devices can be referred to each other, and the repetitions are not Let me repeat. An embodiment of the present application further provides a system, where the system includes multiple computing devices, and the structure of each computing device may refer to the structure of the computing device described above. For the functions or operations that can be realized by the system, reference may be made to the specific implementation steps in the foregoing method embodiments and/or the specific functions described in the foregoing device embodiments, and details are not repeated here.

The embodiment of the present application also provides a computer-readable storage medium, where computer instructions are stored in the computer-readable storage medium, and when the computer instructions are run on a computer device (such as one or more processors), the above-mentioned Method steps in the method examples. For specific implementation of the processor of the computer-readable storage medium executing the above method steps, reference may be made to the specific operations described in the above method embodiments and/or the specific functions described in the above device embodiments, and details are not repeated here.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. This application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware or other arbitrary combinations. When implemented using software, the above-described embodiments may be implemented in whole or in part in the form of computer program products. This application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. coaxial cable, optical fiber, digital subscriber line) or wirelessly (eg, infrared, wireless, microwave, etc.) to another website site, computer, server, or data center. A computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, etc. that includes one or more sets of available media. Usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, random access memory, flash memory, ROM, EEPROM, EEPROM, register or any other form of suitable storage medium.

The present application is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present application. Each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram. These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram. These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

In the above-mentioned embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments. Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, combined or deleted according to actual needs. If the modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims (20)

1. A process design kit device library, characterized in that, the process design kit device library includes: A first device library, wherein the first device library includes a plurality of first devices, and the plurality of first devices are predetermined based on a general process and a general process layer; A second device library, wherein the second device library includes at least one second device, the structure of the second device library and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer , Wherein, for the process to be developed, at least a part of the process to be developed is provided through the first device library of the process design kit device library and provided through the second device library of the process design kit device library The remaining part of the process to be developed, the at least a part of the process to be developed is determined by comparing the process to be developed with the general process, The at least part of the process recipe to be developed is the overlapping part between the process recipe to be developed and the general process recipe, and the remaining part of the process recipe to be developed is the process recipe to be developed and the general process recipe. The non-overlapping parts between the general process and process, The general process recipe is different from the specified process recipe. 2. The process design kit device library according to claim 1, wherein, for the design to be migrated, the process design kit is determined by comparing the pre-migration process and the post-migration process corresponding to the design to be migrated The first device library of the device library and the second device library determining the process design kit device library use the process design kit device library to complete the migration of the design to be migrated. 3. The process design kit device library according to claim 1, wherein the plurality of first devices include transistors, contact holes, and interconnection lines suitable for the general process, and the first device library The electrical characteristics and design rules of each of the plurality of first devices are also included. 4. The process design kit device library according to claim 1, wherein the at least one second device includes basic elements suitable for the specified process, and the second device library also includes the at least one Electrical characteristics and design rules associated with the specified process of the second device. 5. The process design kit device library according to claim 1, wherein the first device library further includes design rules, electrical rules, and layout verification rules associated with the general process. 6. The process design kit device library according to claim 1, wherein the structure of the second device library can also be configured to correspond to the metal layer structure associated with the process to be developed. 7. The process design kit device library according to claim 1, wherein the process design kit device library includes a general view for displaying the first device library and the general process layer. 8. The device library of the process design kit according to claim 2, wherein the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively for the front of the circuit design A process node and a subsequent process node. 9. The device library of the process design kit according to claim 2, wherein the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively for the front of the layout design A process node and a subsequent process node. 10. The process design kit device library according to claim 2, characterized in that, the first device library of the process design kit device library is between the pre-migration process and the post-migration process A reusable part, the second device library of the process design kit device library is a non-reusable part between the pre-migration process and the post-migration process. 11. The process design kit device library according to claim 1, wherein the process design kit device library is used for design migration between multiple process nodes, and for the multiple process nodes Any pair of process nodes immediately adjacent to each other, by comparing the process process of the previous process node and the process process of the next process node in the pair of process nodes, based on the first device library and by configuring the The second device library is used to complete the design migration between the paired process nodes. 12. The process design kit device library according to claim 11, characterized in that, the process of the next process node in the paired process node is provided through the first device library of the process design kit device library At least a portion of a process and a remainder of a process process of a subsequent process node of the pair of process nodes is provided by said second device library of said process design kit device library. 13. The process design kit device library according to claim 12, characterized in that, the first device library of the process design kit device library is the process process of the previous process process node in the paired process process nodes and the reusable part between the process process of the next process node, the second device library of the process design kit device library is the process process of the previous process node and the subsequent process node in the paired process node A non-reusable part between process steps of a process node. 14. A design migration method, characterized in that the design migration method comprises: Provide a process design kit device library including a first device library and a second device library, wherein the first device library includes a plurality of first devices, and the plurality of first devices are predetermined based on a general process and a general process layer , the second device library includes at least one second device, the structure of the second device library and the at least one second device can be configured to correspond to a specified process and can be mapped to a specified process layer, the first device The library is used to provide at least a part of the process to be developed and the second device library is used to provide the remaining part of the process to be developed, and the at least part of the process to be developed is compared with the process to be developed Determined with the general process; For the design to be migrated, by comparing the pre-migration process and the post-migration process corresponding to the design to be migrated, determine the first device library of the process design kit device library and determine the said second device library; and Using the process design kit device library to complete the migration of the design to be migrated, The at least part of the process recipe to be developed is the overlapping part between the process recipe to be developed and the general process recipe, and the remaining part of the process recipe to be developed is the process recipe to be developed and the general process recipe. The non-overlapping parts between the general process and process, The general process recipe is different from the specified process recipe. 15. The design migration method according to claim 14, wherein the design to be migrated is a circuit design, and the pre-migration process and the post-migration process are respectively the previous process for the circuit design The process node and the subsequent process node. 16. The design migration method according to claim 14, wherein the design to be migrated is a layout design, and the pre-migration process and the post-migration process are respectively the previous process for the layout design The process node and the process node of the next process. 17. The design migration method according to claim 14, wherein the first device library of the process design kit device library is a replicable process between the pre-migration process and the post-migration process The second device library of the process design kit device library is a non-reusable part between the pre-migration process and the post-migration process. 18. The design migration method according to claim 14, wherein the process design kit device library is used for design migration between multiple process nodes, for any process node between the multiple process nodes An adjacent pair of process nodes, by comparing the process process of the previous process node and the process process of the next process node in the pair of process nodes, based on the first device library and by configuring the first The two-device library thus completes the design migration between the paired process nodes. 19. The design migration method according to claim 18, characterized in that, the first device library of the process design kit device library provides the information of the process process of the next process node in the paired process node. At least a portion and through said second device library of said process design kit device library provides the remainder of the process recipe of a subsequent process node of the pair of process nodes. 20. The design migration method according to claim 19, wherein the first device library of the process design kit device library is the process process and the subsequent process node of the previous process node in the paired process node. A reusable part between the process steps of a process node, the second device library of the process design kit device library is the process process of the previous process node and the next process in the paired process node A non-reusable portion between process runs of a process node.