CN1161694C - PCI bus period single step interrupt debugging card device and method thereof - Google Patents

Abstract

A single-step debugging card using PCI interface is characterized by that it utilizes bus master controller to send REQ # signal in the period of PCI bus cycle to BE inspected, and requires the master control right of next bus cycle, and latches the signal states of address, data, instruction and group bit enable (BE #) of said bus cycle and utilizes them to display them by means of LED as basis for single-step debugging. Finally, a TRDY # ready signal is sent out by switching of the switching circuit switch, and a device selection signal (DEVSEL #) is pulled to be high level at the same time when the TRDY # ready signal is ended so as to inform a bus main controller on the single-step interrupt debugging card to end the period, thereby achieving the function of single-step debugging.

Description

Pci bus cycle one-step interrupt debugging card unit and method thereof

Technical field

The present invention relates to a kind of one-step debugging card, particularly a kind of application peripheral component connects (Peripheral Component Interconnect, PCI) one-step debugging card at interface alternately.

Background technology

Fig. 1 shows the structure calcspar of present the computer system of widely using.CPU 10 is connected with NB (North bridge is a wafer set) 30 by cpu bus 20; And NB 30 also links to each other with AGP VGA card 60 by AGP bus 50 except joining with storer 40 (can be storeies such as SDRAM, EDORAM).In addition, 30 of NB join with SB (South bridge also is a wafer set) 80 via pci bus 70, in order to Data transmission and information; And SB80 except with hard disk (HD) 90, CD player (CD ROM) 100, USB (universal serial bus) (UniversalSerial Bus, USB) 110, input media (such as mouse, keyboard etc.) 120 joins, outside access or input data, also respectively by XD bus 130 and isa bus 140, join with Basic Input or Output System (BIOS) (BIOS) 150 and acoustic apparatus (Audio, for example adlib) 160.

Traditional one-step interrupt debugging card is applied in industrial standard architectures form bus (IndustryStandard Architecture BUS, ISA BUS) on, force by the IOCHRDY signal that is used for finishing the isa bus cycle and to maintain low level, reaching the purpose that prolongs these bus cycles, and make relative address and data line bus state be able to be inspected.

And on pci bus, CPU needs by the PCI/ISA bridge read cycle to be transferred to isa bus by pci bus for reading of legacy system BIOS, treat that the BIOS data by after being positioned at ROM on the isa bus and reading, send data back to pci bus by isa bus by the PCI/ISA bridge again.Because the BIOS data read cycle must be responded by the PCI/ISA bridge on pci bus, that is relevant pci cycle control signal such as DEVSEL#, TRDY# etc. produce by the PCI/ISA bridge, therefore can not just reach the purpose of suspending the bus cycles merely by maintaining high level in order to signal such as the TRDY# that finishes pci cycle.

And the present Debug Card that is applied on the market on the pci bus, or still need to interrupt the auxiliary of Debug Card by isa bus, maintain low level by forcing in order to the IOCHRDY signal that finishes the isa bus cycle, and reach the purpose that prolongs these bus cycles, or just part BIOS data and address latch are read to memory buffer more one by one in the start initial stage, and tool does not really suspend the bus cycles, and and then makes the function inspect immediately.

With regard to a normal pci bus cycle, when the FRAME# signal becomes low level by high level, promptly represent the beginning of pci bus cycle.At this moment, what present on the AD bus is the address of addressing that pci bus cycle is desired, and on the C/BE# bus, present be the instruction.Whether all devices can be decoded to this address and instruction on the pci bus cycle, itself be the destination apparatus (target device) of this pci bus cycle to determine.If then send the DEVSEL# signal, and the DEVSEL# signal maintained low level, with as responding.When this destination apparatus is finished read-write, can send TRDY# signalisation host pci and carry out follow-up data transfer operation, if during these bus cycles, there is any bus master controller (bus master) to send the control of REQ# semaphore request bus, and PCI moderator (arbiter) is also responded the GNT# signal, after then finishing in these bus cycles, to obtain the ownership of next bus cycles by this bus master controller, that is relevant pci bus control signal such as FRAME#, IRDY# and address, instruction etc. will be sent by this bus master controller.

Summary of the invention

The one-step debugging card at application PCI interface proposed by the invention promptly utilizes described bus master controller function.With desire to inspect the ownership that sends next bus cycles of REQ# semaphore request during the pci bus cycle, and address that should the bus cycles, data, instruction, signal conditions such as BE# are latched and are shown by LED, after the PCI arbiter is responded the approval of GNT# signal, one-step interrupt debugging card promptly sends specific address in following one-period, instruction and FRAME#, signals such as IRDY#, address that this is specific and instruction are after the destination apparatus on the one-step interrupt debugging card (TargetDevice) decoding, send the DEVSEL# signal by this destination apparatus, and it is maintained low level.Suspend operation pci bus on by this in bus master controller cycle, make the address of being latched during the last bus cycles, data, instruction, signal condition such as BE# thereby always be shown on the LED is as the foundation of inspecting of step-by-step debugging.And switch switch by one at last, and send a TRDY# signal, and when this TRDY# signal ended, be high level with the DEVSEL# signal boost simultaneously, finish this cycle with the bus master controller on the notice one-step interrupt debugging card.

The invention provides a kind of pci bus cycle single step and interrupt the method for debug, this method comprises the following step at least: send a request signal (REQ#) by bus master controller, require the control of these bus cycles; Address, data, instruction and the hyte of this bus cycles enabled signal conditions such as (BE#) to be latched and is shown by display; After the PCI moderator is responded a handshaking signal (ACK#) approval, should send this specific address, this instruction, frame signal (FRAME#) and IRDY# the bus cycles in next and signal such as be ready for; The address that this is specific, instruction are sent a device by this destination apparatus and are selected signal (DEVSEL#) after destination apparatus decoding; Showing signal conditions such as the address, data, instruction and the hyte that are latched during the last bus cycles enable on the display; And, send a TRDY# and be ready for signal, to finish this pci bus cycle by a switching switch.

The present invention also provides a kind of pci bus cycle one-step interrupt debugging card, and this Debug Card comprises at least: control logic circuit is latched in address/instruction, in order to producing this address/instruction control signal, and by this address/instruction of an address/instruction latches; Address/instruction buffer control logic circuit controls signal to one address/instruction buffer by described this address of latching/instruction output one; Data/hyte enable signal latchs control logic circuit, in order to producing the latch control signal that this data/hyte enables bus, and lives this data/hyte enable signal by one data/hyte enable signal latches; The bus master controller control signal produces logical circuit, in order to send the control that request signal (REQ#) requires this bus, described bus master controller control signal produces logical circuit, also produce logical circuit by a bus master controller address/data, latch this address/data signal state during making last pci bus cycle, and this address/data signal shown on this display, described bus master controller control signal produces logical circuit, also enable to produce logical circuit by a bus master controller instruction/hyte, latch this instruction/hyte enable signal state during making last this pci bus cycle, and should instruct/the hyte enable signal is shown on this display; Reach one and switch switch, send a TRDY# and be ready for signal, finish this pci bus cycle to notify this bus master controller on this pci bus cycle one-step interrupt debugging card.

Description of drawings

Fig. 1 is the structure calcspar of known computer systems;

Fig. 2 is the present embodiment sequential chart, describes the different bus transmission frequency, the relation of the timing that is produced with foundation pci bus transmission frequency; And

Fig. 3 is that debug signal flow synoptic diagram is interrupted in the single step of the embodiment of the invention.

Embodiment

Relevant detailed content of the present invention and technology, accompanying drawings is as follows.

The sequential chart of the embodiment of the invention as shown in Figure 2, Fig. 2 shows the different bus transmission frequency, the relation of the timing that is produced with foundation pci bus transmission frequency.With regard to (Peripheral Component Interconnect bus cycle of the normal mutual connecting bus of the peripheral component cycle; PCI buscycle), when frame signal (FRAME#) when becoming low level, promptly represent the beginning of pci bus cycle by high level.At this moment, what present on the AD bus is the address (address) of addressing that pci bus cycle is desired, and on the C/BE# bus, present be the instruction (command).Whether and all devices can be decoded to this address and instruction on the pci bus cycle, itself be the destination apparatus (target device) of this pci bus cycle to determine.If then carrying device is selected signal (DEVSEL#), and the DEVSEL# signal is maintained low level, with as response.When this destination apparatus is finished read-write, can send TRDY# is ready for the signalisation host pci and carries out follow-up data transfer operation, if during these bus cycles, there is any bus master controller (bus master) to send the control of REQ# semaphore request bus, and PCI moderator (arbiter) is also responded a GNT# signal, after then finishing in these bus cycles, to obtain the ownership of next bus cycles by this bus master controller, that is relevant pci bus control signal such as FRAME#, IRDY# and address, instruction etc. will be sent by this bus master controller.

The one-step debugging card at application PCI interface proposed by the invention promptly utilizes described bus master controller function.With desire to inspect the ownership that sends next bus cycles of REQ# semaphore request during the pci bus cycle, and signal condition such as address that should the bus cycles, data, instruction, BE# is latched and is shown by LED, after the PCI moderator is responded the approval of GNT# signal, one-step interrupt debugging card promptly sends signals such as specific address, instruction and FRAME#, IRDY# in following one-period, address that this is specific and instruction are after destination apparatus on the one-step interrupt debugging card (Target Device) decoding, send the DEVSEL# signal by this destination apparatus, and it is maintained low level.Suspend operation pci bus on by this in bus master controller cycle, make signal condition such as the address of being latched during the last bus cycles, data, instruction, BE# thereby be shown on the LED always, as the foundation of inspecting of step-by-step debugging.And switch by commutation circuit at last, send a TRDY# and be ready for signal, and when this TRDY# is ready for signal ended, simultaneously the DEVSEL# signal is drawn and be high level, finish this cycle with the bus master controller on the notice one-step interrupt debugging card.

Fig. 3 is that debug signal flow synoptic diagram is interrupted in the single step of the embodiment of the invention, further specifies as follows in conjunction with Fig. 2.

When the pci bus cycle desiring to inspect when beginning, host pci (as the Northbridge among Fig. 1 30) can with the unit address (device address) of desire addressing place the AD bus, and pci bus instruction (bus command) is placed C/BE#, and the FRAME# signal drawn be low level.At this moment, all devices (device) can be decoded to address and instruction on the pci bus, determining itself whether being the destination apparatus (target device) of these bus cycles, the destination apparatus that decoding meets the DEVSEL# signal can be drawn into low level as response.Latch the control signal that control logic circuit 170 is produced by address/instruction, desire to inspect address and the instruction of bus cycles and be latched within address/instruction latch 180.

Host pci draws the IRDY# signal to be low level in beginning to read and write when handling.And destination apparatus is when finishing read-write and handle, and TRDY# drawn be low level.Data/BE# signal latch control logic circuit 240 within data/BE# latch 250, and shows the Data of desire to inspect bus cycles and BE# signal latch when IRDY# and TRDY# are low level simultaneously by display circuit 260.Simultaneously, the output by the control signal that the address/instruction buffer control circuit 210 is produced is opened impact damper 220 shows address and the instruction that is latched in latch 180 by display circuit 230.The output of impact damper 220 only when IRDY# and TRDY# are low level, open during bus cycles of desiring to inspect, all keep under all the other situations closing.

During these bus cycles, bus primary controller control signal generation logical circuit 270 draws REQ# and is low level, in order to require the ownership of follow-up bus cycles to PCI moderator (being positioned at North bridge 30).After the PCI moderator draws the GNT# signal into low level response approval, after the bus master controller on the one-step interrupt debugging card finished in these bus cycles, obtain the control of bus.

When the bus master controller cycle begins, the bus master controller address/data produce circuit 280 and Command/BE# produce logical circuit 290 will specific address and instruction place AD and C/BE# bus respectively, the bus master controller control signal produces logical circuit 270 and priority and FRAME# and IRDY# are drawn is low level.For avoiding on the bus other devices to send DEVSEL# during the bus master controller cycle and the TRDY# signal causes end cycle, this specific address is the specific objective device that is used on the addressing one-step interrupt debugging card.By latch 180 latch addresses and instruction, and through after the address/190 decodings of instruction decode logic circuit meet, this destination apparatus produces logical circuit 200 by the DEVSEL# signal and DEVSEL# is drawn to low level responds this cycle.And because the output of impact damper 220 keeps closed condition, so particular address and instruction that bus master controller is sent can't be shown.

After change-over switch 300 is pressed, produces an on/off switch signal, and suppress circuit 310 by spring and eliminate bounce when switching.Destination apparatus produces logical circuit 320 by the TRDY# signal and the TRDY# signal is drawn is low level, continues behind the pci cycle it is drawn to be high level.And produce logical circuit 200 by the DEVSEL# signal and the DEVSEL# signal is drawn be high level, bus master controller also draws IRDY# by bus master controller control signal generation circuit 270 and is high level simultaneously, finishes this bus master controller cycle.Signal conditions such as the address of latching, cushioning and show by bus master controller, data, instruction, BE#, also thereby be able to show by display circuit 230 and 260 always.And bus master controller control signal generation circuit 270 is drawn REQ# during the bus master controller cycle and is high level, make bus master controller when the bus master controller end cycle, return the ownership of bus, and make pci bus proceed to be interrupted the following one-period in cycle.

Though the present invention is described with aforesaid preferable enforcement; but this embodiment is not in order to limit the present invention; those of ordinary skills; under the premise without departing from the spirit and scope of the present invention; can make amendment to the present invention, so protection scope of the present invention is as the criterion with the accompanying Claim scope.

Claims (11)

1. A method for PCI bus cycle single-step interrupt debugging, the method at least comprises the following steps: A request signal (REQ#) is sent by the bus master to request control of the bus cycle; The address, data, instruction and byte group enable (BE#) and other signal states of the bus cycle are latched and displayed on the display; When the PCI arbiter responds to an acknowledgment signal (ACK#) after approval, it sends specific signals such as the address, the command, the frame signal (FRAME#) and the IRDY# in the next bus cycle; After the specific address and instruction are decoded by a target device, a device selection signal (DEVSEL#) is sent by the target device; Displays on the display the state of signals such as address, data, command and bit enable latched during the previous bus cycle; and By means of a toggle switch, a TRDY# ready signal is sent to end the PCI bus cycle. 2. The method as claimed in claim 1, wherein the step of sending the device selection signal by the target device is to maintain the device selection signal at a low level to suspend the bus master cycle by the bus master operations on the PCI bus. 3. The method as claimed in claim 1, wherein the step of ending the PCI bus cycle is to pull the device selection signal to high level simultaneously by the TRDY# ready signal to notify the bus master The controller ends the bus cycle. 4. The method as claimed in claim 1, wherein the switching switch uses a bouncing suppression circuit to eliminate the unexpected bouncing phenomenon generated during on/off switching. 5. A PCI bus cycle single-step interrupt debugging card, the debugging card at least includes: The address/command latch control logic circuit is used to generate the address/command control signal and latch the address/command through an address/command latch; The address/command buffer control logic circuit outputs a control signal to an address/command buffer through the latched address/command; The data/byte enable signal latch control logic circuit is used to generate the latch control signal of the data/byte enable bus, and latch the data/byte enable signal latch through a data/byte enable signal latch bit enable signal; The bus master control signal generation logic circuit is used to send a request signal (REQ#) to request the control right of the bus, and the bus master control signal generation logic circuit is also generated by a bus master address/data The logic circuit makes the state of the address/data signal latched during the previous PCI bus cycle, and displays the address/data signal on the display. The control signal of the bus master controller generates the logic circuit, and also passes through a bus master. The controller command/byte enable generation logic circuit, so that the command/byte enable signal state is latched during the previous PCI bus cycle, and the command/byte enable signal is displayed on the display; and A toggle switch sends a TRDY# ready signal to notify the bus master on the PCI bus cycle single-step interrupt debug card to end the PCI bus cycle. 6. PCI bus cycle single-step interrupt debugging card as claimed in claim 5, wherein said address/command latch control logic circuit also includes an address/command decoding logic circuit, in order to decode this address/command, to determine whether the address/command is the target device for the PCI bus cycle. 7. The PCI bus cycle single-step interrupt debugging card as claimed in claim 6, wherein when also comprising the target device meeting the PCI bus cycle, a device selection signal (DEVSEL#) generates a logic circuit, and the next PCI bus The device select signal is sent out in the cycle as a response step. 8. The PCI bus cycle single-step interrupt debugging card as claimed in claim 5, wherein said address/command buffer displays the address/command through a display circuit for detection. 9. The PCI bus cycle single-step interrupt debugging card as claimed in claim 5, wherein said data/byte enable signal latch displays the data/byte enable signal through a display circuit for detection. 10. The PCI bus cycle single-step interrupt debugging card as claimed in claim 5, wherein said end of the PCI bus cycle is by pulling the device selection signal to high level at the end of the TRDY# ready signal , to notify the bus master on the PCI bus cycle single-step interrupt debug card to end the PCI bus cycle. 11. The PCI bus cycle single-step interrupt debugging card as claimed in claim 5, wherein said switching switch eliminates the unexpected bouncing phenomenon when switching on/off through a bouncing suppression circuit.

Images