CN116166830A - Data processing system, electronic component, electronic device and data processing method - Google Patents

Abstract

The present disclosure provides a data processing system, an electronic component, an electronic device and a data processing method, aiming at reducing the pressure of decoded data on system bandwidth. In the present disclosure, the data processing system includes a cache module, and the cache module is used to judge whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module; the target data corresponding to the current data refers to: Data that has been output by the decoder and belongs to the same processing unit as the current data; the cache module is also used to input the current data and the target data corresponding to the current data as a processing unit when the total length is equal to the unit processing length To the compression module for compression, thereby effectively compressing the size of the decoded data and reducing the pressure of the decoded data on the system bandwidth; in addition, the cache module is also used to store the current data when the total length is not equal to the unit processing length.

Description

Data processing system, electronic component, electronic device and data processing method

technical field

The present disclosure relates to the field of chip technology, and in particular to a data processing system, electronic components, electronic equipment and a data processing method.

Background technique

As the display format changes from 1080P to 4K to 8K, the decoded image data puts a lot of pressure on the system bandwidth. Taking the video playback scene as an example, the video decoder decoder in the SoC chip decodes the image data, and stores the decoded data to the GDDR (graphics double data rate) memory through the bus, and the display controller DC (display controller) reads data from the GDDR memory through the bus and displays it. During the above-mentioned video playback process, the decoded data volume is very large, which puts a lot of pressure on the system bandwidth.

Contents of the invention

The purpose of the present disclosure is to provide a data processing system, an electronic component, an electronic device and a data processing method, aiming at reducing the pressure of decoded data on the system bandwidth.

According to one aspect of the present disclosure, a data processing system is provided, and the data processing system includes a cache module:

The cache module is used to judge whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module; data belonging to the same processing unit;

The cache module is also used to input the current data and the target data corresponding to the current data as a processing unit to the compression module for compression when the total length is equal to the unit processing length;

The cache module is also used to store current data when the total length is not equal to the unit processing length.

In a feasible implementation manner of the present disclosure, the cache module is further configured to determine the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder.

In a feasible implementation of the present disclosure, when the cache module determines the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder, it is specifically used for:

Compare the address of the current data with the address range of each processing unit; the address range of each processing unit is determined according to the minimum head address of the processing unit and the processing length of the unit, and the minimum head address of the processing unit refers to the processing unit The smallest first address among the first addresses of each data in the unit;

When the address of the current data is located in the address range of a processing unit, each data belonging to the processing unit is determined as the target data corresponding to the current data.

In a feasible implementation manner of the present disclosure, the cache module includes a plurality of first cache units, and each first cache unit is used to store data that has been output by the decoder and belongs to the same processing unit;

The cache module is also used to allocate an empty first cache unit for the current data when there is no corresponding target data for the current data, and record the processing unit state information corresponding to the current data;

The processing unit state information includes at least one of the following information: the address of the current data, the length of the current data, and the identifier of the first cache unit allocated for the current data.

In a feasible implementation of the present disclosure, the cache module is further configured to store the current data in the Cache the memory outside the module, and record the status information of the processing unit corresponding to the current data;

The processing unit status information includes at least one of the following information: the address of the current data, the length of the current data, and the address of the current data in the memory.

In a feasible implementation of the present disclosure, when the cache module stores the current data when the total length is not equal to the unit processing length, it is specifically used for:

When the total length is not equal to the unit processing length, according to the processing unit state information corresponding to the current data, the current data is stored in the corresponding first cache unit, or stored in the memory;

Update the processing unit status information corresponding to the current data.

In a feasible implementation manner of the present disclosure, the cache module further includes a state cache unit, and the state cache unit is used to store the state information of the processing unit.

In a feasible implementation manner of the present disclosure, the cache module further includes a second cache unit;

The cache module is also used to store the current data in the second cache unit when the total length is equal to the unit processing length and the target data corresponding to the current data is stored in the memory, and read the target data corresponding to the current data from the memory to Second cache unit.

In a feasible implementation of the present disclosure, before judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module, the cache module is also used to: judge whether the current data is a line of image data the last part;

The cache module is also used to calculate the total length of the current data and the target data corresponding to the current data when the current data is the last part of a line of image data, and when the total length is less than the unit processing length, process the current data Supplementing, so that the total length of the supplemented current data and target data is equal to the unit processing length, and then inputting the supplemented current data and target data as a processing unit to the compression module for compression.

In a feasible implementation of the present disclosure, when the cache module judges whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module, it is specifically used for:

When the current data is not the last part of a line of image data, it is judged whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module.

In a feasible implementation of the present disclosure, before judging whether the current data is the last part of a row of image data, the cache module is further used to: judge whether the length of the current data is equal to the unit processing length;

When the cache module judges whether the current data is the last part of a row of image data, it is specifically used for: judging whether the current data is the last part of a row of image data when the length of the current data is less than the unit processing length;

The cache module is also used for inputting the current data as a processing unit to the compression module for compression when the length of the current data is equal to the unit processing length.

In a feasible implementation of the present disclosure, the data processing system further includes a decoder and a compression module;

The decoder is used to decode the image data and output the decoded data;

The compression module is used to compress the data input by the cache module.

In a feasible implementation of the present disclosure, when decoding image data, the decoder is specifically used for:

In the case where the image data is image data divided by tiles, the image data is decoded in tile order.

According to another aspect of the present disclosure, an electronic component is further provided, and the electronic component includes the data processing system described in any one of the above embodiments. In some usage scenarios, the product form of the electronic device is embodied as a SoC chip, a graphics card or a CPU motherboard.

According to another aspect of the present disclosure, there is also provided an electronic device, which includes the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

According to another aspect of the present disclosure, there is also provided a data processing method, the method comprising:

Determine whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module; the target data corresponding to the current data refers to: it has been output by the decoder and belongs to the same process as the current data unit data;

When the total length is equal to the unit processing length, the current data and the target data corresponding to the current data are input to the compression module as a processing unit for compression;

In the case where the total length is not equal to the unit processing length, the current data is stored.

In a feasible implementation of the present disclosure, the method further includes:

According to the address of the current data and the address of the data output by the decoder, the target data corresponding to the current data is determined.

In a feasible implementation of the present disclosure, the target data corresponding to the current data is determined according to the address of the current data and the address of the data output by the decoder, including:

Compare the address of the current data with the address range of each processing unit; the address range of each processing unit is determined according to the minimum head address of the processing unit and the processing length of the unit, and the minimum head address of the processing unit refers to the processing unit The smallest first address among the first addresses of each data in the unit;

When the address of the current data is located in the address range of a processing unit, each data belonging to the processing unit is determined as the target data corresponding to the current data.

In a feasible implementation of the present disclosure, the method further includes:

In the case that the current data does not have corresponding target data, allocate an empty first cache unit for the current data from a plurality of first cache units, and store the current data in the empty first cache unit; each first The cache unit is used to store data that has been output by the decoder and belongs to the same processing unit;

Record the processing unit status information corresponding to the current data; the processing unit status information includes at least one of the following information: the address of the current data, the length of the current data, and the identifier of the first cache unit allocated for the current data.

In a feasible implementation of the present disclosure, the method further includes:

When the current data does not have corresponding target data, and there is no empty first cache unit in the plurality of first cache units, store the current data in an external memory, and record the processing unit state information corresponding to the current data;

The processing unit status information includes at least one of the following information: the address of the current data, the length of the current data, and the address of the current data in the memory.

In a feasible implementation of the present disclosure, when the total length is not equal to the unit processing length, storing the current data includes:

When the total length is not equal to the unit processing length, according to the processing unit state information corresponding to the current data, the current data is stored in the corresponding first cache unit, or stored in the memory;

Update the processing unit status information corresponding to the current data.

In a feasible implementation of the present disclosure, the method further includes:

When the total length is equal to the unit processing length and the target data corresponding to the current data is stored in the memory, the current data is stored in the second cache unit, and the target data corresponding to the current data is read from the memory to the second cache unit.

In a feasible implementation of the present disclosure, before judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module, the method further includes: judging whether the current data is the last row of image data a part;

The method also includes: in the case that the current data is the last part of a line of image data, calculating the total length of the current data and the target data corresponding to the current data, and in the case that the total length is less than the unit processing length, performing processing on the current data Supplementing, so that the total length of the supplemented current data and target data is equal to the unit processing length, and then inputting the supplemented current data and target data as a processing unit to the compression module for compression.

In a feasible implementation of the present disclosure, judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module includes:

When the current data is not the last part of a line of image data, it is judged whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module.

In a feasible implementation of the present disclosure, before judging whether the current data is the last part of a line of image data, the method further includes: judging whether the length of the current data is equal to the unit processing length;

Judging whether the current data is the last part of a row of image data includes: judging whether the current data is the last part of a row of image data when the length of the current data is less than the unit processing length;

The method further includes: when the length of the current data is equal to the unit processing length, inputting the current data as a processing unit to the compression module for compression.

Description of drawings

FIG. 1 is a schematic structural diagram of a data processing system provided by an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a cache module proposed by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an image decoding process proposed by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a data processing flow proposed by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a data processing flow proposed by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a data processing flow proposed by an embodiment of the present disclosure;

FIG. 7 is a schematic flowchart of a data processing method proposed by an embodiment of the present disclosure.

Detailed ways

Before introducing the embodiments of the present disclosure, it should be noted that:

Some embodiments of the present disclosure are described as a processing flow. Although each operation step of the flow may be labeled with a sequential step number, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

The embodiments of the present disclosure may use the terms "first", "second" and so on to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

The term "and/or" may be used in the embodiments of the present disclosure, and "and/or" includes any and all combinations of one or more listed associated features.

It should be understood that when describing the connection relationship or communication relationship between two components, unless it is clearly indicated that the two components are directly connected or communicated directly, otherwise, the connection or communication of the two components can be understood as a direct connection or communication, and also It can be understood as indirect connection or communication through intermediate components.

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the exemplary embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, and Not an exhaustive list of all embodiments. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

As the display format changes from 1080P to 4K to 8K, the decoded image data puts a lot of pressure on the system bandwidth. In order to reduce the pressure of the decoded data on the system bandwidth, the inventors of the present disclosure thought of connecting a compression module at the output end of the decoder, and using the compression module to compress the data output by the decoder, thereby effectively compressing the size of the decoded data, Reduce the pressure of decoded data on system bandwidth. However, in the actual implementation, the inventor found that there is a mismatch between the decoder and the compression module. After analysis, the inventor further found that the reason for this mismatch is mainly:

On the one hand, the compression module compresses the data according to a fixed unit processing length. For example, if the fixed unit processing length is 256 bytes, the data length input to the compression module must be equal to 256 bytes each time, otherwise the compression module cannot perform compression correctly. On the other hand, when the decoder decodes image data, it usually outputs data according to a fixed length (such as 256bytes). In this case, since the data length output by the decoder is equal to the unit processing length of the compression module, the decoder There is a match between the compression module. However, when the encoding format of the image data is the H.265 encoding format or VP9 encoding format, the H.265 encoding format and VP9 encoding format have the function of dividing the image by any tile. In this case, the decoder will follow The image data is decoded sequentially in tiles, and the output data is usually less than 256bytes when decoding to a tile boundary, which causes no adaptation between the decoder and the compression module.

Based on the above situation, the inventors of the present disclosure provide a data processing system, electronic components, electronic equipment and data processing method through the following embodiments, aiming at reducing the pressure of the decoded data on the system bandwidth, and further overcoming the problem of decoders and compression modules The problem of incompatibility between.

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a data processing system provided by an embodiment of the present disclosure. As shown in FIG. 1 , the data processing system includes a cache module for judging whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module. Wherein, the target data corresponding to the current data refers to data that has been output by the decoder and belongs to the same processing unit as the current data.

The cache module is also used for inputting the current data and the target data corresponding to the current data as a processing unit to the compression module for compression when the total length is equal to the unit processing length.

The cache module is also used to store current data when the total length is not equal to the unit processing length.

In this disclosure, a cache module is set between the decoder and the compression module. After the cache module obtains the current data output by the decoder, it calculates the total length of the current data and the target data corresponding to the current data, and judges whether the total length is equal to the compression The unit processing length of the module. If they are equal, it means that the current data and its corresponding target data can be processed by the compression module, so the current data and its corresponding target data can be input to the compression module as a processing unit for compression processing. If they are not equal, it means that the current data and its corresponding target data cannot be processed by the compression module, so the current data can be stored temporarily, and then input to the compression module for compression processing after the unit processing length is enough.

For ease of understanding, as an example, it is assumed that the unit processing length of the compression module is equal to 256 bytes. It is also assumed that the length of the current data output by the decoder is 64 bytes, and the target data corresponding to the current data includes two copies, and the length of the two target data is both 96 bytes, so the total length of the current data and the corresponding target data is equal to 64+96+ 96=256bytes, which is equal to the unit processing length of the compression module, and then the current data and its corresponding target data are input to the compression module as a processing unit for compression processing.

Or assume that the length of the current data output by the decoder is 96 bytes, and the target data corresponding to the current data is only one copy, and the length of the target data is 96 bytes, so the total length of the current data and the corresponding target data is equal to 192 bytes, which is smaller than the compression module The unit handles the length, thus temporarily storing the current data. Wait until the decoder outputs the same processing unit as the current data and can make up 256 bytes of data, and then input the processing unit to the compression module for compression processing.

In this disclosure, by setting a cache module between the decoder and the compression module, the cache module stores the current data when the total length of the current data and the target data corresponding to the current data is not equal to the unit processing length of the compression module. When the total length of the data and the target data corresponding to the current data is equal to the unit processing length of the compression module, the current data and the target data corresponding to the current data are input to the compression module as a processing unit for compression, and the compression module outputs the compressed data , so that the pressure of the decoded data on the system bandwidth can be effectively reduced, and the problem of incompatibility between the decoder and the compression module can also be overcome.

In some specific implementations of the present disclosure, the cache module is further configured to determine the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder.

In this disclosure, after the cache module determines the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder, it judges whether the total length of the current data and its corresponding target data is equal to that of the compression module. Unit processing length.

When the cache module determines the target data corresponding to the current data, a relatively simple and efficient way to determine is: compare the address of the current data with the respective address range of each processing unit; the address range of each processing unit is based on the processing Determined by the minimum initial address of the unit and the processing length of the unit, the minimum initial address of the processing unit refers to the smallest initial address among the initial addresses of each data in the processing unit; when the address of the current data is located in the address range of a processing unit Next, each data belonging to the processing unit is determined as the target data corresponding to the current data.

Among them, the cache module can pre-calculate the address range of each processing unit. For example, when the decoder outputs the first piece of data of a processing unit, the cache module can determine the address interval of the first piece of data according to the first address of the first piece of data and the unit processing length. The address range of the processing unit. The specific determination method may be: use the first address of the first data as the lower limit of the address range, and use the address corresponding to the first address of the first data plus the unit processing length as the upper limit of the address range. Among them, the first piece of data of the processing unit is the piece of data with the smallest first address in the processing unit, in other words, it is the piece of data with the smallest address among the continuous 256bytes data (assuming that the unit processing length is equal to 256bytes).

When the cache module determines the target data corresponding to the current data, it compares the address of the current data (which can be the first address or the end address) with the address range of each processing unit. If the address of the current data is within the address range of a certain processing unit , each data in the processing unit is the target data corresponding to the current data, in other words, the current data also belongs to the processing unit. For example, the address of the current data is exactly within the address range [b1,b1+256] of the processing unit b, then the current data belongs to the processing unit b, and the data in the processing unit b is the target data corresponding to the current data.

In addition, if the address of the current data is not located within the address range of any processing unit, it means that the current data does not have corresponding target data. In other words, it shows that the current data is the first piece of data in a processing unit, and then the address range of the processing unit can be determined according to the first address of the current data and the unit processing length.

In the present disclosure, when determining the target data corresponding to the current data, by comparing the current data with the address range of each processing unit, the target data corresponding to the current data can be determined. The determination method is simple and efficient, and it is beneficial to reduce the SoC chip of complexity.

In addition, when the cache module determines the target data corresponding to the current data, another determination method is: according to the first address and length of the data with the largest first address in the processing unit, calculate the end address of the data, and judge the end address. Whether the address is equal to the first address of the current data, and if they are equal, each data belonging to the processing unit is determined as the target data corresponding to the current data.

For ease of understanding, for example, assuming that processing unit a includes data x and data y, where the first address of data x is the largest, the end address of data x is calculated according to the first address of data x and the length of data x, and Compare the end address of data x with the first address of the current data, if they are equal, determine the data x and data y included in the processing unit a as the target data corresponding to the current data, and also indicate that the current data belongs to the processing unit a.

In some specific implementations of the present disclosure, as shown in FIG. 2, FIG. 2 is a schematic structural diagram of a cache module proposed by an embodiment of the present disclosure. The cache module includes a plurality of first cache units, and each first cache unit is used for Data that has been output by the decoder and belongs to the same processing unit is stored.

The cache module is further configured to allocate an empty first cache unit for the current data and record the status information of the processing unit corresponding to the current data when there is no corresponding target data for the current data. Wherein, the processing unit state information includes at least one of the following information: the address of the current data, the length of the current data, and the identifier of the first cache unit allocated for the current data.

In this disclosure, if the current data does not have corresponding target data, that is, among the data output by the decoder, there is no data belonging to the same processing unit as the current data, which means that the current data is the first in a processing unit. copies of data.

If the current data is the first piece of data in a processing unit, the cache module will allocate an empty first cache unit for the current data, which is used to cache the current data and the subsequent output of the decoder Data belonging to the same processing unit as the current data. In addition, the cache unit will also record the processing unit status information corresponding to the current data. The processing unit status information may include the first address of the current data, the length of the current data, and the identifier of the first cache unit allocated for the current data, wherein the first The identifier of the cache unit may specifically be index information index of the first cache unit.

In some specific implementation manners, the status information of the processing unit may also include an address range corresponding to the processing unit. For the calculation method of the address range, reference may be made to the above-mentioned embodiments. To simplify the description, details are not repeated here. When the cache module subsequently receives the new data output by the decoder, it can determine the processing unit to which the new data belongs and the corresponding target data according to the address interval in the state information of each processing unit.

In some specific implementation manners, the processing unit status information may further include storage indication information, and the storage indication information is used to indicate whether the data of the processing unit is stored in the cache module.

It should be noted that the first cache unit in this disclosure is empty, and there may be the following situations: 1) no data is stored in the first cache unit; 2) all data stored in the first cache unit has been input to the compression module . In other words, if no data is stored in a first cache unit, the first cache unit is empty. If all the data stored in a first cache unit has been input to the compression module, the first cache unit is also considered to be empty.

FIG. 2 exemplarily shows six first cache units, and each first cache unit at least includes: a data segment and a validity indication segment. Wherein, the data segment of each first buffer unit is used to store data output by the decoder, and these data belong to the same processing unit and have not been input to the compression module. The length (ie storage capacity) of the data segment of each first cache unit is greater than or equal to the unit processing length. In order to reduce the cost and/or reduce the occupation of the chip area, the length of the data segment of each first cache unit may be configured to be equal to the unit processing length, such as 256 bytes. The validity indication segment of each first cache unit is used to store a validity identifier, and the validity identifier is used to indicate whether the first cache unit is empty, that is, indicates whether the first cache unit can be allocated. As shown in Figure 2, when the validity flag of the first cache unit is 1, it means that the first cache unit is not empty, and the first cache unit has been occupied, so it cannot be allocated; when the validity of the first cache unit When the flag is 0, it means that the first cache unit is empty, the first cache unit is not occupied, and thus can be allocated.

In Fig. 2, wherein the first cache unit A, the first cache unit B and the first cache unit C are not empty, the first cache unit A, the first cache unit B and the first cache unit C have respectively stored the processing unit a , partial data of processing unit b and processing unit c. And the first cache unit D, the first cache unit E and the first cache unit F are all empty. If the current data output by the decoder is the first piece of data in a processing unit, the decoder can allocate a first cache unit for the current data from the first cache unit D, the first cache unit E, and the first cache unit F , and store the current data in the allocated data segment of the first cache unit, and update the validity flag of the first cache unit to 1.

In some specific implementation manners of the present disclosure, as shown in FIG. 2 , the cache module may further include a state cache unit, which is used to store the state information of the processing unit. In some implementation manners, there are multiple state buffer units, and each state buffer unit is used to store processing unit state information of a processing unit. In some implementation manners, there is one state buffer unit, and the state buffer unit is used to store the processing unit state information of each processing unit. In some implementation manners, the number of state buffer units is several, and each state buffer unit is used to store processing unit state information of a part of processing units.

In some specific implementations of the present disclosure, considering that the H.265 encoding format and the VP9 encoding format can divide an image by any tile (tile), the tile height used when dividing an image determines the number of first buffer units required, For example, when a tile with a higher height is used to segment an image, more first cache units are required. For ease of understanding, as shown in Figure 3, both image a and image b are divided by tiles, the tile height in image a is 4 pixels, and the tile height in image b is 8 pixels.

When decoding the image a, the decoder decodes the data in each tile sequentially in the order of tile1 to tile12, and continues to decode the data in the next tile after all the data in one tile is decoded. When decoding each tile, the decoder decodes the data of each row of pixels in the tile in order from top to bottom, and when decoding the data of each row of pixels, reads the data in order from left to right for decoding .

As shown in Figure 3, when the decoder decodes image a, it decodes in the following order:

1) Decode the data in area 1 of the first line; the data volume in area 1 is equal to the preset unit data volume, and the data length obtained by the decoder after decoding the unit data volume is equal to the aforementioned unit processing length (hereafter processed in units The length is equal to 256bytes as an example), so the length of the decoded data in area 1 is equal to 256bytes, and the data can be directly input to the compression module for compression without being cached;

2) Decode the data of area 2 in the first row; the rightmost side of area 2 is the boundary of tile1, the data volume of area 2 is less than the unit data volume, the length of the decoded data in area 2 is less than 256 bytes, area 2 is The decoded data will be allocated an empty first cache unit (for example, the first cache unit a);

3) Decode the data in area 3 of the second line; the length of the decoded data in area 3 is equal to 256 bytes, and the data does not need to be cached;

4) Decode the data in area 4 of the second row. The length of the decoded data in area 4 is less than 256 bytes, and the decoded data in area 4 will be allocated an empty first cache unit (for example, the first cache unit b );

5) Decode the data in area 5 of the third row; the length of the decoded data in area 5 is equal to 256 bytes, and the data does not need to be cached;

6) Decode the data in area 6 of the third row. The length of the decoded data in area 6 is less than the unit processing length, and the decoded data in area 6 will be allocated an empty first buffer unit (for example, the first buffer unit c);

7) Decode the data in area 7 of the fourth line; the length of the decoded data in area 7 is equal to 256 bytes, and the data does not need to be cached;

8) Decode the data in area 8 of the fourth row. The length of the decoded data in area 8 is less than the unit processing length, and the decoded data in area 8 will be allocated an empty first buffer unit (for example, the first buffer unit d);

9) Decode the data in area 9 of the first row; the sum of the data volume in area 9 and the data volume in area 2 is equal to the preset unit data volume, and the decoded data in area 9 is stored in the first cache unit a The data belong to the same processing unit, and the total length of the two is equal to 256bytes, so the two are input as a processing unit to the compression module for compression, and then the validity flag of the first cache unit a is updated to 0, indicating that the first Cache unit a is empty at this time;

10) Decode the data in area 10 of the first row; the length of the decoded data in area 10 is equal to 256 bytes, and the data does not need to be cached;

11) Decode the data in area 11 of the first row; the length of the decoded data in area 11 is less than 256 bytes, and the decoded data in area 11 is stored in the new first cache unit a;

12) Decode the data in area 12 of the second row; the sum of the data volume in area 12 and the data volume in area 4 is equal to the preset unit data volume, and the decoded data in area 12 is stored in the first cache unit b The data belong to the same processing unit, and the total length of the two is equal to 256bytes, so the two are input as a processing unit to the compression module for compression, and then the validity flag of the first cache unit b is updated to 0, indicating that the first Cache unit b is now empty.

By analogy, the decoder completes the decoding of image a. It can be seen that when the decoder decodes the image a, in order to realize the adaptation between the decoder and the compression module, at least the first cache unit a, the first cache unit b, the first cache unit c, the first cache unit d, etc. 4 a first cache unit. In the same way, when the decoder decodes the image b, in order to realize the adaptation between the decoder and the compression module, at least 8 first buffer units are needed. It can be seen that the tile height used when dividing an image determines the number of required first cache units.

In addition, it needs to be added that the number of copies of data that each processing unit consists of mainly depends on the width of the tile. The smaller the width of the tile, the more copies of data each processing unit includes. For example, in image a in FIG. 3 , the decoded data in area 2 and the decoded data in area 9 constitute a processing unit, in other words, the processing unit consists of only two pieces of data. However, if the width of the tile in the image a is reduced so that a preset unit of data is truncated twice or more, the processing unit will consist of three or more pieces of data.

As mentioned above, since the tile height used when dividing an image determines the number of first buffer units required, and in the H.265 encoding format and VP9 encoding format, the size of the tile is arbitrary, so the height of the tile is very small. When the value is high, the required number of first cache units is large. In order to control the cost of the chip and/or reduce the occupation of the chip area by the first cache unit, usually only a limited number of first cache units are provided. Therefore, when the height of the tile is very high, the first cache unit may not be enough.

In order to deal with the situation that the first cache unit is not enough, in the present disclosure, the cache module is also used to: when there is no corresponding target data in the current data, and there is no empty first cache unit among the multiple first cache units, The current data is stored in a memory outside the cache module, and the status information of the processing unit corresponding to the current data is recorded. Wherein, the processing unit state information includes at least one of the following information: the address of the current data, the length of the current data, and the address of the current data in the memory.

In this disclosure, if the current data is the first piece of data in a processing unit, the caching module will search for an empty first caching unit from multiple first caching units, and if an empty first caching unit is found, cache The module allocates the found empty first cache unit to the current data. If all the first cache units are occupied (that is, there is no empty first cache unit), the cache module stores the current data in a memory outside the cache module (such as GDDR). In addition, the cache unit will also record the processing unit status information corresponding to the current data. The processing unit status information may include the first address of the current data, the length of the current data, and the address of the current data in GDDR. The processing unit status information may be stored in In the state cache unit shown in Figure 2.

In some specific implementation manners, the status information of the processing unit may also include an address range corresponding to the processing unit. For the calculation method of the address range, reference may be made to the above-mentioned embodiments. To simplify the description, details are not repeated here. When the cache module subsequently receives the new data output by the decoder, it can determine the processing unit to which the new data belongs and the corresponding target data according to the address interval in the state information of each processing unit.

In some specific implementation manners, the processing unit status information may further include storage indication information, and the storage indication information is used to indicate whether the data of the processing unit is stored in the cache module.

As mentioned above, the cache module is also used to store the current data when the total length of the current data and the target data corresponding to the current data is not equal to the unit processing length. In some specific implementations of the present disclosure, when the cache module stores the current data when the total length is not equal to the unit processing length, it is specifically used to: when the total length is not equal to the unit processing length, according to the corresponding The processing unit state information is to store the current data in the corresponding first cache unit, or store it in the memory; and update the processing unit state information corresponding to the current data.

In specific implementation, when the total length of the current data and the target data corresponding to the current data is not equal to the unit processing length, the cache module queries the processing unit status information corresponding to the current data, according to the storage indication information in the processing unit status information to determine whether the data of the processing unit is stored in the cache module or in the GDDR outside the cache module. If the data of the processing unit is stored in the cache module, the current data is further stored in the corresponding first cache unit according to the first cache unit identifier in the status information of the processing unit. If the data of the processing unit is stored in the GDDR outside the cache module, the current data is further stored in the corresponding location of the GDDR according to the memory address information in the status information of the processing unit.

In some specific implementation manners of the present disclosure, as shown in FIG. 2 , the cache module may further include a second cache unit. The cache module is also used to store the current data in the second cache unit when the total length is equal to the unit processing length and the target data corresponding to the current data is stored in the memory, and read the target data corresponding to the current data from the memory to Second cache unit.

In the present disclosure, if the total length of the current data output by the decoder and the corresponding target data is equal to the unit processing length, the current data and the corresponding target data may be output to the compression module as a processing unit. If the target data corresponding to the current data is stored in a first cache unit in the cache module at this time, the cache module can first store the current data in the first cache unit, and then store the data in the data segment of the first cache unit All data is input to the compression module as a processing unit for compression. And if the target data corresponding to the current data is stored in the GDDR outside the cache module at this time, the cache module can first store the current data to the second cache unit, and read the target data corresponding to the current data from the memory to the second cache unit. The cache unit, after splicing the current data and its target data, inputs the spliced data as a processing unit to the compression module for compression.

In the present disclosure, for the data of each processing unit stored in the memory (such as GDDR), by sharing the second cache unit, the cost of the chip can be effectively reduced, and the chip area occupied by the cache module can be reduced.

In some specific implementations of the present disclosure, before judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module, the cache module is further used to: judge whether the current data is a row of image data the last part.

Wherein, a row of image data refers to data corresponding to a row of pixels in the image. The last part of a row of image data refers to data corresponding to the last segment of pixels in a row of pixels. In the present disclosure, if a segment of pixels is continuous and includes the last pixel of a row of pixels, the segment of pixels is the last segment of pixels in a row of pixels. For example, a row of pixels includes pixel 1 to pixel 2560, wherein pixel 2560 is the last pixel. If a certain segment of pixels includes pixel N (1≤N≤2560) to pixel 2560, wherein pixel N to pixel 2560 are continuous, then this segment of pixels is the last segment of pixels in this row of pixels.

In the present disclosure, it may be determined whether the current data is the last part of the row of image data according to the address information of a row of image data and the address of the current data.

In some specific implementation manners, the number of pixels included in a row of images can be determined by reading the resolution information of the current image stored in the resolution register, and determined by reading the image format information of the current image stored in the image format register. The data amount of each pixel, and then determine the end address of a row of images according to the number of pixels of a row of images and the amount of data of each pixel. If the end address of the current data is equal to the end address of a certain line of image, it is determined that the current data is the last part of one line of data. It should be noted that this specific implementation is only one of many possible implementations of the present disclosure, and the present disclosure does not limit how to determine whether the current data is the last part of the row of image data.

The cache module is also used to calculate the total length of the current data and the target data corresponding to the current data when the current data is the last part of a line of image data, and when the total length is less than the unit processing length, process the current data Supplementing, so that the total length of the supplemented current data and target data is equal to the unit processing length, and then inputting the supplemented current data and target data as a processing unit to the compression module for compression.

In this disclosure, after obtaining the current data output by the decoder, the cache unit can judge whether the current data is the last part of a line of image data, and if so, further determine the target data corresponding to the current data, and calculate the current data and its target data If the total length is less than the unit processing length, calculate the length difference between the unit length and the total length, and fill the current data with zeros according to the length difference. For example, if the length difference is 5 bytes, then add 5 bytes at the end of the current data 0, so that the total length of the current data and its target data after 0 padding is equal to the unit processing length, and then the current data and its target data after 0 padding are input to the compression module as a processing unit for compression.

In addition, if the current data is not the last part of a line of image data, the cache module, as mentioned above, judges whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module. The data and the target data corresponding to the current data are input as a processing unit to the compression module for compression. If they are not equal, the cache module stores the current data.

In some specific implementations of the present disclosure, before judging whether the current data is the last part of a line of image data, the cache module is further configured to: judge whether the length of the current data is equal to the unit processing length. If the length of the current data is less than the unit processing length, the cache module judges whether the current data is the last part of a line of image data as described above. If the length of the current data is equal to the unit processing length, the cache module inputs the current data as a processing unit to the compression module for compression.

In addition, as shown in FIG. 1, the data processing system may further include a decoder and a compression module. Wherein, the decoder is used to decode the image data and output the decoded data. The compression module is used to compress the data input by the cache module. In some specific implementation manners, when the decoder decodes the image data, if the image data is image data divided by blocks, the decoder decodes the image data according to the order of the blocks.

Referring to FIG. 4 to FIG. 6 , FIG. 4 to FIG. 6 are schematic diagrams of a data processing flow proposed by an embodiment of the present disclosure. As shown in Figures 4 to 6, the data processing flow includes the following steps:

S1: Graphics processor The processor in the GPU reads the header file header of the video file (or image file) to determine that the current frame image is an image divided by tiles, and then the processor configures the registers through the AHB bus.

Wherein, the registers configured by the processor include a base address register, a resolution register and an image format register. The base address register is used to store the address of compressed data, the resolution register is used to store the resolution of the current frame image, and the image format register is used to store the image format of the current frame image (such as YUV format).

S2: The processor sets the enable register to start the video decoder.

S3: The video decoder sequentially decodes each part of the image data according to the order of the tiles, so as to sequentially output the decoded data of each part.

Wherein, the video decoder may output the decoded data to the cache module in the form of a burst based on the AXI protocol.

S4: The cache module obtains the current data output by the video decoder, and judges whether the length of the current data is equal to 256 bytes (in this example, the unit processing length of the compression module is set to 256 bytes); if yes, execute S5; if not, execute S6 .

S5: Input the current data to the compression module for compression.

S6: Determine whether the current data is the last part of a row of image data; if yes, execute S7; otherwise, execute S10.

S7: Determine the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder.

Wherein, the target data corresponding to the current data refers to data that has been output by the decoder and belongs to the same processing unit as the current data.

When determining the target data corresponding to the current data, the address of the current data can be compared with the address range corresponding to each processing unit; if the address of the current data is within the address range corresponding to a certain processing unit, the The data is the target data corresponding to the current data; if the address of the current data is not in the address range corresponding to any processing unit, then the current data does not have corresponding target data, which means that the current data is the first data of a processing unit, Furthermore, the address interval corresponding to the processing unit may also be determined according to the first address of the current data.

S8: If the target data is not determined (that is, there is no corresponding target data in the current data), add 0 at the end of the current data until the length of the current data is equal to 256 bytes, and then input the current data after filling in 0 to the compression module to compress.

S9: If the target data is determined, calculate the total length of the current data and the target data, and when the total length is equal to 256 bytes, input the current data and the target data as a processing unit to the compression module for compression; if the total length is less than 256 bytes In the case of 0, add 0 at the end of the current data until the total length of the current data and target data after 0 is equal to 256 bytes, and then input the current data and target data as a processing unit to the compression module for compression.

S10: Determine the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder.

Wherein, the target data corresponding to the current data refers to data that has been output by the decoder and belongs to the same processing unit as the current data.

When determining the target data corresponding to the current data, the address of the current data can be compared with the address range corresponding to each processing unit; if the address of the current data is within the address range corresponding to a certain processing unit, the The data is the target data corresponding to the current data, and at the same time, it indicates that the current data belongs to the processing unit; if the address of the current data is not in the address range corresponding to any processing unit, then the current data does not have corresponding target data, thus indicating that the current data is The first piece of data of a processing unit, and furthermore, the address range corresponding to the processing unit can be determined according to the first address of the current data.

S11: If the target data is not determined (that is, the current data does not have corresponding target data), then judge whether there is an empty first cache unit among the first cache units; if yes, execute step S12; if not, execute step S13.

Wherein, each first cache unit is located in the cache module.

S12: Allocate an empty first cache unit for the current data, and store the current data at the minimum address of the first cache unit.

In addition, the processing unit status information corresponding to the current data may also be recorded, and the validity flag of the corresponding first cache unit is updated to 1, indicating that the first cache unit is currently not empty. Among them, the processing unit status information corresponding to the current data may include the following information: the first address of the current data, the length of the current data, storage indication information (the storage indication information is used to indicate whether the data of the processing unit is stored in the cache module), as The identifier of the first cache unit allocated for the current data, and the address range corresponding to the processing unit.

S13: Store the current data in the GDDR memory outside the cache module, and record the status information of the processing unit corresponding to the current data.

Among them, the processing unit status information corresponding to the current data may include the following information: the first address of the current data, the length of the current data, storage indication information (the storage indication information is used to indicate whether the data of the processing unit is stored in the cache module), the current The address of the data in the GDDR memory, the address range corresponding to the processing unit.

S14: If the target data is determined, judge whether the total length of the current data and the target data is equal to 256 bytes; if yes, execute step S15; if not, execute step S18.

S15: According to the processing unit status information of the processing unit to which the current data belongs, determine whether the data of the processing unit is stored in the cache module; if yes, execute step S16; if not, execute step S17.

In this embodiment, by executing the above step S10, the processing unit to which the current data belongs has been determined. In S15, the storage indication information in the processing unit status information corresponding to the processing unit can be queried, so as to determine whether the data of the processing unit stored in the cache module.

S16: According to the first cache unit identifier in the processing unit status information, read the target data corresponding to the current data from the corresponding first cache unit, and input the current data and the target data as a processing unit to the compression module for compression.

Then, update the validity flag of the corresponding first cache unit to 0, indicating that the first cache unit is empty.

S17: Store the current data in the second cache unit, and read back the target data corresponding to the current data to the second cache unit from the corresponding address of the GDDR memory according to the GDDR memory address information in the processing unit status information, and then The current data and target data in the second cache unit are input to the compression module as a processing unit for compression.

Wherein, the second cache unit is located in the cache module. When reading back the target data corresponding to the current data from the GDDR memory, first obtain the storage location information of the current data in the second cache unit, and obtain the ID corresponding to the burst used to transmit the current data, and then shift the ID , and put the storage location information in the low bit of the ID to generate a unique RID; then when the cache module reads the target data from the GDDR memory based on the AXI protocol, it will send the RID to the GDDR memory, and when the GDDR memory returns the target data The RID will be carried; the cache module determines the position of the data to be spliced (that is, the current data) in the second cache unit according to the low bit of the RID carried by the target data, so as to splice the current data with the read-back target data, and finally Input the spliced data as a processing unit to the compression module for compression.

S18: According to the processing unit status information of the processing unit to which the current data belongs, determine whether the data of the processing unit is stored in the cache module; if yes, perform step S19; if not, perform step S20.

In this embodiment, by executing the above step S10, the processing unit to which the current data belongs has been determined. In S18, the storage indication information in the processing unit status information corresponding to the processing unit can be queried, so as to determine whether the data of the processing unit stored in the cache module.

S19: According to the first cache unit identifier in the processing unit state information, store the current data in the corresponding first cache unit, and update the corresponding processing unit state information.

Wherein, when updating the corresponding processing unit status information, information such as the first address and length of the current data may be added to the processing unit status information.

In addition, after the current data is stored in the first cache unit, if the current data and the data already stored in the first cache unit are continuous, the two can also be spliced, and then the data length in the processing unit status information can be updated.

S20: According to the GDDR memory address information in the processing unit state information, store the current data in the corresponding location of the GDDR memory, and update the corresponding processing unit state information.

Wherein, when updating the corresponding processing unit status information, information such as the first address and length of the current data may be added to the processing unit status information.

In addition, after the current data is stored in the GDDR memory, if the current data and the data already stored in the GDDR memory are continuous, the two can also be spliced, and then the data length in the processing unit status information can be updated.

An embodiment of the present disclosure further provides an electronic component, where the electronic component includes the data processing system described in any one of the foregoing embodiments. In some usage scenarios, the product form of the electronic component is embodied as a SoC chip, a graphics card or a CPU motherboard.

An embodiment of the present disclosure also provides an electronic device, which includes the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smartphone, tablet computer, VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server wait.

Referring to FIG. 7 , an embodiment of the present disclosure also provides a data processing method, which belongs to the same inventive concept as the aforementioned data processing system, so in order to avoid repetition, the following only briefly describes the data processing method, and related specific implementation methods , you can refer to the aforementioned introduction to the data processing system. As shown in Figure 7, the data processing method includes the following steps:

S710: Determine whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module; the target data corresponding to the current data refers to: it has been output by the decoder and belongs to the same A processing unit of data.

S720: When the total length is equal to the unit processing length, input the current data and the target data corresponding to the current data as a processing unit to the compression module for compression.

S730: When the total length is not equal to the unit processing length, store the current data.

In some specific implementation manners of the present disclosure, the method further includes: determining the target data corresponding to the current data according to the address of the current data and the address of the data output by the decoder.

In some specific implementations of the present disclosure, according to the address of the current data and the address of the data output by the decoder, determining the target data corresponding to the current data includes: combining the address of the current data with the respective address range of each processing unit Compare; the address range of each processing unit is determined according to the minimum first address of the processing unit and the unit processing length, the minimum first address of the processing unit refers to the smallest first address among the first addresses of each data in the processing unit; When the address of the current data is located in the address range of a processing unit, each data belonging to the processing unit is determined as the target data corresponding to the current data.

In some specific implementation manners of the present disclosure, the method further includes: in the case that the current data does not have corresponding target data, allocating an empty first cache unit for the current data from the plurality of first cache units, and The current data is stored in the empty first cache unit; each first cache unit is used to store data that has been output by the decoder and belongs to the same processing unit; record the processing unit status information corresponding to the current data; processing unit status information It includes at least one of the following information: the address of the current data, the length of the current data, and the identifier of the first cache unit allocated for the current data.

In some specific implementation manners of the present disclosure, the method further includes: when the current data does not have corresponding target data, and there is no empty first cache unit in the plurality of first cache units, storing the current data in An external memory, and record the processing unit state information corresponding to the current data; the processing unit state information includes at least one of the following information: the address of the current data, the length of the current data, and the address of the current data in the memory.

In some specific implementations of the present disclosure, when the total length is not equal to the unit processing length, storing the current data includes: when the total length is not equal to the unit processing length, according to the processing unit status information corresponding to the current data, storing the current data in the corresponding first cache unit, or storing in the memory; updating the state information of the processing unit corresponding to the current data.

In some specific implementations of the present disclosure, the method further includes: when the total length is equal to the unit processing length, and the target data corresponding to the current data is stored in the memory, storing the current data in the second cache unit, and from The memory reads target data corresponding to the current data to the second cache unit.

In some specific implementations of the present disclosure, before judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module, the method further includes: judging whether the current data is the last row of image data part.

The method also includes: in the case that the current data is the last part of a line of image data, calculating the total length of the current data and the target data corresponding to the current data, and in the case that the total length is less than the unit processing length, performing processing on the current data Supplementing, so that the total length of the supplemented current data and target data is equal to the unit processing length, and then inputting the supplemented current data and target data as a processing unit to the compression module for compression.

In some specific implementation manners of the present disclosure, judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module includes: when the current data is not the last part of a line of image data, judging Whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module.

In some specific implementations of the present disclosure, before judging whether the current data is the last part of a row of image data, the method further includes: judging whether the length of the current data is equal to the unit processing length; judging whether the current data is the last part of a row of image data The last part of includes: judging whether the current data is the last part of a line of image data when the length of the current data is less than the unit processing length.

The method also includes: when the length of the current data is equal to the unit processing length, inputting the current data as a processing unit to the compression module for compression.

While preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment and all changes and modifications which fall within the scope of the present disclosure.

It is obvious that those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies thereof, the present disclosure also intends to include these modifications and variations.

Claims (25)

1. A data processing system, the data processing system comprising a cache module:

the buffer module is used for judging whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module; the target data corresponding to the current data refers to: data which has been output by the decoder and which belongs to the same processing unit as the current data;

the buffer module is further configured to input, as a processing unit, the current data and target data corresponding to the current data to the compression module for compression when the total length is equal to the unit processing length;

the buffer module is further configured to store the current data if the total length is not equal to the unit processing length.

2. The data processing system of claim 1, the cache module further configured to determine target data corresponding to the current data based on an address of the current data and an address of data that has been output by a decoder.

3. The data processing system according to claim 2, wherein the buffer module is specifically configured to, when determining the target data corresponding to the current data according to the address of the current data and the address of the data that has been output by the decoder:

comparing the address of the current data with the respective address interval of each processing unit; the address interval of each processing unit is determined according to the minimum head address of the processing unit and the unit processing length, wherein the minimum head address of the processing unit refers to the minimum head address in the head address of each data in the processing unit;

and determining each data belonging to a processing unit as target data corresponding to the current data when the address of the current data is located in an address interval of the processing unit.

4. The data processing system according to claim 2, the buffer module comprising a plurality of first buffer units each for storing data which has been output by the decoder and belongs to the same processing unit;

the buffer module is further configured to allocate an empty first buffer unit to the current data and record processing unit state information corresponding to the current data when the current data does not have corresponding target data;

The processing unit status information includes at least one of the following: and the address of the current data, the length of the current data and the identification of the first cache unit allocated for the current data.

5. The data processing system according to claim 4, wherein the buffer module is further configured to store the current data to a memory outside the buffer module and record processing unit status information corresponding to the current data when the current data does not have corresponding target data and no empty first buffer unit exists in the plurality of first buffer units;

the processing unit status information includes at least one of the following: the address of the current data, the length of the current data, and the address of the current data in the memory.

6. The data processing system according to claim 5, wherein the buffer module is configured to store the current data when the total length is not equal to the unit processing length:

storing the current data to a corresponding first buffer unit or to the memory according to the processing unit state information corresponding to the current data when the total length is not equal to the unit processing length;

And updating the state information of the processing unit corresponding to the current data.

7. The data processing system of claim 5, the cache module further comprising a state cache unit to store processing unit state information.

8. The data processing system of claim 5, the cache module further comprising a second cache unit;

the buffer module is further configured to store the current data to the second buffer unit and read the target data corresponding to the current data from the memory to the second buffer unit when the total length is equal to the unit processing length and the target data corresponding to the current data is stored in the memory.

9. The data processing system according to claim 1, wherein the buffer module is further configured to, before determining whether a total length of the current data and the target data corresponding to the current data is equal to a unit processing length of the compression module: judging whether the current data is the last part of one line of image data;

the buffer module is further configured to calculate, when the current data is the last part of one line of image data, a total length of the current data and target data corresponding to the current data, and supplement the current data when the total length is smaller than the unit processing length, so that the total length of the supplemented current data and target data is equal to the unit processing length, and input the supplemented current data and target data as a processing unit to the compression module for compression.

10. The data processing system according to claim 9, wherein the buffer module is specifically configured to, when determining whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module:

and judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module or not under the condition that the current data is not the last part of one line of image data.

11. The data processing system of claim 9, the caching module, prior to determining whether the current data is the last portion of a line of image data, further to: judging whether the length of the current data is equal to the unit processing length;

the buffer module is specifically configured to, when determining whether the current data is the last part of a line of image data: judging whether the current data is the last part of one line of image data or not in the case that the length of the current data is smaller than the unit processing length;

the buffer module is further configured to input the current data as a processing unit to the compression module for compression when the length of the current data is equal to the unit processing length.

12. The data processing system of claim 1, further comprising the decoder and the compression module;

the decoder is used for decoding the image data and outputting the decoded data;

the compression module is used for compressing the data input by the cache module.

13. The data processing system of claim 1, the decoder, when decoding image data, being specifically configured to:

in the case where the image data is image data divided by tiles, the image data is decoded in a tile order.

14. An electronic assembly comprising the data processing system of any one of claims 1 to 13.

15. An electronic device comprising the electronic assembly of claim 14.

16. A method of data processing, the method comprising:

judging whether the total length of the current data output by the decoder and the target data corresponding to the current data is equal to the unit processing length of the compression module or not; the target data corresponding to the current data refers to: data which has been output by the decoder and which belongs to the same processing unit as the current data;

when the total length is equal to the unit processing length, inputting the current data and target data corresponding to the current data as a processing unit to the compression module for compression;

And storing the current data in the case that the total length is not equal to the unit processing length.

17. The data processing method of claim 16, the method further comprising:

and determining target data corresponding to the current data according to the address of the current data and the address of the data which is output by the decoder.

18. The data processing method of claim 17, wherein the determining the target data corresponding to the current data according to the address of the current data and the address of the data that has been output by the decoder, comprises:

comparing the address of the current data with the respective address interval of each processing unit; the address interval of each processing unit is determined according to the minimum head address of the processing unit and the unit processing length, wherein the minimum head address of the processing unit refers to the minimum head address in the head address of each data in the processing unit;

and determining each data belonging to a processing unit as target data corresponding to the current data when the address of the current data is located in an address interval of the processing unit.

19. The data processing method of claim 17, the method further comprising:

Under the condition that the current data does not have corresponding target data, an empty first cache unit is allocated for the current data from a plurality of first cache units, and the current data is stored in the empty first cache unit; each first buffer unit is used for storing data which is output by the decoder and belongs to the same processing unit;

recording the state information of the processing unit corresponding to the current data; the processing unit status information includes at least one of the following: and the address of the current data, the length of the current data and the identification of the first cache unit allocated for the current data.

20. The data processing method of claim 19, the method further comprising:

storing the current data to an external memory and recording processing unit state information corresponding to the current data under the condition that the corresponding target data does not exist in the current data and an empty first cache unit does not exist in the plurality of first cache units;

the processing unit status information includes at least one of the following: the address of the current data, the length of the current data, and the address of the current data in the memory.

21. The data processing method according to claim 20, wherein the storing the current data in the case where the total length is not equal to the unit processing length, comprises:

storing the current data to a corresponding first buffer unit or to the memory according to the processing unit state information corresponding to the current data when the total length is not equal to the unit processing length;

and updating the state information of the processing unit corresponding to the current data.

22. The data processing method of claim 20, the method further comprising:

and storing the current data into a second cache unit and reading the target data corresponding to the current data from the memory into the second cache unit under the condition that the total length is equal to the unit processing length and the target data corresponding to the current data is stored in the memory.

23. The data processing method according to claim 16, before determining whether or not a total length of the current data and target data corresponding to the current data is equal to a unit processing length of a compression module, the method further comprising: judging whether the current data is the last part of one line of image data;

The method further comprises the steps of: and when the current data is the last part of one line of image data, calculating the total length of the current data and the target data corresponding to the current data, supplementing the current data so that the total length of the supplemented current data and the target data is equal to the unit processing length when the total length is smaller than the unit processing length, and inputting the supplemented current data and the target data into the compression module as a processing unit for compression.

24. The data processing method according to claim 23, wherein the determining whether the total length of the current data and the target data corresponding to the current data is equal to a unit processing length of a compression module includes:

and judging whether the total length of the current data and the target data corresponding to the current data is equal to the unit processing length of the compression module or not under the condition that the current data is not the last part of one line of image data.

25. The data processing method of claim 23, before determining whether the current data is the last portion of a line of image data, the method further comprising: judging whether the length of the current data is equal to the unit processing length;

The determining whether the current data is the last part of a line of image data includes: judging whether the current data is the last part of one line of image data or not in the case that the length of the current data is smaller than the unit processing length;

the method further comprises the steps of: and under the condition that the length of the current data is equal to the unit processing length, inputting the current data into the compression module as one processing unit for compression.

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