CN116166434A - Processor allocation method and system, device, storage medium and electronic equipment - Google Patents

Abstract

The embodiment of the present application provides a processor allocation method, system, device, storage medium, and electronic equipment. The method includes: determining N hosts included in the target server; receiving computing power resources requested by the N hosts, wherein the computing Power resources are used to represent resources that process the data of N hosts; assign M processors that match computing power resources to N hosts based on the numbers of N hosts, where M processors are used to process data of N hosts, The M processors and the N hosts are connected through a switch chip, and the switch chip is used to expand a bus connected to the processors. Through the present application, the problem of low utilization rate of processors in the related art is solved, and the effect of improving the utilization rate of processors is achieved.

Description

Processor allocation method and system, device, storage medium, electronic equipment

technical field

The embodiments of the present application relate to the computer field, and in particular, relate to a processor allocation method, system, device, storage medium, and electronic equipment.

Background technique

At present, artificial intelligence has penetrated into all walks of life through the integration of data, computing power, algorithms and scenarios, promoting and empowering digital intelligence transformation. Among them, the powerful computing power improves the processing capabilities of complex data such as images and voices, thereby changing the traditional human or human-computer interaction methods, and enabling new interaction methods to be quickly applied.

At this stage, the heterogeneous computing combination of a central processing unit (Central Processing ing Unit, referred to as CPU) and a graphics processing unit (Graph i cs Processing ing Unit, referred to as GPU) is still the most powerful computing power of artificial intelligence. preferred. In practice, many enterprise artificial intelligence (Artificial Intelligence (AI) systems for short) call GPUs directly through physical forms, and GPUs do not implement resource pooling like computing, storage, and network virtualization in cloud scenarios. Therefore, the utilization rate of the GPU is extremely low, resulting in limited elastic expansion capability, and the input-output ratio is not directly proportional.

In addition, the status of CPU and GPU is quite different, one is a necessity and the other is an accelerator. The CPU is running all the time, and the GPU, as a device attached to the computer, is only called when needed. Therefore, the key to efficient use of GPU resources is to call them on demand and release them when they are used up, regardless of whether the GPU resources are enough or where they come from.

At present, most server GPU cards are mounted inside the server chassis and can only serve a single server. Most methods to realize GPU resource pooling adopt the method of dividing a single physical GPU into multiple virtual GPUs according to a fixed ratio, such as 1/2 or 1/4, each virtual GPU has equal video memory, and computing power is polled. For example, in 2021, Nvidia provides MIG technology on some Ampere series GPUs, which can divide the A100 model GPU into up to 7 parts.

The GPU cards of traditional servers are basically integrated in the server. When the server is turned on, all the GPUs in the chassis will be powered on. When the computing demand is not very large, the spare GPUs in the chassis will also be powered on. It is impossible to dynamically adjust GPU resources according to actual needs, resulting in unnecessary waste of resources and unnecessary increase in power consumption.

Contents of the invention

Embodiments of the present application provide a processor allocation method, system, device, storage medium, and electronic equipment, so as to at least solve the problem of low processor utilization in the related art.

According to an embodiment of the present application, a processor allocation method is provided, including: determining N hosts included in the target server, wherein each host corresponds to a host number, and N is a natural number greater than or equal to 1; Receive the computing power resources requested by the N above-mentioned hosts, wherein the above-mentioned computing power resources are used to represent the resources for processing the data of the N above-mentioned hosts; based on the numbers of the N above-mentioned hosts, assign the N above-mentioned hosts matching the above-mentioned computing power resources M processors, wherein the M processors are used to process the data of the N hosts, and the M processors and the N hosts are connected through a switch chip, and the switch chip is used to expand the bus connected to the processors , the above M is a natural number greater than or equal to 1.

According to another embodiment of the present application, a processor allocation system is provided, including: a target server, N hosts are set in the target server, wherein each of the hosts corresponds to a host number, and the above N is greater than or equal to A natural number of 1; a switch chip, the above-mentioned switch chip is connected to N above-mentioned hosts, and connected to M processors, for expanding the bus connected to the above-mentioned processors, wherein, the above-mentioned M is a natural number greater than or equal to 1, and the above-mentioned M The processor is used to process data of the N hosts.

In an exemplary embodiment, the above-mentioned switch chip includes: a complex programmable logic device CPLD, which is connected to the management controller BMC in each of the above-mentioned hosts through a transmission bus, and is used to receive the computing power resources requested by the above-mentioned host through the above-mentioned BMC, And based on the numbers of the N hosts, allocate M processors matching the computing power resources to the N hosts, where the computing power resources are used to represent resources for processing data of the N hosts.

In an exemplary embodiment, the above-mentioned host includes: a signal transceiver, connected to the above-mentioned CPLD, for transmitting the low-level signal of the above-mentioned host to the above-mentioned CPLD, wherein the above-mentioned low-level signal is used to indicate that the above-mentioned host accesses the above target server.

In an exemplary embodiment, the above-mentioned processor allocation system further includes: a power supply chip, connected to the CPLD in the above-mentioned switch chip, and connected to the above-mentioned processor, for controlling the power supply of the above-mentioned processor.

According to yet another embodiment of the present application, there is also provided a processor allocation device, including: a first determining module, configured to determine N hosts included in the target server, wherein each of the above-mentioned hosts corresponds to a host number, and the above-mentioned N is a natural number greater than or equal to 1; the first receiving module is configured to receive computing power resources requested by N above-mentioned hosts, wherein the above-mentioned computing power resources are used to represent resources for processing data of N above-mentioned hosts; the first allocation module , for allocating M processors matching the above-mentioned computing resources to the N above-mentioned hosts based on the numbers of the N above-mentioned hosts, wherein, the M above-mentioned processors are used to process the data of the N above-mentioned hosts, and the M above-mentioned processors and The N above-mentioned hosts are connected through a switch chip, and the above-mentioned switch chip is used to expand the bus connected to the above-mentioned processor, and the above-mentioned M is a natural number greater than or equal to 1.

In an exemplary embodiment, the above-mentioned first determining module includes: a first determining unit, configured to determine that the above-mentioned target server is connected to the above-mentioned host when a low-level signal is detected by the complex programmable logic device CPLD , wherein, the above-mentioned CPLD is arranged in the above-mentioned switch chip, and is connected with the signal transceiver in the above-mentioned host computer, and the above-mentioned signal transceiver is used to transmit the above-mentioned low-level signal to the above-mentioned CPLD; the second determining unit is used for detecting the above-mentioned The number of low-level signals determines the number of the hosts, and N hosts are determined, wherein one host corresponds to one low-level signal.

In an exemplary embodiment, the above-mentioned apparatus further includes: a first processing module, configured to determine the number of the above-mentioned hosts based on the detected number of the above-mentioned low-level signals, and after determining N of the above-mentioned hosts, through the above-mentioned CPLD, each The hosts are numbered to obtain N host numbers; the first storage module is used to store the N host numbers in registers, wherein the registers are set in the CPLD; the first sending module is used to pass the transmission bus. Each host number is sent to the corresponding management controller BMC in the host, wherein the transmission bus connects the host and the CPLD.

In an exemplary embodiment, the above-mentioned first receiving module includes: a first receiving unit, configured to receive the computing resources required by each of the above-mentioned hosts sent by the BMC in each of the above-mentioned hosts, and obtain the computing resources of the N above-mentioned hosts. manpower resources.

In an exemplary embodiment, the above-mentioned first allocation module includes: a first sending unit, configured to send a power-on instruction to the target processor when the target computing power resource requested by the target host is greater than a first preset threshold , to control the power-on of the target processor, wherein the target host is any one of the N hosts, and the target processor is a processor among the M processors that matches the target computing resource; the first The establishment unit is configured to establish a connection between the above-mentioned target processor and the above-mentioned target host based on the target number of the above-mentioned target host, so as to call the above-mentioned target processor to process the data sent by the above-mentioned target host.

In an exemplary embodiment, the above-mentioned device further includes: a second sending module, configured to connect the above-mentioned target processor and the above-mentioned target host based on the target number of the above-mentioned target host, when the target computing power resource requested by the target host is less than the above-mentioned first In the case of a preset threshold, send a power-off instruction to the target processor to control the power-off of the target processor; the first disconnection module is used to disconnect the target processor and the target based on the target number of the target host connection between hosts.

In an exemplary embodiment, the above-mentioned apparatus further includes: a third sending module, configured to send a reset to the above-mentioned target processor after the connection between the above-mentioned target processor and the above-mentioned target host is disconnected based on the target number of the above-mentioned target host signal to reset the bus for the expansion connection between the aforementioned target processor and the aforementioned switch.

In an exemplary embodiment, each of the above-mentioned processors is correspondingly connected to a power supply chip, wherein the above-mentioned power supply chip is used to control the power supply of the above-mentioned processor.

According to yet another embodiment of the present application, a computer-readable storage medium is also provided, and a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to perform any one of the above-mentioned methods when running Steps in the examples.

According to yet another embodiment of the present application, there is also provided an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above Steps in the method examples.

Through this application, M processors are allocated according to the computing power resources requested by N hosts in the target server, and the computing power resources of the processors are dynamically managed, so that the connected hosts can perform the computing power of the processors according to actual needs. scheduling. It can effectively improve the utilization rate of the processor, improve the utilization rate of the computing resources of the processor, and reduce the overall power consumption of the system. Therefore, the problem of low utilization rate of the processor in the related art can be solved, and the effect of improving the utilization rate of the processor can be achieved.

Description of drawings

FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a processor allocation method according to an embodiment of the present application;

FIG. 2 is a flowchart of a processor allocation method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a GPU PCI E link according to an embodiment of the present application;

Fig. 4 is the connection topological diagram of the PCIe Switch chip according to the embodiment of the application;

FIG. 5 is a schematic diagram of identifying multiple hosts according to an embodiment of the present application;

FIG. 6 is a schematic diagram of GPU power supply and reset according to an embodiment of the present application;

7 is a schematic diagram of a processor allocation system according to an embodiment of the present application;

Fig. 8 is a structural block diagram of a processor allocation device according to an embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

It should be noted that the terms "first" and "second" in the description and claims of the present application and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence.

At first, the relevant technologies involved in the present invention are described:

BMC: Baseboard Management Control l l er, used for server motherboard management.

CPU: Central Process ing Unit it, central processing unit.

I2C: Inter-Integrated Circuit, that is, I 2C, a bus structure.

CPLD: Comp l ex Programmab l e Logic Device, complex programmable logic device.

GPU: Graph i cs Process ing Unit it, graphics processor.

CDFP: 400Gbps Form-factor P luggab l e, a pluggable transceiver module supporting 400Gbps rate.

BMC: Baseboard Management Control l l er, used for server motherboard management.

CPU: Central Process ing Unit it, central processing unit.

I2C: Inter-Integrated Circuit, that is, I 2C, a bus structure.

CPLD: Comp l ex Programmab l e Log i c Device, complex programmable logic device.

GPU: Graph i cs Process ing Unit it, graphics processor.

CDFP: 400Gbps Form-factor P luggab l e, a pluggable transceiver module supporting 400Gbps rate.

PCI E: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

The method embodiments provided in the embodiments of the present application may be executed in mobile terminals, computer terminals or similar computing devices. Taking running on a mobile terminal as an example, FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a method for allocating processors according to an embodiment of the present application. As shown in Figure 1, the mobile terminal may include one or more (only one is shown in Figure 1) processors 102 (processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc.) and a memory 104 for storing data, wherein the above-mentioned mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. Those skilled in the art can understand that the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG. 1 , or have a different configuration from that shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the processor allocation method in the embodiment of the present application, and the processor 102 runs the computer program stored in the memory 104 to execute Various functional applications and data processing are to realize the above-mentioned method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Transmission device 106 is used to receive or transmit data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

A processor allocation method is provided in this embodiment. FIG. 2 is a flowchart of a processor allocation method according to an embodiment of the present application. As shown in FIG. 2 , the process includes the following steps:

Step S202, determining N hosts included in the target server, wherein each host corresponds to a host number, and N is a natural number greater than or equal to 1;

Step S204, receiving computing power resources requested by N hosts, where computing power resources are used to represent resources for processing data of N hosts;

Step S206, allocate M processors matching the computing power resources to the N hosts based on the numbers of the N hosts, where the M processors are used to process the data of the N hosts, and the M processors and the N hosts pass through The switch chip is connected, and the switch chip is used to expand the bus connected to the processor, and M is a natural number greater than or equal to 1.

In this embodiment, the values of N and M can be flexibly set based on actual scenarios. For example, the target server includes 2 hosts, and 2 or 3 processors are required to process data. The processor may be a GPU or other processors, which is not limited here.

In this embodiment, the computing resource is the processing resource required by the data in the host. For example, two GPUs are required for image processing to transmit a recorded video in the host.

In this embodiment, the switch chip may include multiple switches. For example, two switch chips PCIe Switch are set in the processor box GPU BOX, and multiple GPU card slots are set to access multiple GPU cards. The host computer and the GPU BOX are connected through a CDFP connector and related cables. The CDFP connector is a 400Gbps pluggable I/O component suitable for high-speed applications such as data centers, high-performance computing, and storage and networking equipment.

Optionally, as shown in FIG. 3 , multiple PCIe Switch chips can be set in the GPU BOX. The hosts Host1 and Host2 each send out a PCI E x16 high-speed signal, which is connected to each PC I E Switch chip on the GPU BOX, and the downlink port of each PCI E Switch chip is respectively connected to two GPU cards. It should be noted that the number of connected GPU cards is determined according to the number of ports supported by the PCI E Switch chip. When the number of PCIe channels provided by the CPU is insufficient, the number of PCIe channels in the system can be expanded through the PCIe Switch chip. Although PCI e Gen5 has increased the signal rate to 32GT/s, GPU cards, AI accelerator cards, and new-generation network cards still require large data transmission bandwidth. Through the expansion of the PCI eSwitch chip, more function expansion cards can be accommodated on the whole server.

Optionally, the connection topology of the PCIe Switch chip is as shown in FIG. 4, the solid line represents the PCIE connection relationship of Host1, and the dotted line represents the PCIE connection relationship of Host2. As can be seen from Figure 4, when the target server includes two Hosts, any PCIE X16 from any Host can be connected to any GPU card through the PCIE Switch chip, so that each GPU can be connected by the connected PC. Enter the purpose of Host access. Among them, the H port in the PCIE Switch chip is used to indicate the uplink connection to the Host host, the F is used to indicate the PCIE cascade port of two PCIE Switch chips, and the D port is used to indicate the downlink port, which is used to connect to the GPU card.

Wherein, the executor of the above steps may be a terminal, a server, a specific processor set in the terminal or server, or a processor or processing device set relatively independently from the terminal or server, but is not limited thereto.

Through the above steps, M processors are allocated according to the computing power resources requested by the N hosts in the target server, and the computing power resources of the processors are dynamically managed, so that the connected hosts can perform the computing power of the processors according to actual needs. scheduling. It can effectively improve the utilization rate of the processor, improve the utilization rate of the computing resources of the processor, and reduce the overall power consumption of the system. Therefore, the problem of low utilization rate of the processor in the related art can be solved, and the effect of improving the utilization rate of the processor can be achieved.

In an exemplary embodiment, determining the N hosts included in the target server includes: in the case that a low-level signal is detected by the complex programmable logic device CPLD, determining the access host in the target server, wherein the CPLD is set to In the switch chip and connected with the signal transceiver in the host, the signal transceiver is used to transmit low-level signals to the CPLD; determine the number of hosts based on the number of detected low-level signals, and determine N hosts, wherein one The host corresponds to a low level signal. The signal transceiver in the present embodiment can be CDFP, for example, as shown in Figure 5, includes n Host mainframes in the target server Server, the serial number of mainframe is respectively Host1-n, and the signal between Server and GPU BOX passes through CDFP1- ntransmission. The identification of the number of host hosts is mainly based on the HOST_PRESENT signal on the host host. The HOST_PRESENT signal is pulled down and grounded on each host host. It is connected to the CPLD of the GPU BOX through the CDFP connector. When entering, because the HOST_PRESENT is pulled down to ground, the CPLD of the GPU BOX will detect a low-level signal, thereby judging that the Host host is in place; when the CPLD detects n HOST_PRESENT low-level signals, it is considered that the current target server includes n Host host. In this embodiment, by identifying the number of currently connected Host hosts, the sharing of GPU computing resources can be accurately realized.

In an exemplary embodiment, the number of hosts is determined based on the number of detected low-level signals. After determining N hosts, the method further includes: numbering each host by CPLD to obtain N host numbers; N host numbers are stored in registers, wherein the registers are set in the CPLD; each host number is sent to the management controller BMC in the corresponding host through a transmission bus, wherein the transmission bus connects the host and the CPLD. In this embodiment, each Host in the target server needs to know the number of the host it is currently accessing, for example, the relative number of 1-n. In this embodiment, the serial number of the host is mainly transmitted through I2C signals. As shown in Figure 5, after the CPLD of the GPU BOX identifies the number of Hosts in the current system, it will number the Hosts and store the numbering information in the registers of the CPLD. For example, if there are 5 host hosts in the current system, the number is 1-5, and the transmission of the number information is realized through the I2C signal that each host host is connected to the CPLD through the CDFP connector. The host host can read the register data of the CPLD through the I2C signal to obtain its current host number information. At the same time, the CPLD and BMC on the GPU BOX also reserve an I2C signal to pass the host number information to the BMC of the GPU BOX, so that the GPU BOX can monitor the number of hosts and optimize the power-on strategy of the GPU card when there are multiple hosts. In this embodiment, by setting the number of the host, the computing resources required by the host can be allocated accurately.

In an exemplary embodiment, receiving the computing power resources requested by the N hosts includes: receiving the computing power resources required by each host sent by the BMC in each host, and obtaining the computing power resources of the N hosts. In this embodiment, by determining the computing resources required by each host, processors can be accurately assigned to the host.

In an exemplary embodiment, allocating M processors matching the computing resources to the N hosts based on the numbers of the N hosts includes: when the target computing resource requested by the target host is greater than a first preset threshold , to send a power-on instruction to the target processor to control the power-on of the target processor, wherein the target host is any one of the N hosts, and the target processor is a processor among the M processors that matches the target computing resources ; Establish a connection between the target processor and the target host based on the target number of the target host to call the target processor to process the data sent by the target host. In this embodiment, the first preset threshold can be set based on the actual usage scenario. For example, if it is necessary to identify a portrait in a video stored for one month, two GPUs are required for processing. At this time, two target processors need to be controlled Power-on. Connect two GPUs to the host machine according to the number of the host machine to process video data. In this embodiment, the resource allocation processor can be used to effectively schedule resources and increase the rationality of resource utilization.

In an exemplary embodiment, after the target processor and the target host are connected based on the target number of the target host, the method further includes: when the target computing resource requested by the target host is less than a first preset threshold, sending the target processor A power-off command is sent to control the power-off of the target processor; the connection between the target processor and the target host is disconnected based on the target number of the target host. In this embodiment, after the data processing of the host is completed, the processor needs to be released in time, and the processor is controlled to be powered off, so as to save energy consumption.

In an exemplary embodiment, after the connection between the target processor and the target host is disconnected based on the target number of the target host, the method further includes: sending a reset signal to the target processor to reset the extension between the target processor and the switch. connected bus. In this embodiment, in order to realize GPU pooling, the power supply of each GPU card needs to be controlled separately, and each processor needs to be connected to a power supply chip, so that each GPU card can be independently downloaded in idle time. It can be controlled and powered on in time when it is powered on or needs to be connected. As shown in Figure 6, one I2C signal is connected between each Host in the Server and the CPLD of the GPU BOX, which mainly transmits the information that the current Host needs to request or release GPU resources, and transmits it to the CPLD of the GPU BOX, and the CPLD transmits the information Analyze and identify which GPU card needs to be powered on or off, realize the dynamic release and call of the GPU card, and maximize the use of GPU card computing resources. At the same time, the reset signal PERST of the PCIE of the GPU card is also given from the CPLD. Its source is consistent with the enable signal of the power chip, and is obtained from the Host through the I2C signal to reset the PCIE of the GPU card. In this embodiment, by setting a separate power supply chip for each processor, the flexible call and release of the processor can be realized.

In this embodiment, a processor allocation system is provided. FIG. 7 is a schematic diagram of a processor allocation system according to an embodiment of the present application. As shown in FIG. 7, the system includes:

A target server, where N hosts are set in the target server, where each host corresponds to a host number, and N is a natural number greater than or equal to 1;

A switch chip, the switch chip is connected to N hosts and M processors to expand the bus connecting the processors, where M is a natural number greater than or equal to 1, and the M processors are used to process the data of the N hosts .

In this embodiment, the computing resource is the processing resource required by the data in the host. For example, two GPUs are required for image processing to transmit a recorded video in the host.

In this embodiment, the switch chip may include multiple, for example, two switch chips PCIe Switch are set in the processor box GPU BOX, and multiple GPU card slots are set to access multiple GPU cards. The host computer and the GPU BOX are connected through a CDFP connector and related cables. The CDFP connector is a 400Gbps pluggable I/O component suitable for high-speed applications such as data centers, high-performance computing, and storage and networking equipment.

Optionally, as shown in FIG. 3 , multiple PCIe Switch chips can be set in the GPU BOX. The hosts Host1 and Host2 each send out a PCI E x16 high-speed signal, which is connected to each PC I E Switch chip on the GPU BOX, and the downlink port of each PCI E Switch chip is respectively connected to two GPU cards. It should be noted that the number of connected GPU cards is determined according to the number of ports supported by the PCI E Switch chip. When the number of PCIe channels provided by the CPU is insufficient, the number of PCIe channels in the system can be expanded through the PCIe Switch chip. Although PCI e Gen5 has increased the signal rate to 32GT/s, GPU cards, AI accelerator cards, and new-generation network cards still require large data transmission bandwidth. Through the expansion of the PCI eSwitch chip, more function expansion cards can be accommodated on the whole server.

Optionally, the connection topology of the PCIe Switch chip is as shown in FIG. 4, the solid line represents the PCIE connection relationship of Host1, and the dotted line represents the PCIE connection relationship of Host2. As can be seen from Figure 4, when the target server includes two Hosts, any PCIE X16 from any Host can be connected to any GPU card through the PCIE Switch chip, so that each GPU can be connected by the connected PC. Enter the purpose of Host access. Among them, the H port in the PCIE Switch chip is used to indicate the uplink connection to the Host host, the F is used to indicate the PCIE cascade port of two PCIE Switch chips, and the D port is used to indicate the downlink port, which is used to connect to the GPU card.

In an exemplary embodiment, as shown in FIG. 4, the switch chip includes: a complex programmable logic device CPLD, which is connected to the management controller BMC in each host through a transmission bus, and is used to receive the computing power requested by the host through the BMC. resources, and assign M processors that match the computing power resources to the N hosts based on the numbers of the N hosts, where the computing power resource is used to represent the resources that process the data of the N hosts.

In an exemplary embodiment, the host includes: a signal transceiver connected to the CPLD for transmitting a low-level signal of the host to the CPLD, wherein the low-level signal is used to indicate that the host has accessed the target server.

In an exemplary embodiment, the processor distribution system further includes: a power supply chip, connected to the CPLD in the switch chip, and connected to the processor, for controlling the power supply of the processor.

The present invention is described below in conjunction with specific embodiment:

This embodiment takes the control of the GPU as an example for illustration, and mainly includes the following contents:

1. Configure the PCIe link of the GPU. The PCI E link of the GPU takes the GPU pooling of the dual-host Host as an example. As shown in Figure 3, Host1 and Host2 are the hosts of the two servers respectively, and the host and the GPU BOX are connected through CDFP connectors 1 and 2 and related lines. cable to connect. The hosts Host1 and Host2 each output a PCI E x16 high-speed signal, which is connected to the PCI E Switch chip on the GPU BOX. Each PCI E Switch downlink port is connected to two GPU cards respectively. The number of GPU cards connected in actual applications is based on It depends on the number of ports supported by the PCI E Switch. When the number of PCIe channels provided by the CPU is insufficient, the PCIe Switch chip can be used to expand the number of PCIe channels in the system. Through the expansion of the PCIe Switch chip, more function expansion cards can be accommodated on the whole server.

2. Set the connection topology of PCI E. As shown in FIG. 4 , the PCI E connection relationship of Host1 and the PCI E connection relationship of Host2 are marked. Any PCI E X16 from the Host can be connected to any GPU card in the system through the PCI E Switch, so that each GPU can be accessed by the connected Host.

3. Set up a separate power chip for each GPU. As shown in Figure 6, setting a separate power chip for each GPU can realize that each GPU card can be powered off independently during idle time or can be powered on in a timely and controlled manner when it needs to be connected.

To sum up, in this embodiment, the connection of each Host to the GPU provides a high-speed connection path for GPU pooling; through the identification of the number of Hosts in the system and the power supply design and reset design of the GPU, the separate up and down of the GPU can be realized. electric control. Through the GPU pooling design, the utilization rate of the GPU in the system can be effectively improved, and the utilization rate of GPU computing power resources can be improved. When the demand for computing power is low, some GPU resources can be released, the overall power consumption of the system can be reduced, and unnecessary waste of electricity, so as to achieve the purpose of reducing costs.

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, disk, CD) contains several instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

In this embodiment, a device for allocating processors is also provided, which is used to implement the above embodiments and preferred implementation modes, and those that have been explained will not be repeated here. As used below, the term "module" may be a combination of software and/or hardware that realizes a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

Fig. 8 is a structural block diagram of a processor allocation device according to an embodiment of the present application. As shown in Fig. 8, the device includes:

The first determining module 82 is configured to determine N hosts included in the target server, wherein each of the above-mentioned hosts corresponds to a host number, and the above-mentioned N is a natural number greater than or equal to 1;

The first receiving module 84 is configured to receive computing power resources requested by the N hosts above, where the computing power resources are used to represent resources for processing data of the N hosts mentioned above;

The first allocation module 86 is configured to allocate M processors matching the above-mentioned computing power resources to the N above-mentioned hosts based on the numbers of the N above-mentioned hosts, wherein the M above-mentioned processors are used to process the data of the N above-mentioned hosts, and M The above-mentioned processors and the N above-mentioned hosts are connected through a switch chip, and the above-mentioned switch chip is used to expand the bus connecting the above-mentioned processors, and the above-mentioned M is a natural number greater than or equal to 1.

In an exemplary embodiment, the above-mentioned first determination module 82 includes:

The first determination unit is configured to determine that the host is connected to the target server when a low-level signal is detected by the complex programmable logic device CPLD, wherein the CPLD is arranged in the switch chip and communicates with the host The signal transceiver in the above-mentioned signal transceiver is used to transmit the above-mentioned low-level signal to the above-mentioned CPLD;

The second determination unit is configured to determine the number of the hosts based on the number of detected low-level signals, and determine N hosts, wherein one host corresponds to one low-level signal.

In an exemplary embodiment, the above-mentioned device also includes:

The first processing module is used to determine the number of the above-mentioned hosts based on the number of detected low-level signals, and after determining the N above-mentioned hosts, number each of the above-mentioned hosts through the above-mentioned CPLD to obtain N host numbers;

The first storage module is used to store the N numbers of the above-mentioned hosts in registers, wherein the above-mentioned registers are set in the above-mentioned CPLD;

The first sending module is configured to send each host number to the corresponding management controller BMC in the host through a transmission bus, wherein the transmission bus connects the host and the CPLD.

In an exemplary embodiment, the above-mentioned first receiving module includes:

The first receiving unit is configured to receive the computing power resources required by each of the above-mentioned hosts sent by the BMC in each of the above-mentioned hosts, and obtain the computing power resources of the N above-mentioned hosts.

In an exemplary embodiment, the above-mentioned first distribution module includes:

The first sending unit is configured to send a power-on instruction to the target processor to control the power-on of the target processor when the target computing resource requested by the target host is greater than a first preset threshold, wherein the target host is Any one of the N above-mentioned hosts, the above-mentioned target processor is a processor among the M above-mentioned processors that matches the above-mentioned target computing resources;

The first establishing unit is configured to establish a connection between the above-mentioned target processor and the above-mentioned target host based on the target number of the above-mentioned target host, so as to call the above-mentioned target processor to process the data sent by the above-mentioned target host.

In an exemplary embodiment, the above-mentioned device also includes:

The second sending module is configured to, after connecting the target processor and the target host based on the target number of the target host, send the A power-off command to control the power-off of the above-mentioned target processor;

The first disconnection module is configured to disconnect the connection between the target processor and the target host based on the target number of the target host.

In an exemplary embodiment, the above-mentioned device also includes:

The third sending module is configured to send a reset signal to the target processor after disconnecting the connection between the target processor and the target host based on the target number of the target host to reset the connection between the target processor and the switch Extended connected bus.

In an exemplary embodiment, each of the above-mentioned processors is correspondingly connected to a power supply chip, wherein the above-mentioned power supply chip is used to control the power supply of the above-mentioned processor.

It should be noted that the above-mentioned modules can be realized by software or hardware. For the latter, it can be realized by the following methods, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned modules can be combined in any combination The forms of are located in different processors.

Embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is set to execute the steps in any one of the above method embodiments when running.

In an exemplary embodiment, the above-mentioned computer-readable storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM) ), mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.

An embodiment of the present application also provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

In an exemplary embodiment, the electronic device may further include a transmission device and an input and output device, wherein the transmission device is connected to the processor, and the input and output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and exemplary implementation manners, and details will not be repeated here in this embodiment.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned application can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices In fact, they can be implemented in program code executable by a computing device, and thus, they can be stored in a storage device to be executed by a computing device, and in some cases, can be executed in an order different from that shown here. Or described steps, or they are fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present application is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of this application shall be included within the scope of protection of this application.

Claims (15)

1. A processor allocation method, characterized in that, comprising: Determine N hosts included in the target server, where each host corresponds to a host number, and N is a natural number greater than or equal to 1; receiving computing power resources requested by N hosts, where the computing power resources represent resources for processing data of N hosts; Based on the numbers of the N hosts, allocate M processors matching the computing resources to the N hosts, wherein the M processors are used to process the data of the N hosts, and the M processors are used to process the data of the N hosts, and the M processors are used to process the data of the N hosts. The processor and the N hosts are connected through a switch chip, and the switch chip is used to expand the bus connecting the processors, and the M is a natural number greater than or equal to 1. 2. The method according to claim 1, wherein determining the N hosts included in the target server comprises: In the case that a low-level signal is detected by the complex programmable logic device CPLD, it is determined that the host is accessed in the target server, wherein the CPLD is arranged in the switch chip and communicates with the host in the host A signal transceiver is connected, and the signal transceiver is used to transmit the low-level signal to the CPLD; The number of the hosts is determined based on the number of detected low-level signals, and N hosts are determined, where one host corresponds to one low-level signal. 3. The method according to claim 2, wherein the number of the hosts is determined based on the number of detected low-level signals, and after determining N hosts, the method further comprises: Numbering each of the hosts through the CPLD to obtain N host numbers; storing N host numbers in registers, wherein the registers are set in the CPLD; Each host number is sent to the corresponding management controller BMC in the host through a transmission bus, wherein the transmission bus connects the host and the CPLD. 4. The method according to claim 1, wherein receiving the computing resources requested by N hosts comprises: receiving the computing power resources required by each of the hosts sent by the BMC in each of the hosts, and obtaining the computing power resources of the N hosts. 5. The method according to claim 1, wherein assigning M processors matching the computing power resources to the N hosts based on the numbers of the N hosts includes: When the target computing resource requested by the target host is greater than the first preset threshold, a power-on instruction is sent to the target processor to control the target processor to be powered on, wherein the target host is N hosts Any one of the hosts, the target processor is a processor among the M processors that matches the target computing resource; A connection between the target processor and the target host is established based on the target number of the target host, so as to invoke the target processor to process data sent by the target host. 6. The method according to claim 5, wherein after connecting the target processor and the target host based on the target number of the target host, the method further comprises: When the target computing resource requested by the target host is less than the first preset threshold, sending a power-off instruction to the target processor to control the target processor to be powered off; The connection between the target processor and the target host is disconnected based on the target number of the target host. 7. The method according to claim 6, wherein after disconnecting the connection between the target processor and the target host based on the target number of the target host, the method further comprises: sending a reset signal to the target processor to reset the bus of the expansion connection between the target processor and the switch. 8. The method according to any one of claims 1-7, characterized in that the method further comprises: Each of the processors is correspondingly connected to a power supply chip, wherein the power supply chip is used to control the power supply of the processor. 9. A processor allocation system, comprising: A target server, where N hosts are set in the target server, where each host corresponds to a host number, and N is a natural number greater than or equal to 1; A switch chip, the switch chip is connected to N hosts and M processors for expanding the bus connected to the processors, wherein the M is a natural number greater than or equal to 1, and the M processors The processor is configured to process data of N hosts. 10. The processor allocation system according to claim 9, wherein the switch chip comprises: The complex programmable logic device CPLD is connected to the management controller BMC in each of the hosts through the transmission bus, and is used to receive the computing resources requested by the host through the BMC, and based on the number of N hosts as The N hosts allocate M processors matching the computing power resources, where the computing power resources represent resources for processing data of the N hosts. 11. The processor allocation system according to claim 10, wherein the host computer comprises: A signal transceiver, connected to the CPLD, for transmitting the low-level signal of the host to the CPLD, wherein the low-level signal is used to indicate that the host has accessed the target server. 12. The processor allocation system according to claim 9, wherein the processor allocation system further comprises: The power supply chip is connected with the CPLD in the switch chip and connected with the processor, and is used to control the power supply of the processor. 13. A processor allocation device, comprising: The first determination module is configured to determine N hosts included in the target server, where each host corresponds to a host number, and N is a natural number greater than or equal to 1; The first receiving module is configured to receive computing power resources requested by N hosts, where the computing power resources represent resources for processing data of N hosts; A first allocating module, configured to allocate M processors matching the computing resources to the N hosts based on the numbers of the N hosts, wherein the M processors are used to process the N hosts The M processors and the N hosts are connected through a switch chip, and the switch chip is used to expand the bus connecting the processors, and the M is a natural number greater than or equal to 1. 14. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, any one of claims 1 to 8 is implemented. The steps of the method. 15. An electronic device comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the rights are realized when the processor executes the computer program The steps of the method described in any one of Claims 1 to 8.

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