CN116166186A - Cache controller based on dual-port Sram and working method - Google Patents

Abstract

The invention relates to a dual-port Sram-based Cache controller and a working method thereof. The Cache controller is composed of a dual-port Sram and related control circuits. The dual-port Sram is used to cache data in the memory, and the read port is used to match the reading of the processor. The transmission and write ports are used to load the read data of the bus, and the two sets of ports do not affect each other; the Cache controller can continue to match the read operation address of the processor while loading data from the memory, and can immediately feedback the data if it hits the Sram or Bus ; The width of the dual-port Sram in the Cache controller is 2 ⁿ multiples of the bus width. According to the Cache controller and the working method of the present invention, the processor can continue to access the hit data through the reading port of the dual-port Sram. Therefore, there is no mutual interference between the loading operation and the access hit data, and a certain logic area is exchanged for the efficiency of the entire system.

Description

A kind of Cache controller and working method based on dual-port SRAM

technical field

The invention relates to the field of controllers, in particular to a dual-port Sram-based Cache controller and a working method.

Background technique

In microcontrollers, the clock frequency of the processor is faster than that of the memory, and there is generally a gap of several to tens of times. In order to reduce the processor's waiting for reading data and improve system execution efficiency, a level of Cache can be added between the processor and the memory. Cache is a memory implemented based on SRAM. Its capacity is smaller than that of system memory but its speed is much higher, which can be the same as the frequency of the processor.

When the processor reads data, if the required data can be found in the Cache, we call it a hit (Hit). On the contrary, if no data is found, we call it missing (Miss). At this time, the controller needs to load a small piece of data (including but not limited to the data required for this transmission) from the external memory and store it in Sram for easy processing. The server can be accessed in time in the future.

For the existing Cache controller, after the processor obtains the data of the current access address, the Cache controller may be in the data loading stage. At this time, the port of Sram is occupied by the write operation, and the processor needs to wait until all the data is loaded. In order to continue the visit to the next address.

Contents of the invention

For solving the problems of the technologies described above, a kind of Cache controller based on dual-port Sram of the present invention, Cache controller is made up of dual-port Sram and relevant control circuit thereof, uses dual-port Sram to cache the data of storage memory, read port is used for matching processing The read and transfer of the device, the write port is used to load the read data of the bus, and the two sets of ports do not affect each other; the Cache controller can continue to match the read operation address of the processor while loading data from the memory. If it hits the Sram or Bus, it can Feedback data immediately; the width of the dual-port Sram in the Cache controller is 2 ⁿ multiples of the bus width, and each miss can load 2 ⁿ data from the memory; the Cache controller can match the data in the Sram, or can Match data on the bus being transmitted.

In one embodiment of the present invention, the Sram includes TagSram and DataSram, wherein TagSram is used to store flag bits, and V(x) uses 0 or 1 to indicate whether the data of a certain offset address in the cache is valid, The number of digits of V can be 2 ⁿ ; the value of T is taken from the high-order digits of the address, and the number of digits depends on the capacity of Sram, which can be used to match the future read address; DataSram is used to store data, and its width can be Bus width 2 ⁿ times of .

The present invention also provides the working method of Cache controller in addition, based on the Cache controller design of dual-port Sram described in claim 1-2, it is characterized in that: comprise the steps:

Step S1: The processor initiates a read transfer on the bus, the Cache controller receives the request, and jumps to step S7;

Step S2: The processor can directly read the data in Sram and jump to step S1 to perform the next read transfer;

Step S3: The processor can directly read the data on the Bus and jump to step S1 to perform the next read transfer;

Step S4: wait for the bus loading work to be completed and then jump to step S8;

Step S5: The current read data of the processor does not exist in the Cache controller, and the controller needs to load data from the memory; if there is currently a loading operation being executed, then jump to step S4, if not, then jump to step S8 ;

Step S6: The Cache controller matches the read address of the current processor and the read address being loaded by the current bus. If the two addresses are the same, the data hits and jumps to step S3; if it does not hit, jumps to step S5;

Step S7: The Cache controller searches the TagSram through the high bit of the address. If the data corresponding to the address already exists in the Sram, the data hits and jumps to step S2; if it does not hit, jumps to step S6;

Step S8: The Cache controller starts this data loading, feeds back the first data read on the bus to the processor, and jumps to step S1 to execute the next read transfer.

Compared with the prior art, the above-mentioned technical scheme of the present invention has the following advantages: the Cache controller and working method of the present invention, by using dual-port Sram, when the write port of Sram is occupied, the processor can pass the read port of Sram Take the port and continue to access the hit data. Therefore, there is no mutual interference between the loading operation and the access hit data, and a certain logic area is exchanged for the efficiency of the entire system.

Description of drawings

In order to make the content of the present invention more clearly understood, the present invention will be further described in detail below according to the specific embodiments of the present invention and in conjunction with the accompanying drawings.

Fig. 1 is the topological schematic diagram of the Cache controller in the system of the present invention;

Fig. 2 is the storage schematic diagram of dual-port Sram in the Cache controller of the present invention;

Fig. 3 is the work flowchart of Cache controller of the present invention;

Fig. 4 is a kind of sequence diagram of Cache controller of the present invention;

FIG. 5 is another timing diagram of the Cache controller of the present invention.

Detailed ways

As shown in Fig. 1, the present embodiment provides a kind of Cache controller based on dual-port Sram, adds a level of Cache controller in the middle of processor and memory, and Cache controller is made up of dual-port Sram and related control circuit thereof, is used for Accelerates the read speed of the processor.

As shown in FIG. 2, it is a storage diagram of TagSram and DataSram in the Cache controller. TagSram is used to store flag bits, V(x) uses 0 or 1 to indicate whether the data of a certain offset address in the cache is valid, and the number of bits of V can be 2 ⁿ (n=0, 1, 2, 3, etc. )indivual. The value of T is taken from the high-order bits of the address, and the number of bits depends on the capacity of Sram, which can be used to match future read addresses. The DataSram is used to store data, and its width can be 2 ⁿ (n=0, 1, 2, 3, etc.) times the width of the Bus.

As shown in FIG. 3 , it is a working flowchart of the Cache controller.

The working method of Cache controller, based on the Cache controller design of dual-port Sram described in claim 1-2, is characterized in that: comprise the steps:

Step S1: The processor initiates a read transfer on the bus, the Cache controller receives the request, and jumps to step S7;

Step S2: The processor can directly read the data in Sram and jump to step S1 to perform the next read transfer;

Step S3: The processor can directly read the data on the Bus and jump to step S1 to perform the next read transfer;

Step S4: wait for the bus loading work to be completed and then jump to step S8;

Step S5: The current read data of the processor does not exist in the Cache controller, and the controller needs to load data from the memory; if there is currently a loading operation being executed, then jump to step S4, if not, then jump to step S8 ;

Step S6: The Cache controller matches the read address of the current processor and the read address being loaded by the current bus. If the two addresses are the same, the data hits and jumps to step S3; if it does not hit, jumps to step S5;

Step S7: The Cache controller searches the TagSram through the high bit of the address. If the data corresponding to the address already exists in the Sram, the data hits and jumps to step S2; if it does not hit, jumps to step S6;

Step S8: The Cache controller starts this data loading, feeds back the first data read on the bus to the processor, and jumps to step S1 to execute the next read transfer.

Figure 4 and Figure 5 are timing diagrams of the Cache controller, and the signals involved in the diagrams are described as follows.

Clk: global clock signal. CoreAddr: Processor read address; CoreRdata: Processor read data.

Symbol Ax(y): Indicates that the processor will read data from address x and offset address y.

HitSram: Indicates that the current transmission hits Sram, and the processor reads data from Sram. TagSramAddr1: Read address of TagSram; TagSramRead: Read enable of TagSram; TagSramDout: Tag value read in TagSram. TagSram Addr2: Write address of TagSram; TagSramWrite: Write enable of TagSram; TagSramDin: Tag value to be written into TagSram.

Symbol STx: indicates the tag of address x read from TagSram.

The signal meaning of DataSram is similar to that of TagSram.

Symbol SDx: indicates the data of address x read from DataSram.

HitBus: Indicates that the current transmission hits the Bus, and the processor reads data from the Bus. BusAddr: the address of the current load operation; BusRdata: the read data of the current load operation.

Symbol BDx(y): Indicates that the address read from the Bus is x, and the data whose offset address is y.

As shown in FIG. 4 , the first read transfer initiated by the processor with the address A1(1) hits the Sram, and the second read transfer initiated by the processor with the address A2(2) misses the Sram. The specific process is as follows:

At time T1, the processor initiates a read transfer with address A1(1), and simultaneously reads the tag and data corresponding to address A1 from TagSram and DataSram.

At T2, the address high bit matches the label ST1 and V(1) is valid, indicating that the data at the current address already exists in the Sram, the HitSram signal is pulled high, and the processor directly reads the data SD1(1) from the DataSram.

At time T3, the processor initiates a read transfer with address A2(2), and simultaneously reads the tag and data corresponding to address A2 from TagSram and DataSram.

At time T4, the address high bit does not match the label ST2 or V(2) is invalid, indicating that the data at the current address does not exist in the Sram, and the controller needs to load a piece of data containing the current required data from the external memory.

At T5, clear the V of the A2 address in TagSram, and at the same time write the high bit of the currently transmitted address as a tag. Initiate a read transfer with BusAddr A2(2) on the bus.

At time T7, the processor reads the first data BD2(2) read on the bus. Write V(2) to address A2 in TagSram. Write data BD2(2) to address A2(2) in DataSram. Initiate a read transfer with BusAddr A2(0) on the bus.

At time T10, write V(0) into address A2 in TagSram. Write data BD2(0) to address A2(0) in DataSram. Initiate a read transfer on the bus with BusAddr A2(1).

At time T11, write V(1) into address A2 in TagSram. Write data BD2(1) to address A2(0) in DataSram. Initiate a read transfer with BusAddr A2(3) on the bus.

At time T12, write V(3) into address A2 in TagSram. Write data BD2(3) to address A2(0) in DataSram.

As shown in Figure 5: the first time is the read transfer initiated by the processor with the address A2(2) and misses the Sram, the second time is the read transfer initiated by the processor with the address A3(3) and hit the Sram, the second time is the read transfer initiated by the processor with the address A3(3) and hit the Sram Three read transfers initiated by the processor with the address A2(1) and hitting the Bus. Since there are many parallel operations in this process, the description will be explained from two perspectives, namely "processor and Sram read port" and "bus and Sram write port". The specific process is as follows:

T1 moment,

Processor and Sram read port: The processor initiates a read transfer with address A2(2), and reads the tag and data corresponding to address A2 from TagSram and DataSram at the same time.

Bus and Sram write port: idle.

T2 moment,

Processor and Sram read port: The address high bit does not match the label ST2 or V(2) is invalid, indicating that the data at the current address does not exist in the Sram, and the controller needs to load a piece of data containing the current required data from the external memory.

Bus and Sram write port: idle.

T3 moment,

Processor and Sram read ports: idle.

Bus and Sram write port: Clear the V of the A2 address in TagSram, and write the high bit of the currently transmitted address as a tag. Initiate a read transfer with BusAddr A2(2) on the bus.

T5 moment,

Processor and Sram read port: The processor reads the first data BD2(2) read on the bus. The processor initiates a read transfer with address A3(3), and reads the tag and data corresponding to address A3 from TagSram and DataSram at the same time.

Bus and Sram write port: write V(2) to A2 address in TagSram. Write data BD2(2) to address A2(2) in DataSram. Initiate a read transfer with BusAddr A2(0) on the bus.

At time T6,

Processor and Sram read port: the address high bit matches the label ST3 and V(3) is valid, indicating that the data at the current address already exists in Sram, the HitSram signal is pulled high, and the processor directly reads data SD3(3) from DataSram.

Bus and Sram write port: free.

At time T8,

Processor and Sram read port: The processor initiates a read transfer with address A2(1), and reads the tag and data corresponding to address A2 from TagSram and DataSram at the same time.

Bus and Sram write port: write V(0) to A2 address in TagSram. Write data BD2(0) to address A2(0) in DataSram. Initiate a read transfer on the bus with BusAddr A2(1).

T9 moment,

Processor and Sram read port: the address high bit matches the label ST2 but V(1) is invalid, indicating that the data at the current address does not exist in Sram; the bus address matches the processor read address, the HitBus signal is pulled high, and the processor directly reads from the Bus Read data on BD2(1).

Bus and Sram write port: write V(1) to A2 address in TagSram. Write data BD2(1) to address A2(0) in DataSram. Initiate a read transfer with BusAddr A2(3) on the bus.

Time T10,

Processor and Sram read ports: idle.

Bus and Sram write port: write V(3) to A2 address in TagSram. Write data BD2(3) to address A2(0) in DataSram.

Apparently, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation. For those of ordinary skill in the art, on the basis of the above description, other various changes or modifications can also be made. It is not necessary and impossible to exhaustively list all the implementation manners here. However, the obvious changes or changes derived therefrom are still within the scope of protection of the present invention.

Claims (3)

1. The Cache controller based on the dual-port Sram is composed of the dual-port Sram and a related control circuit thereof, and is characterized in that the dual-port Sram is used for caching data of a memory, a read port is used for matching read transmission of a processor, a write port is used for loading read data of a bus, and the two ports are not affected by each other; the Cache controller can continuously match the read operation address of the processor while loading data from the memory, and can immediately feed back the data if the Cache controller hits Sram or Bus; the width of the dual-port Sram in the Cache controller is 2 of the bus width ⁿ Multiple, 2 can be loaded from memory on each miss ⁿ Data; the Cache controller may match the data in Sram, or may match the data on the bus being transferred.

2. The Cache controller of claim 1, wherein: the Sram comprises TagSram and DataSram, wherein TagSram is used for storing a flag bit, V (x) is used for indicating whether data of a certain offset address in the strip cache is valid or not by 0 or 1, and the bit number of V can be 2 ⁿ A plurality of; the value of T is taken from the high bits of the address, the number of bits depending on the capacity of the Sram, which can be used to match the subsequent read address; dataSram is used to store data, and its width may be 2 of Bus width ⁿ Multiple times.

The working method of the Cache controller based on the dual-port Sram Cache controller design of claim 1-2 is characterized by comprising the following steps: the method comprises the following steps:

step S1: the processor initiates a read transmission on the bus, the Cache controller receives the request and jumps to step S7;

step S2: the processor can directly read the data in the Sram and jump to the step S1 to execute the next read transmission;

step S3: the processor can directly read the data on the Bus and jump to the step S1 to execute the next read transmission;

step S4: waiting for bus loading work to be completed and then jumping to the step S8;

step S5: the current read data of the processor does not exist in the Cache controller, and the controller needs to load the data from the memory; if the loaded operation is currently being executed, jumping to the step S4, and if not, jumping to the step S8;

step S6: the Cache controller matches the read address of the current processor and the read address of the current bus under loading, if the two addresses are the same, the data hits and jumps to step S3; if not, jumping to step S5;

step S7: the Cache controller searches TagSram through the high-order address, if the data corresponding to the address exists in the Sram, the data hits and jumps to step S2; if not, jumping to step S6;

step S8: the Cache controller starts the data loading, feeds back the first data read on the bus to the processor, and jumps to step S1 to execute the next read transmission.

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