CN116157003A - Resistive random access memory element, memory device and manufacturing method thereof - Google Patents

Abstract

The invention provides a resistive random access storage element, a storage device and a preparation method thereof. The storage element includes a first electrode, a resistive storage layer and a second electrode arranged in sequence; the material of the second electrode is MNx, The material of the resistive storage layer is MOy, wherein M is selected from one of Ti, Ta and Al. In the present invention, the metal atoms of the second electrode and the metal atoms of the resistive storage layer are set to be the same metal atoms, and at the same time have the same metal atoms as the conductive channel, which can effectively prevent the M metal atoms participating in the conductive channel from being too rich Set, thereby improving the life and durability of the device, and improving the retention ability of the device, thereby obtaining better device performance. In the present invention, by controlling the ratio of N in the second electrode, the second electrode can be provided with conductivity, and at the same time, the migration and diffusion of metal ions into the resistive storage layer can be more controllable.

Description

Resistive random access memory element, memory device and manufacturing method thereof

technical field

The invention belongs to the field of design and manufacture of semiconductor integrated circuits, in particular to a resistive random access memory element, a memory device and a preparation method thereof.

Background technique

Resistive random-access memory (ReRAM) is a kind of non-volatile memory (non-volatile memory, NVM), which has smaller size, fast read and write, long data storage time, low power consumption, The characteristics of good reliability and compatibility with the semiconductor manufacturing process are gradually attracting attention in this field. The basic structure of resistive random access memory is that a variable resistance layer is sandwiched between the upper and lower electrodes, and the variable resistance material is made to be in a high resistance state (high resistance state, HRS) and a low resistance state (low resistance state) by applying an external voltage. resistancestate, LRS), and then compile different resistance states into 1 or 0 to achieve the purpose of storing and distinguishing data.

The current resistive random access memory (ReRAM) is mainly divided into conductive bridge random access memory (conductive-bridge random access memory, CBRAM) and oxide random access memory (Oxygen-vacancy random access memory, OxRAM). The structure mainly includes three parts: top electrode (TE), resistive switch layer (SL) and bottom electrode (BE). In the oxide random access memory, oxygen ions in the resistive switch layer (SL) migrate under the action of an electric field, and finally form a conductive channel (filament) composed of oxygen vacancies. In the conductive bridge random access memory, the metal in one electrode will ionize under the action of an electric field and enter the resistive switch layer (SL), and finally form a conductive channel composed of metal particles. Existing resistive random access memory devices often face various problems in reliability, for example, their cycle characteristics and retention capabilities are limited by materials.

It should be noted that the above introduction to the technical background is only for the convenience of a clear and complete description of the technical solution of the present application, and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are known to those skilled in the art just because these solutions are described in the background technology section of this application.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a resistive random access memory element, a memory device and a preparation method thereof, which are used to solve the problem of insufficient reliability of the resistive random access memory in the prior art The problem.

To achieve the above object and other related objects, the present invention provides a resistive random access memory element, the resistive random access memory element includes: a first electrode, a resistive memory layer and a second electrode arranged in sequence; The material of the second electrode is MNx, wherein M is selected from one of Ti, Ta and Al, and 0≤x≤1.

Optionally, the second electrode MNx includes n second sub-electrode layers, n≥2, and the ratio of N among the n second sub-electrode layers is from the resistive variable memory layer toward the resistive variable memory layer. The direction of storage layers decreases layer by layer.

Optionally, the difference between the N ratio x in two adjacent second sub-electrode layers is greater than or equal to 0.05.

Optionally, among the n second sub-electrode layers, the thickness of the second sub-electrode layer with the largest N ratio x is less than or equal to 5 nanometers.

Optionally, among the n second sub-electrode layers, the thickness of the second sub-electrode layer increases as the N ratio x decreases.

Optionally, the N ratio x in the second electrode MNx decreases linearly from the resistive storage layer toward a direction away from the resistive storage layer.

Optionally, the ratio x of N in the second electrode MNx is greater than or equal to 0.3, and less than or equal to the stoichiometric ratio of M and N.

Optionally, the material of the resistive storage layer is MOy, and the metal atoms in the resistive storage layer MOy are the same as the metal atoms in the second electrode MNx, wherein M is selected from Ti, Ta and Al One of them, 0≤y≤1.

Optionally, the metal atom in the conductive channel of the resistive random access memory element is M, which is the same as the metal atom in the second electrode MNx and the resistive memory layer MOy, wherein the metal atom M migrates forming a conductive channel composed of metal atoms M in the second electrode and the resistive storage layer, so that the resistive storage layer is converted into a low resistance state, or/and the O in the resistive storage layer Migration occurs to form a conductive channel formed by oxygen holes in the resistive storage layer, so that the resistive storage layer is transformed into a low-resistance state.

Optionally, the material of the first electrode is an inert metal or a metal nitride, the inert metal includes one of W and Pt, and the metal nitride includes one of TiN and TaN.

Optionally, sidewall structures of the first electrode, the resistive storage layer and the second electrode are further formed.

Optionally, the resistive random access memory element further includes: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, The electrode hole structure includes a damascene structure; the electrode hole structure is filled with metal electrodes, and the metal atoms in the metal electrodes are M the same as the metal atoms in the second electrode MNx.

The present invention also provides a resistive random access memory device, which includes an array composed of a plurality of resistive random access memory elements described in any one of the solutions above.

The present invention also provides a method for preparing a resistive random access memory element. The preparation method includes the steps of: forming a first electrode, a resistive memory layer, and a second electrode arranged in sequence, and the material of the second electrode is MNx, wherein, M is selected from one of Ti, Ta and Al, 0≤x≤1.

Optionally, forming the second electrode includes: growing n layers of second sub-electrode layers layer by layer on the resistive variable storage layer by a deposition method, and controlling the N in each layer of the second sub-electrode layer ratio, so that the N ratio x in the n second sub-electrode layers decreases layer by layer from the resistive memory layer toward the direction away from the resistive memory layer.

Optionally, forming the second electrode includes: growing n layers of second sub-electrode layers layer by layer on the resistive variable storage layer by a deposition method, by controlling the ratio of N in each second sub-electrode layer , so that the N ratio x in the n second sub-electrode layers decreases layer by layer from the resistive memory layer toward the direction away from the resistive memory layer; by performing an annealing process under an N atmosphere, the The N in the second sub-electrode layer diffuses, so that the N ratio x in the second electrode MNx decreases linearly from the resistive memory layer toward the direction away from the resistive memory layer.

Optionally, the ratio of N in each of the second sub-electrode layers is adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition process.

Optionally, the preparation method further includes a step of: forming sidewall structures on sidewalls of the first electrode, the resistive memory layer and the second electrode.

Optionally, the preparation method further includes the steps of: forming an interlayer dielectric layer on the second electrode; forming an electrode hole structure exposing the second electrode in the interlayer dielectric layer, and the electrode hole structure It includes a damascene structure; a metal electrode is formed in the electrode hole structure, and the metal atoms in the metal electrode are M the same as the metal atoms in the second electrode MNx and the resistive variable storage layer MOy.

Optionally, forming the resistive variable storage layer includes: growing multiple layers of MOy material layers layer by layer by a deposition method, and adjusting the concentration of O in each layer of MOy material layers by controlling the ambient atmosphere, power, and bias voltage during the deposition process. Proportion.

As mentioned above, the resistive random access memory element of the present invention and its preparation method have the following beneficial effects:

In the present invention, the material of the second electrode is set as MNx, the material of the resistive storage layer is set as MOy, the metal atoms of the second electrode and the metal atoms of the resistive storage layer are set as the same metal atoms, and at the same time, it is compatible with the conductive The channel has the same metal atoms, which can effectively avoid the over-enrichment of M metal atoms participating in the formation of the conductive channel, thereby improving the life and durability of the device, and improving the retention capacity of the device, thereby obtaining better device performance.

In the present invention, by controlling the ratio of N in the second electrode MNx, the second electrode can be provided with conductivity, and at the same time, the migration and diffusion of metal ions into the resistive storage layer can be more controllable.

The preparation process of the present invention can control the proportion of N in the second electrode MNx according to different requirements, which is convenient for adjusting device performance, and the process has stronger controllability.

Description of drawings

The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and explain the principle of the present application together with the text description. Apparently, the drawings in the following description are only some embodiments of the present application.

FIG. 1 is a schematic structural diagram of a resistive random access memory element according to an embodiment of the present invention.

FIG. 2 is a schematic structural diagram of another resistive random access memory element according to an embodiment of the present invention.

3 to 11 are schematic structural diagrams of each step of the manufacturing method of the resistive random access memory device according to the embodiment of the present invention.

FIG. 12 is a graph showing cycle characteristics of a resistive random access memory device implemented in the present invention.

FIG. 13 is a graph showing cycle characteristics of a resistive random access memory element realized for a conventional method.

Component designation description

101 First electrode

102 Resistive storage layer

103, 104 second electrode

1031, 1032, 1033 second sub-electrode layer

201 metal layer

202 interlayer dielectric layer

203 conductive hole

105 side wall structure

106 insulating layer

107 electrode hole structure

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

It should be emphasized that the term "comprising/comprising" when used herein refers to the presence of a feature, integer, step or component, but does not exclude the presence or addition of one or more other features, integers, steps or components.

Features described and/or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with, or instead of features in other embodiments .

For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in Figure 1, this embodiment provides a resistive random access memory element, which includes: a first electrode 101, a resistive memory layer 102 and a second electrode 103 arranged in sequence The material of the second electrode 103 is MNx (metal nitride), the material of the resistive storage layer 102 is MOy (metal oxide), wherein, M is selected from Ti (titanium), Ta (tantalum) and One of Al (aluminum), 0≤x≤1, 0≤y≤1. For example, the material of the second electrode 103 may be TiNx, the material of the resistive storage layer 102 is TiOy, or the material of the second electrode 103 may be TaNx, and the material of the resistive storage layer 102 is TaOy, or alternatively, the material of the second electrode 103 may be AlNx, and the material of the resistive memory layer 102 is AlOy. In the present invention, the material of the second electrode 103 is set to MNx, the material of the resistive storage layer 102 is set to MOy, and the metal atoms of the second electrode 103 and the metal atoms of the resistive storage layer 102 are set to be the same metal atoms, and at the same time Having the same metal atoms as the conductive channel formed can effectively avoid excessive enrichment of M metal atoms participating in the conductive channel, thereby improving the life and durability of the device, and improving the retention capacity of the device, thereby obtaining better device performance.

In one embodiment, the material of the first electrode 101 is an inert metal or a metal nitride. Specifically, the inert metal can be one of W and Pt, and the metal nitride can be TiN or TaN. kind of.

In one embodiment, the second electrode 103 includes n second sub-electrode layers 1031, 1032, 1033, n≥2, N (nitrogen) in n second sub-electrode layers 1031, 1032, 1033 The ratio x decreases layer by layer from the resistive storage layer 102 toward a direction away from the resistive storage layer 102 .

As shown in FIG. 1, in a specific example, the second electrode 103 includes three second sub-electrode layers 1031, 1032, 1033, and the ratio of N in the three second sub-electrode layers 1031, 1032, 1033 It may be x1, x2 and x3 respectively, and x1, x2 and x3 decrease layer by layer from the resistive storage layer 102 toward the direction away from the resistive storage layer 102, that is, x1>x2>x3.

In one embodiment, the N ratio x in the second electrode 103 is greater than or equal to 0.3 to ensure that it has a better control effect on the migration and diffusion of metal ions into the resistive variable storage layer 102, and the N ratio x Less than or equal to the stoichiometric ratio of M and N, in order to avoid the structure stability and conductivity of the second electrode 103 being affected by an excessively high N ratio, the N ratio in the two adjacent second sub-electrode layers 1031, 1032, 1033 The difference of x is greater than or equal to 0.05, so as to form a better control effect on the migration and diffusion of metal ions through the N ratio gradient.

In a specific example, taking the second electrode 103 as AlNx as an example, the stoichiometric ratio of Al and N is 1, and the N ratio x can range from 0.3 to 1. For example, in AlNx, x1, x2 and x3 The values of can be 1, 0.8, 0.6 respectively, that is, the materials of the three second sub-electrode layers 1031, 1032, 1033 are AlN, AlN _0.8 , AlN _0.6 respectively. Of course, the values of x1, x2 and x3 can also be 0.8, 0.5 and 0.3, that is, the materials of the three second sub-electrode layers 1031, 1032 and 1033 are AlN _0.8 , AlN _0.5 and AlN _0.3 respectively. Certainly, the value of N of each of the second sub-electrode layers 1031 , 1032 , 1033 in the AlNx can be set according to actual device requirements, and is not limited to the examples listed above. In other embodiments, the material of the second electrode 103 can also be TiNx or TaNx, and its specific value can be set according to the parameter requirements of the device. The number of the second sub-electrode layers 1031 , 1032 , 1033 included in the second electrode 103 can also be set to be more layers, for example, it can be 4-10 layers. In the present invention, by controlling the ratio of N in the second electrode 103 , the second electrode 103 can be provided with conductivity, and the migration and diffusion of metal ions into the resistive memory layer 102 can be more controllable.

In one embodiment, among the n second sub-electrode layers 1031, 1032, 1033, the thickness of the second sub-electrode layer 1031, 1032, 1033 with the largest N ratio x is less than or equal to 5 nanometers, so as to ensure that the subsequent Metal atoms can pass through the second sub-electrode layer 1031 , 1032 , 1033 with the largest N ratio x to reach the resistive memory layer 102 and form a conductive channel. In one embodiment, among the n second sub-electrode layers 1031 , 1032 , 1033 , the thicknesses of the second sub-electrode layers 1031 , 1032 , 1033 increase as the N ratio x decreases.

In one embodiment, FIG. 2 is a schematic structural diagram of another resistive random access memory element. In the resistive random access memory element in FIG. 2 , the N ratio x in the second electrode 104 is from The resistive storage layer 102 decreases linearly in a direction away from the resistive storage layer 102 . The resistive random access memory element removes the layer-by-layer change of the N ratio in the above embodiment, and sets the N ratio x to a linear change, which can make the migration and diffusion of metal atoms smoother and more controllable. higher.

In one embodiment, the metal atom in the conductive channel of the resistive random access memory element is M, which is the same as the metal atom in the second electrode 103 and the resistive memory layer 102, wherein the metal atom M migrates to the second electrode 103 and the resistive storage layer 102 to form a conductive channel composed of metal atoms M, so that the resistive storage layer 102 changes to a low resistance state, or/and the resistive storage layer 102 O (oxygen) in the storage layer 102 migrates to form a conductive channel formed by oxygen holes in the resistive storage layer 102 , so that the resistive storage layer 102 changes to a low-resistance state.

In one embodiment, please refer to FIG. 10 or FIG. 11 , sidewalls of the first electrode, the resistive memory layer and the second electrode may also be formed with a sidewall structure 105 .

In one embodiment, referring to FIG. 10 or FIG. 11, the resistive random access memory element may further include: an interlayer dielectric layer 106 disposed on the second electrode; An electrode hole structure exposing the second electrode is formed, and the electrode hole structure includes a Damascene structure; the electrode hole structure is filled with a metal electrode 107, and the metal atoms in the metal electrode 107 are M and the second electrode. The metal atoms in the electrodes MNx are the same.

This embodiment also provides a resistive random access memory device, which includes an array composed of a plurality of resistive random access memory elements as described in any one of the solutions above.

As shown in FIGS. 3 to 11 , this embodiment also provides a method for manufacturing a resistive random access memory element. The method includes the steps of: forming a first electrode 101 , a resistive memory layer 102 and The second electrode 103, the material of the second electrode 103 is MNx, the material of the resistive storage layer 102 is MOy, wherein M is selected from one of Ti, Ta and Al, 0≤x≤1, 0≤y≤1.

Specifically, the preparation method comprises the following steps:

As shown in Figure 3, step 1) is carried out at first, and a circuit substrate is provided, and the substrate includes a substrate, a metal layer 201 disposed on the substrate, an insulating layer 106 disposed on the metal layer 201, and a circuit substrate disposed on the substrate. The conductive hole 203 in the insulating layer 106 .

The substrate may be, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a III-V compound substrate, a silicon carbide substrate, an SOI substrate, and the like. Various circuit elements, such as NMOS transistors, PMOS transistors, capacitors, resistors, etc., may be formed in the substrate to realize corresponding circuit functions.

As shown in Figure 4, then proceed to step 2), by using a deposition method to form a first electrode 101 on the circuit substrate, the material of the first electrode 101 is an inert metal or metal nitride, specifically, the inert The metal can be one of W and Pt, and the metal nitride can be one of TiN and TaN.

As shown in FIG. 5, step 3) is then performed to form a resistive storage layer 102 on the first electrode 101. Specifically, multiple layers of MOy material layers can be grown layer by layer by a deposition method, and by controlling the deposition process The ratio of O in each MOy material layer is adjusted by ambient atmosphere, power, and bias voltage.

As shown in FIG. 6 , step 4) is followed to form the second electrode 103 on the resistive storage layer 102 .

In one embodiment, forming the second electrode 103 includes the following steps: growing n layers of second sub-electrode layers 1031, 1032, 1033 layer by layer on the resistive storage layer 102 by a deposition method, and controlling each layer The ratio of N in the second sub-electrode layers 1031, 1032, 1033 is such that the ratio x of N in the n second sub-electrode layers 1031, 1032, 1033 moves from the resistive storage layer 102 toward the The direction of the resistive storage layer 102 decreases layer by layer. Specifically, the ratio of N in each of the second sub-electrode layers 1031 , 1032 , 1033 can be adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition process.

In another embodiment, forming the second electrode 104 includes: growing n layers of second sub-electrode layers layer by layer on the resistive variable storage layer 102 by a deposition method, and controlling each layer of the second sub-electrode layer The ratio of N in the n second sub-electrode layers, so that the N ratio x in the n second sub-electrode layers decreases layer by layer from the resistive memory layer 102 toward the direction away from the resistive memory layer 102; performing an annealing process to diffuse N in the second sub-electrode layer, so that the ratio x of N in the second electrode 104 is linear from the resistive memory layer 102 toward the direction away from the resistive memory layer 102 reduced, the final device structure is shown in Figure 11.

As shown in FIG. 7 , proceed to step 5) to pattern the second electrode 103 and the resistive storage layer 102. Specifically, by growing silicon nitride as a hard mask, photolithography and etching After patterning the silicon nitride, the second electrode 103 and the resistive memory layer 102 are etched using silicon nitride as a mask to form a desired pattern.

As shown in FIG. 8 , step 6) is followed to form sidewall structures 105 on the sidewalls of the first electrode 101 , the resistive memory layer 102 and the second electrode 103 . Specifically, the sidewall structure 105 may be formed by a deposition method, and then the above-mentioned silicon nitride hard mask is removed.

As shown in FIG. 9 , step 7) is followed to form an interlayer dielectric layer 202 on the second electrode 103 . The interlayer dielectric layer 202 can be, for example, silicon dioxide or the like.

As shown in FIG. 10 , finally perform step 8), forming an electrode hole structure 107 exposing the second electrode 103 in the interlayer dielectric layer 202; forming a metal electrode in the electrode hole structure 107, and the metal electrode The metal atoms in the electrodes are M the same as the metal atoms in the second electrode 103 and the resistive storage layer 102 .

In one embodiment, the electrode hole structure 107 includes a damascene structure.

FIG. 12 shows the cycle characteristics of the resistive random access memory element realized by the present invention, and FIG. 13 shows the cycle characteristics of the resistive random access memory element realized by the conventional method. Among them, the circle point is the high resistance of the device, and the triangle point is the low resistance of the device. From the comparison of Fig. 12 and Fig. 13, it can be seen that the resistive random access memory element realized by the present invention in Fig. 12 has more constricted high and low resistance values. The random access memory elements were basically successfully cycled for 1000 times, while the resistive random access memory element realized by the conventional method in FIG. 13 had a large number of cycle failures. It can be seen that the present invention can effectively improve the service life and durability of the device, and improve the holding capacity of the device, thereby obtaining better device performance.

As mentioned above, the resistive random access memory element, memory device and preparation method thereof of the present invention have the following beneficial effects:

In the present invention, the material of the second electrode is set as MNx, the material of the resistive storage layer is set as MOy, the metal atoms of the second electrode and the metal atoms of the resistive storage layer are set as the same metal atoms, and at the same time, it is compatible with the conductive The channel has the same metal atoms, which can effectively avoid the over-enrichment of M metal atoms participating in the formation of the conductive channel, thereby improving the life and durability of the device, and improving the retention capacity of the device, thereby obtaining better device performance.

In the present invention, by controlling the ratio of N in the second electrode, the second electrode can be provided with conductivity, and at the same time, the migration and diffusion of metal ions into the resistive storage layer can be more controllable.

The preparation process of the present invention can control the proportion of N in the second electrode according to different requirements, which is convenient for adjusting device performance, and the process has stronger controllability.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (20)

1. A resistive random access memory element, the resistive random access memory element comprising:

the first electrode, the resistance change storage layer and the second electrode are sequentially arranged;

and the material of the second electrode is MNx, wherein M is one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

2. The resistive random access memory element of claim 1, wherein: the second electrode MNx comprises N second sub-electrode layers, N is more than or equal to 2, and the proportion x of N in the N second sub-electrode layers is reduced layer by layer from the resistive memory layer towards the direction away from the resistive memory layer.

3. The resistive random access memory element of claim 2, wherein: the difference of the N proportion x in the two adjacent second sub-electrode layers is larger than or equal to 0.05.

4. The resistive random access memory element of claim 2, wherein: and in the N second sub-electrode layers, the thickness of the second sub-electrode layer with the largest N proportion x is less than or equal to 5 nanometers.

5. The resistive random access memory element of claim 2, wherein: the thickness of the N second sub-electrode layers increases with the decrease of the N proportion x.

6. The resistive random access memory element of claim 1, wherein: the N ratio x in the second electrode MNx decreases linearly from the resistive memory layer toward a direction away from the resistive memory layer.

7. The resistive random access memory element of claim 1, wherein: the N ratio x in the second electrode MNx is greater than or equal to 0.3 and less than or equal to the stoichiometric ratio of M and N.

8. The resistive random access memory element of claim 1, wherein: the resistive memory layer is made of MOy, and metal atoms in the resistive memory layer MOy are the same as metal atoms in the second electrode MNx, wherein M is selected from one of Ti, ta and Al, and y is more than or equal to 0 and less than or equal to 1.

9. The resistive random access memory element of claim 8, wherein: the metal atoms of the conductive channel of the resistive random access memory element are M, which are the same as the metal atoms in the second electrode MNx and the resistive memory layer MOy, wherein the metal atoms M migrate to the second electrode and form the conductive channel composed of the metal atoms M in the resistive memory layer, so that the resistive memory layer is converted into a low-resistance state, or/and the O in the resistive memory layer migrates to form the conductive channel formed by oxygen holes in the resistive memory layer, so that the resistive memory layer is converted into a low-resistance state.

10. The resistive random access memory element of claim 1, wherein: the material of the first electrode is an inert metal or a metal nitride, wherein the inert metal comprises one of W and Pt, and the metal nitride comprises one of TiN and TaN.

11. The resistive random access memory element of claim 1, wherein: and side wall structures are formed on the side walls of the first electrode, the resistance change storage layer and the second electrode.

12. The resistive random access memory element of claim 1, wherein: the resistive random access memory element further includes: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, and the electrode hole structure comprises a Damascus structure; and the electrode hole structure is filled with a metal electrode, and metal atoms in the metal electrode are M and the same as metal atoms in the second electrode MNx.

13. A resistive random access memory device comprising an array of a plurality of resistive random access memory elements according to any one of claims 1 to 12.

14. A method of manufacturing a resistive random access memory element according to any one of claims 1 to 12, comprising the steps of:

and forming a first electrode, a resistive random access memory layer and a second electrode which are sequentially arranged, wherein the material of the second electrode is MNx, M is selected from one of Ti, ta and Al, and x is more than or equal to 0 and less than or equal to 1.

15. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the second electrode includes:

and growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and reducing the N proportion x in the N second sub-electrode layers layer by layer from the resistive random access memory layer towards the direction away from the resistive random access memory layer by controlling the N proportion in each layer of the second sub-electrode layers.

16. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the second electrode includes:

growing N layers of second sub-electrode layers layer by layer on the resistive random access memory layer by a deposition method, and controlling the proportion of N in each layer of second sub-electrode layers to enable the proportion x of N in N second sub-electrode layers to be reduced layer by layer from the resistive random access memory layer towards a direction away from the resistive random access memory layer;

and (3) performing an annealing process in an N atmosphere to diffuse N in the second sub-electrode layer, so that the proportion x of N in the second electrode MNx linearly decreases from the resistive memory layer towards a direction away from the resistive memory layer.

17. The method of manufacturing a resistive random access memory device according to claim 15 or 16, wherein: the proportion of N in each second sub-electrode layer is regulated by controlling the ambient atmosphere, power and bias voltage in the deposition process.

18. The method of manufacturing a resistive random access memory device according to claim 14, wherein: the method also comprises the steps of: and forming a side wall structure on the side walls of the first electrode, the resistive random access memory layer and the second electrode.

19. The method of manufacturing a resistive random access memory device according to claim 14, wherein: the method also comprises the steps of:

forming an interlayer dielectric layer on the second electrode;

forming an electrode hole structure exposing the second electrode in the interlayer dielectric layer, wherein the electrode hole structure comprises a Damascus structure;

and forming a metal electrode in the electrode hole structure, wherein metal atoms in the metal electrode are M and the same as those in the second electrode MNx and the resistive random access memory layer MOy.

20. The method of manufacturing a resistive random access memory device according to claim 14, wherein: forming the resistive memory layer includes:

and growing a plurality of MOy material layers layer by a deposition method, and regulating the proportion of O in each MOy material layer by controlling the ambient atmosphere, power and bias voltage in the deposition process.

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