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CN116154005A - A kind of layout and preparation method of NOR Flash - Google Patents

A kind of layout and preparation method of NOR Flash Download PDF

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Publication number
CN116154005A
CN116154005A CN202310196225.8A CN202310196225A CN116154005A CN 116154005 A CN116154005 A CN 116154005A CN 202310196225 A CN202310196225 A CN 202310196225A CN 116154005 A CN116154005 A CN 116154005A
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Prior art keywords
floating gate
flash
control gate
pattern
active region
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杨洋
周长见
沈安星
张有志
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Yuexin Semiconductor Technology Co ltd
South China University of Technology SCUT
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Yuexin Semiconductor Technology Co ltd
South China University of Technology SCUT
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention provides a layout of NOR Flash and a preparation method thereof, wherein the layout of NOR Flash comprises an active region graph, a floating gate graph and a control gate graph, the floating gate graph and the active region graph are vertically intersected, and each intersection point is provided with one floating gate graph, and the floating gate graph is positioned in the control gate graph, so that the upper surface and the side wall of a floating gate are covered by the control gate when the layout of NOR Flash is adopted for preparation, namely five surfaces of the floating gate are covered by the control gate, thereby two covering surfaces are increased, the optimized layout of NOR Flash can improve the coupling coefficient of a NOR Flash storage unit, the realization difficulty of a high-voltage device process is reduced, and the layout is simple, high in operability and easy to realize.

Description

Layout and preparation method of NOR Flash
Technical Field
The invention relates to the technical field of semiconductors, in particular to a layout and a preparation method of NOR Flash.
Background
With the progress of semiconductor technology, semiconductor memories bring more convenience to the storage and transmission of data in the work and life of people, and the semiconductor memories are continuously and intensively researched and developed to improve the safety and the use efficiency of data storage. The memory can be classified into a volatile type memory which can store data only when power is turned on and a nonvolatile type memory which can store data without loss even when power is turned off. The ideal nonvolatile memory has the advantages of high integration level, high access speed, low power consumption, wide working temperature range, single power supply operation and the like, so that the nonvolatile memory can be widely applied to production and life. NOR Flash is a nonvolatile memory, which can realize online erasable and programmable operations, and has the advantages of easy use, low cost and high reliability, so that NOR Flash is a nonvolatile memory which is very long in the development history of semiconductors, and the figure of NOR Flash is visible in almost every electronic product, which has important milestone significance for the development of nonvolatile memories.
As shown in fig. 1, the current NOR Flash sequentially comprises a P-type substrate, a tunnel oxide layer, a Floating Gate (FG), an ONO charge blocking layer and a Control Gate (CG), wherein a sidewall is formed around the Floating Gate (FG), the ONO charge blocking layer and the control gate, the floating gate is used for storing charges, the sidewall insulates the floating gate and the control gate from the outside, the P-type substrate has an active region, the active region comprises a source region and a drain region, and the tunnel oxide layer, the floating gate, the ONO charge blocking layer and the control gate are all located on the P-type substrate between the source region and the drain region. The electric charges enter and exit the floating gate under the action of a strong electric field, so that the erasing and writing of the memory cell are realized, wherein the electric charges on the floating gate represent "1", and the electric charges on the floating gate represent "0". When the floating gate does not reach the maximum stored charge amount, the larger the voltage applied to the control gate, the larger the charge amount stored on the floating gate.
As shown in fig. 2, in the equivalent circuit of NOR Flash, when an external voltage is directly applied to a control gate, the voltage is indirectly applied to a floating gate by using a capacitive voltage division principle through a coupling effect, and the coupling coefficient characterizes the voltage divided by the floating gate. Thus, when the same voltage is applied to the control gate, the larger the coupling coefficient is, the more the floating gate is divided into voltages. While the coupling coefficient of a conventional NOR Flash memory cell is limited.
Disclosure of Invention
The invention aims to provide a layout and a preparation method of NOR Flash, which can improve the coupling coefficient of a NOR Flash storage unit.
In order to solve the problems, the invention provides a layout of NOR Flash, which comprises an active region pattern, a floating gate pattern and a control gate pattern, wherein the floating gate pattern is vertically intersected with the active region pattern, each intersection point is provided with one floating gate pattern, and the floating gate pattern is positioned in the control gate pattern.
Optionally, the length of the floating gate pattern in the second direction is 0.15 μm smaller than the length of the control gate pattern in the second direction, and an axis of the floating gate pattern in the second direction overlaps with an axis of the control gate pattern in the second direction.
Optionally, all the active region patterns are arranged in parallel along a first direction, and each active region pattern extends along a second direction; and
all the control gate patterns are arranged in parallel along the second direction, and each control gate pattern extends along the first direction.
Optionally, the length of the floating gate pattern along the first direction is greater than the length of the active region pattern along the first direction.
On the other hand, the invention also provides a preparation method of the NOR Flash, which adopts the layout of the NORFlash and comprises the following steps:
step S1: providing a substrate, forming an active region on the substrate by adopting an active region pattern, forming a floating gate on the substrate of the active region by adopting a floating gate pattern, and covering part of the substrate at two sides of the active region along a first direction by the floating gate;
step S2: forming a control gate on the floating gate by adopting a control gate pattern, wherein the control gate covers the upper surface and the side wall of the floating gate; and
step S3: and forming a source electrode and a drain electrode in the active region to form a storage unit of NOR Flash, thereby forming the NOR Flash.
Optionally, step S1 specifically includes:
providing a substrate, wherein a p-well region is formed in the substrate, and a tunneling oxide layer is formed on the substrate of the p-well region;
forming an active region on the substrate by adopting the active region pattern through an etching process, so that the tunneling oxide layer covers the substrate of the active region, wherein the active region comprises a source region and a drain region;
forming a floating gate on the tunneling oxide layer between the source region and the drain region by adopting the floating gate pattern, wherein the floating gate also covers part of the substrate at two sides of the active region along a first direction; and
and forming a charge blocking layer on the floating gate, wherein the charge blocking layer covers the upper surface and the side wall of the floating gate and the substrate outside the floating gate.
Further, the step S2 specifically includes:
forming a control gate film layer on the charge blocking layer by adopting the control gate pattern, so that the control gate film layer covers the charge blocking layer on the upper surface of the floating gate, the charge blocking layer on the side wall of the floating gate and the charge blocking layer between the adjacent active areas;
removing the control gate film layer on part of the charge blocking layer between the adjacent active areas through an etching process to form a control gate; and
and forming side walls at two ends of the floating gate, the charge blocking layer and the control gate along the second direction.
Further, the length of the control gate in the first direction is 0.1 μm larger than the length of the floating gate in the first direction.
Further, the length of the control gate in the second direction is 0.15 μm larger than the length of the floating gate in the second direction.
Further, the step S3 specifically includes:
forming a photoresist layer, wherein the photoresist layer covers the upper surface of the control gate, the surface of the side wall and the charge blocking layer on the substrate;
forming a patterned photoresist layer through a photoetching process, wherein the patterned photoresist layer exposes the charge blocking layer on the source region;
removing the charge blocking layer on the source region through an etching process to expose the tunnel oxide layer on the source region;
forming source electrodes in the source electrode regions through an ion implantation process, wherein each source electrode is a self-aligned common source electrode of two adjacent memory cells in the same active region; and
and forming a drain electrode in the drain electrode region through an ion implantation process to form a storage unit of NOR Flash, thereby forming the NOR Flash.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a layout of NOR Flash and a preparation method thereof, wherein the layout of NOR Flash comprises an active region graph, a floating gate graph and a control gate graph, wherein the floating gate graph and the active region graph are vertically intersected, each intersection point is provided with one floating gate graph, and the floating gate graph is positioned in the control gate graph, so that the upper surface and the side wall of a floating gate are covered by a control gate when the layout of NORFflash is adopted for preparation, namely five surfaces of the floating gate are covered by the control gate, two covering surfaces are increased, the coupling coefficient of a NOR Flash memory cell can be improved by the optimized layout of NOR Flash, the realization difficulty of a high-voltage device process is reduced, and the layout is simple, high in operability and easy to realize.
Drawings
FIG. 1 is a schematic diagram of a NOR Flash architecture;
FIG. 2 is an equivalent circuit of the NOR Flash memory cell of FIG. 1;
FIG. 3 is a layout diagram of a NOR Flash;
FIG. 4 is a schematic diagram of a layout of NOR Flash provided by an embodiment of the present invention;
fig. 5-7 are schematic structural diagrams of NOR Flash provided in an embodiment of the present invention in a preparation process.
Reference numerals illustrate:
in fig. 1-2:
10-a substrate; 20-a tunnel oxide layer; 31-floating gate; a 32-ONO charge blocking layer; 33-control gate; 34-side walls; x-a first direction; y-a second direction; s-source electrode; d-drain electrode;
in fig. 3-5:
100-a substrate; 200-a tunnel oxide layer; 310-floating gate; 320-a charge blocking layer; 330-control gate; 340-side walls; 400-photoresist layer; 110' -active region pattern; 310' -floating gate pattern; 330' -control gate pattern; x-a first direction; y-a second direction; s-source electrode; d-drain.
Detailed Description
As described in the background art, the coupling coefficient characterizes the voltage of the floating gate, and the factors affecting the coupling coefficient are the contact area of the ONO charge blocking layer and the control gate, the contact area of the ONO charge blocking layer and the floating gate, the thickness of the ONO charge blocking layer, the contact area of the floating gate and the tunnel oxide layer, the thickness of the tunnel oxide layer, and the like. Because the NOR Flash requires high-voltage driving during operation, the high-voltage device requires higher process conditions than the low-voltage device, and is difficult to realize, so that in order to reduce the process manufacturing difficulty of the high-voltage device, the consideration is required to be given to how to obtain a larger coupling coefficient in the process of device design.
As shown in fig. 3, the length of the control gate in the second direction y is the same as the length of the active region in the second direction y, so that the control gate cannot cover both end surfaces of the floating gate in the second direction y. Therefore, the control gate of the conventional NOR Flash covers only three surfaces of the floating gate (i.e., both end surfaces of the floating gate in the first direction x from the upper surface of the floating gate), and thus the coupling coefficient of the resulting NOR Flash memory cell is limited.
Wherein, the coupling coefficient C of the traditional NOR Flash R The following formula is satisfied:
Figure BDA0004107312870000051
Figure BDA0004107312870000052
Figure BDA0004107312870000053
wherein C1 is the capacitance at the ONO charge blocking layer; c2 is the capacitance at the tunnel oxide layer; d (D) 2 Is the thickness of the ONO charge blocking layer; w (W) 1 The length of the floating gate along the first direction; l (L) 1 The length of the floating gate along the second direction; d (D) 1 The thickness of the floating gate; w (W) 2 The length of the tunneling oxide layer along the first direction; l (L) 2 The length of the tunneling oxide layer along the second direction; d (D) 3 Is the thickness of the tunnel oxide layer.
The layout makes the coupling coefficient of the traditional NOR Flash memory cell limited.
Therefore, the invention provides a layout of NOR Flash and a preparation method thereof, the layout of NOR Flash comprises an active region graph, a floating gate graph and a control gate graph, the floating gate graph and the active region graph are vertically intersected, each intersection point is provided with one floating gate graph, and the floating gate graph is positioned in the control gate graph, so that the upper surface and the side wall of a floating gate are covered by a control gate when the layout of NOR Flash is adopted for preparation, namely five surfaces of the floating gate are covered by the control gate, two covering surfaces are increased, the coupling coefficient of a NOR Flash memory cell can be improved by the optimized layout of NOR Flash, the realization difficulty of a high-voltage device process is reduced, and the layout is simple, high in operability and easy to realize.
The layout and the preparation method of the NOR Flash are further described in detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
Fig. 4 is a schematic diagram of a layout of NOR Flash provided in this embodiment. As shown in fig. 4, the present embodiment provides a layout of a NOR Flash, which includes an active region pattern 110', a floating gate pattern 310', and a control gate pattern 330', where the active region pattern 110' is used to form an active region in a NOR Flash memory cell, the floating gate pattern 310 'is used to form a floating gate in the NOR Flash memory cell, and the control gate pattern 330' is used to form a control gate in the NOR Flash memory cell.
All the active region patterns 110 'are disposed in parallel along the first direction x, and each of the active region patterns 110' extends along the second direction y. All the control gate patterns 330 'are disposed in parallel along the second direction y, and each of the control gate patterns 330' extends along the first direction x. The floating gate pattern 310' is disposed to intersect the active region pattern 110' perpendicularly, and has one of the floating gate patterns 330' at each intersection, and the floating gate pattern 310' is located within the control gate pattern 330 '.
Wherein the length of the control gate pattern 330 'along the second direction y is greater than the length of the floating gate pattern 310' along the second direction y, preferably, the length of the floating gate pattern 310 'along the second direction y is 0.15 μm smaller than the length of the control gate pattern 330' along the second direction y, and the axis of the floating gate pattern 310 'along the second direction y overlaps with the axis of the control gate pattern 330' along the second direction y. The length of the floating gate pattern 310 'along the first direction x is greater than the length of the active region pattern 110' along the first direction x.
All the control gate patterns 330 'are arranged in parallel along the second direction y and vertically intersect all the active region patterns 110', and one floating gate pattern 310 'on each active region pattern 110' is covered, so that the length of the floating gate pattern 310 'along the second direction y is smaller than that of the control gate pattern 330' along the second direction y, and the length of the floating gate pattern 310 'along the first direction x is smaller than that of the control gate pattern 330' along the first direction x, namely, the floating gate pattern 310 'is positioned in the control gate pattern 330', and the layout of the NOR Flash of the embodiment is simple, high in operability and easy to implement.
When the NOR Flash is manufactured, after the control gate pattern 330' is used for forming the control gate on the floating gate, an etching process is used for etching the control gate, so that the control gate on each floating gate is independent respectively, namely the control gate on each storage unit and the control gates on other storage units are mutually independent, each control gate can cover the upper surface of one floating gate, two end faces of the floating gate in the first direction x and two end faces of the floating gate in the second direction y, namely each control gate covers five surfaces of the floating gate in each storage unit, the optimized layout of the NOR Flash can improve the coupling coefficient of the NOR Flash storage unit, and the realization difficulty of the high-voltage device process is reduced.
At this time, coupling coefficient C of NOR Flash R The following formula is satisfied:
Figure BDA0004107312870000071
Figure BDA0004107312870000072
Figure BDA0004107312870000073
wherein C1 is the capacitance at the charge blocking layer; c2 is the capacitance at the tunnel oxide layer; w (W) 1 The length of the floating gate along the first direction; l (L) 1 The length of the floating gate along the second direction; d (D) 1 The thickness of the floating gate; d (D) 2 Is the thickness of the charge blocking layer; w (W) 2 The length of the tunneling oxide layer along the first direction; l (L) 2 The length of the tunneling oxide layer along the second direction; d (D) 3 Is the thickness of the tunnel oxide layer.
It can be seen that, compared with the coupling coefficient of the conventional NOR Flash memory cell, the coupling coefficient of the NORFlash memory cell of the embodiment increases the contact area between the control gate and the floating gate (i.e., increases the coverage area of the control gate covering both end surfaces of the floating gate in the second direction y), thereby increasing the coupling coefficient of the memory cell.
The embodiment also provides a preparation method of the NOR Flash, which comprises the following steps:
step S1: providing a substrate, forming an active region on the substrate by adopting an active region pattern, forming a floating gate on the substrate of the active region by adopting a floating gate pattern, and covering part of the substrate at two sides of the active region along a first direction by the floating gate;
step S2: forming a control gate on the floating gate by adopting a control gate pattern, wherein the control gate covers the upper surface and the side wall of the floating gate; and
step S3: and forming a source electrode and a drain electrode in the active region to form a storage unit of NOR Flash, thereby forming the NOR Flash.
The following describes in detail a preparation method of NOR Flash provided in this embodiment with reference to FIGS. 5 to 7.
As shown in fig. 5, step S1 is first performed, providing a substrate 100, forming an active region (not shown) on the substrate 100 using an active region pattern, and forming a floating gate 310 on the substrate 100 using the floating gate pattern.
The method specifically comprises the following steps:
first, a substrate 100 is provided, a p-well region is formed in the substrate 100, and a tunnel oxide layer 200 is formed on the substrate 100 of the p-well region.
The substrate 100 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, and may be a die, or may be a wafer processed by an epitaxial growth process, and in detail, the substrate 100 is, for example, a silicon substrate.
Next, forming an active region on the substrate 100 by an etching process using the active region pattern such that the tunneling oxide layer 200 covers the substrate 100 of the active region, the active region including a source region and a drain region;
next, forming a floating gate 310 on the tunneling oxide layer 200 between the source region and the drain region using the floating gate pattern, the floating gate 310 further covering a portion of the substrate 100 on both sides of the active region along the first direction x;
next, a charge blocking layer 320 is formed on the floating gate 310, the charge blocking layer 320 covering the upper surface and the sidewalls of the floating gate 310 (i.e., the end surfaces of the floating gate 310 at both ends in the first direction x and the end surfaces of the floating gate 310 at both ends in the second direction y), that is, the charge blocking layer 320 covering five surfaces of the floating gate 310 except the lower surface, the charge blocking layer 320 also covering the substrate 100 outside the floating gate 310.
The charge blocking layer 320 includes a first sub-blocking layer, a second blocking layer, and a third blocking layer, where the first sub-blocking layer and the third blocking layer are both oxide material layers, and the second blocking layer is a nitride material layer.
Next, step S2 is performed to form a control gate 330 on the charge blocking layer 320 using a control gate pattern, wherein the control gate 330 covers the upper surface and the sidewalls of the floating gate 310.
The method specifically comprises the following steps:
first, a control gate film layer is formed on the charge blocking layer 320 using the control gate pattern such that the control gate film layer covers the charge blocking layer 320 on the upper surface of the floating gate 310, the charge blocking layer 320 on the sidewalls of the floating gate 310 (i.e., the end surfaces of the floating gate at both ends in the first direction x and the end surfaces of the floating gate at both ends in the second direction y), and the charge blocking layer 320 between adjacent active regions.
Next, the control gate film layer on the portion of the charge blocking layer 320 between adjacent active regions is removed by an etching process to form the control gate 330. Wherein the length of the control gate 330 in the first direction x is 0.1 μm greater than the length of the floating gate 310 in the first direction x. The length of the control gate 330 in the second direction y is 0.15 μm greater than the length of the floating gate 310 in the second direction y, so that the control gate 330 covers the charge blocking layer 320 on the upper surface of the floating gate 310, the charge blocking layer 320 on the sidewalls of the floating gate 310 (i.e., the end surfaces of the floating gate at both ends in the first direction x and the end surfaces of the floating gate at both ends in the second direction y).
In this way, the control gate 330 covers five surfaces of the floating gate 310, thereby increasing the contact area between the control gate 330 and the charge blocking layer 320, and the contact area between the floating gate 310 and the charge blocking layer 320, thereby increasing the coupling coefficient of the memory cell, i.e., increasing the voltage to which the floating gate 310 is divided under the same voltage applied to the control gate 330.
Next, side walls 340 are formed at two ends of the floating gate, the charge blocking layer and the control gate along the second direction y, the side walls 340 include a first side wall, a second side wall and a third side wall which are sequentially formed at two ends of the floating gate 310, the charge blocking layer 320 and the control gate 330 along the second direction y, for example, the first side wall and the third side wall are both oxide material layers, and the second side wall is a nitride material layer.
As shown in fig. 6, step S3 is then performed to form a source S and a drain D in the active region to form a memory cell of NOR Flash, thereby forming NOR Flash.
The method specifically comprises the following steps:
first, a photoresist layer 400 is formed, and the photoresist layer 400 covers the upper surface of the control gate 330, the surface of the sidewall 340, and the charge blocking layer 320 on the substrate 100.
Next, forming a patterned photoresist layer 400 through a photolithography process, wherein the patterned photoresist layer 400 exposes the charge blocking layer 320 on the source region;
then, removing the charge blocking layer 320 on the source region by an etching process to expose the tunnel oxide layer 200 on the source region;
next, forming source electrodes S in the source regions by an ion implantation process, wherein each source electrode S is a self-aligned common source electrode of two adjacent memory cells in the same active region;
and then forming a drain electrode D in the drain electrode region through an ion implantation process to form a storage unit of NOR Flash, thereby forming the NOR Flash.
In summary, the invention provides a layout and a preparation method of NOR Flash, the layout of NOR Flash comprises an active region graph, a floating gate graph and a control gate graph, the floating gate graph and the active region graph are vertically intersected, each intersection is provided with one floating gate graph, and the floating gate graph is positioned in the control gate graph, so that the upper surface and the side wall of a floating gate are covered by a control gate when the layout of NOR Flash is adopted for preparation, namely five surfaces of the floating gate are covered by the control gate, two covering surfaces are increased, the coupling coefficient of a NOR Flash memory cell can be improved by the optimized layout of NOR Flash, the realization difficulty of a high-voltage device process is reduced, and the layout is simple, high in operability and easy to realize.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims (10)

1.一种NOR Flash的版图，其特征在于，包括有源区图形、浮栅图形和控制栅图形，所述浮栅图形与有源区图形垂直相交设置，且在每个相交点上均具有一个所述浮栅图形，所述浮栅图形位于所述控制栅图形内。1. The layout of a kind of NOR Flash is characterized in that, comprises active region pattern, floating gate pattern and control gate pattern, and described floating gate pattern and active region pattern vertical intersect are arranged, and all have on each intersecting point One said floating gate pattern, said floating gate pattern is located in said control gate pattern. 2.如权利要求1所述的NOR Flash的版图，其特征在于，所述浮栅图形在第二方向上的长度较所述控制栅图形在第二方向上的长度小0.15μm，且所述浮栅图形在第二方向上的轴线与所述控制栅图形在第二方向上的轴线重叠。2. The layout of NOR Flash according to claim 1, wherein the length of the floating gate pattern in the second direction is 0.15 μm shorter than the length of the control gate pattern in the second direction, and the The axis of the floating gate pattern in the second direction overlaps the axis of the control gate pattern in the second direction. 3.如权利要求1所述的NOR Flash的版图，其特征在于，3. The layout of NOR Flash as claimed in claim 1, is characterized in that, 所有所述有源区图形沿第一方向平行设置，且每个所述有源区图形沿第二方向延伸；以及All of the active area patterns are arranged in parallel along a first direction, and each of the active area patterns extends along a second direction; and 所有所述控制栅图形沿第二方向平行设置，且每个所述控制栅图形沿第一方向延伸。All the control gate patterns are arranged in parallel along the second direction, and each of the control gate patterns extends along the first direction. 4.如权利要求1所述的NOR Flash的版图，其特征在于，所述浮栅图形沿第一方向的长度大于所述有源区图形沿第一方向的长度。4. The NOR Flash layout according to claim 1, wherein the length of the floating gate pattern along the first direction is greater than the length of the active region pattern along the first direction. 5.一种NOR Flash的制备方法，采用如权利要求1～4中任一项所述的NOR Flash的版图，其特征在于，包括以下步骤：5. A preparation method of NOR Flash, adopting the layout of NOR Flash as described in any one of claims 1 to 4, is characterized in that, comprises the following steps: 步骤S1：提供一衬底，采用有源区图形在所述衬底上形成有源区，采用浮栅图形在所述有源区的衬底上形成浮栅，所述浮栅还沿第一方向覆盖所述有源区两侧的部分衬底；Step S1: providing a substrate, using an active region pattern to form an active region on the substrate, using a floating gate pattern to form a floating gate on the substrate of the active region, and the floating gate is also along the first direction covering part of the substrate on both sides of the active region; 步骤S2：采用控制栅图形在所述浮栅上形成控制栅，所述控制栅覆盖所述浮栅的上表面和侧壁；以及Step S2: using a control gate pattern to form a control gate on the floating gate, the control gate covering the upper surface and side walls of the floating gate; and 步骤S3：在所述有源区形成源极和漏极，以形成NOR Flash的存储单元，从而形成NORFlash。Step S3: forming a source and a drain in the active region to form a storage unit of NOR Flash, thereby forming NORFlash. 6.如权利要求5所述的NOR Flash的制备方法，其特征在于，步骤S1具体包括：6. The preparation method of NOR Flash as claimed in claim 5 is characterized in that, step S1 specifically comprises: 提供一衬底，所述衬底中形成有p阱区，在所述p阱区的衬底上形成有隧穿氧化层；A substrate is provided, a p-well region is formed in the substrate, and a tunnel oxide layer is formed on the substrate of the p-well region; 采用所述有源区图形通过刻蚀工艺在所述衬底上形成有源区，使得所述隧穿氧化层覆盖所述有源区的衬底，所述有源区包括源极区和漏极区；Using the active region pattern to form an active region on the substrate through an etching process, so that the tunnel oxide layer covers the substrate of the active region, and the active region includes a source region and a drain Polar region; 采用所述浮栅图形在所述源极区和漏极区之间的隧穿氧化层上形成浮栅，所述浮栅还沿第一方向覆盖所述有源区两侧的部分衬底；以及Using the floating gate pattern to form a floating gate on the tunnel oxide layer between the source region and the drain region, the floating gate also covers part of the substrate on both sides of the active region along a first direction; as well as 在所述浮栅上形成电荷阻挡层，所述电荷阻挡层覆盖所述浮栅的上表面和侧壁，以及所述浮栅外侧的所述衬底。A charge blocking layer is formed on the floating gate, the charge blocking layer covers the upper surface and sidewalls of the floating gate, and the substrate outside the floating gate. 7.如权利要求6所述的NOR Flash的制备方法，其特征在于，步骤S2具体包括：7. The preparation method of NOR Flash as claimed in claim 6, is characterized in that, step S2 specifically comprises: 采用所述控制栅图形在所述电荷阻挡层上形成控制栅膜层，使得所述控制栅膜层覆盖所述浮栅上表面的电荷阻挡层、所述浮栅侧壁上的电荷阻挡层、以及相邻所述有源区之间的电荷阻挡层；Using the control gate pattern to form a control gate film layer on the charge blocking layer, so that the control gate film layer covers the charge blocking layer on the upper surface of the floating gate, the charge blocking layer on the side wall of the floating gate, and a charge blocking layer between adjacent active regions; 通过刻蚀工艺去除相邻所述有源区之间的部分电荷阻挡层上的控制栅膜层，以形成控制栅；以及removing the control gate film layer on a portion of the charge blocking layer between adjacent active regions by an etching process to form a control gate; and 在所述浮栅、电荷阻挡层和控制栅沿第二方向的两端形成侧墙。Spacers are formed at both ends of the floating gate, the charge blocking layer and the control gate along the second direction. 8.如权利要求7所述的NOR Flash的制备方法，其特征在于，所述控制栅在第一方向上的长度较所述浮栅在第一方向上的长度大0.1μm。8. The manufacturing method of NOR Flash according to claim 7, wherein the length of the control gate in the first direction is 0.1 μm larger than the length of the floating gate in the first direction. 9.如权利要求7所述的NOR Flash的制备方法，其特征在于，所述控制栅在第二方向上的长度较所述浮栅在第二方向上的长度大0.15μm。9. The method for manufacturing NOR Flash according to claim 7, wherein the length of the control gate in the second direction is 0.15 μm larger than the length of the floating gate in the second direction. 10.如权利要求7所述的NOR Flash的制备方法，其特征在于，步骤S3具体包括：10. The preparation method of NOR Flash as claimed in claim 7, is characterized in that, step S3 specifically comprises: 形成光刻胶层，所述光刻胶层覆盖了所述控制栅的上表面、所述侧墙的表面、以及所述衬底上的电荷阻挡层；forming a photoresist layer, the photoresist layer covering the upper surface of the control gate, the surface of the spacer, and the charge blocking layer on the substrate; 通过光刻工艺形成图形化的光刻胶层，图形化的所述光刻胶层暴露出所述源极区上的电荷阻挡层；forming a patterned photoresist layer through a photolithography process, and the patterned photoresist layer exposes the charge blocking layer on the source region; 通过刻蚀工艺去除所述源极区上的电荷阻挡层，以暴露出所述源极区上的隧道氧化层；removing the charge blocking layer on the source region through an etching process to expose the tunnel oxide layer on the source region; 通过离子注入工艺在所述源极区形成源极，每个所述源极为同一个所述有源区中相邻的两个存储单元的自对准共源极；以及Forming sources in the source region by an ion implantation process, each of the sources is a self-aligned common source of two adjacent memory cells in the same active region; and 在所述漏极区通过离子注入工艺形成漏极，以形成NOR Flash的存储单元，从而形成NOR Flash。A drain is formed in the drain region by an ion implantation process to form a NOR Flash storage unit, thereby forming a NOR Flash.
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