CN116133434A - An antifuse device and its manufacturing method - Google Patents

Abstract

The embodiment of the disclosure provides an antifuse device and a manufacturing method thereof. The antifuse device includes: the first doped region and the second doped region are arranged in the substrate; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer which are arranged in close proximity along a first direction, and the length of the second gate oxide layer along a second direction is larger than that of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the surface of the substrate; the second gate oxide layer includes a first portion between the first doped region and the second doped region and a second portion between the first doped region and the first gate oxide layer; the thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate; and a gate electrode positioned on the gate oxide layer.

Description

An antifuse device and its manufacturing method

technical field

Embodiments of the present disclosure relate to the technical field of semiconductor manufacturing, and in particular, to an antifuse device and a manufacturing method thereof.

Background technique

One-time programmable read-only memory (One-Time-Programmable Read Only Memory, OTPROM) can be programmed by the user independently, providing users with a certain degree of flexibility, but once programmed, the data cannot be erased electrically, therefore, The design complexity is simplified and the cost is reduced.

Currently, the OTP read-only memory includes a fuse type and an anti-fuse type. Among them, the storage unit of the fuse type memory is turned on when no data is written, showing a low resistance state, which is a state; through a certain mechanism, such as high temperature, high voltage, etc., the storage unit is fused, showing High-impedance state, so as to realize the writing of data, this is another state. The storage unit of the anti-fuse memory is disconnected when no data is written, and it is in a high-impedance state. The resistance state, so as to realize the data writing process, is another state.

Contents of the invention

In view of this, the embodiments of the present disclosure provide an antifuse device and a manufacturing method thereof to solve at least one technical problem existing in the prior art.

In order to achieve the above object, the technical solution of the present disclosure is achieved in the following way:

In a first aspect, an embodiment of the present disclosure provides an antifuse device, and the antifuse device includes:

a first doped region and a second doped region disposed in the substrate;

a gate oxide layer on the substrate, the gate oxide layer includes a first gate oxide layer and a second gate oxide layer adjacently arranged along a first direction, and the length of the second gate oxide layer along a second direction is greater than The length of the first gate oxide layer along the second direction, wherein both the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer includes A first part between the doped region and the second doped region and a second part between the first doped region and the first gate oxide layer; the first gate oxide layer is along the third The upward thickness is smaller than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface;

A gate on the gate oxide layer.

In some embodiments, the first portion of the second gate oxide layer and the first gate oxide layer are respectively located on adjacent two sides of the second doped region.

In some embodiments, the orthographic projection of the gate on the substrate is L-shaped.

In some embodiments, the orthographic area of the second doped region on the substrate is smaller than the orthographic area of the first doped region on the substrate.

In some embodiments, the sum of the length of the orthographic projection of the second doped region on the substrate along the second direction and the length of the first gate oxide layer along the second direction is equal to the The length of the second gate oxide layer along the second direction.

In some embodiments, the sum of the orthographic projection areas of the second doped region and the first gate oxide layer on the substrate is equal to the orthographic projection area of the second gate oxide layer on the substrate area.

In some embodiments, the antifuse device also includes:

a word line, the word line is connected to the gate;

A bit line, the bit line is connected to the first doped region or the second doped region.

In some embodiments, the first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a drain region. area is the source area.

In a second aspect, an embodiment of the present disclosure provides a method of manufacturing an antifuse device, the method of manufacturing including:

provide the substrate;

A gate oxide layer is formed on the substrate; the gate oxide layer includes a first gate oxide layer and a second gate oxide layer adjacently arranged along a first direction, and a length of the second gate oxide layer along a second direction is greater than The length of the first gate oxide layer along the second direction, wherein both the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer is along the length of the second direction including a first portion and a second portion in contact with the first gate oxide layer; a thickness of the first gate oxide layer along a third direction is smaller than a thickness of the second gate oxide layer along the third direction, wherein, The third direction is a direction perpendicular to the surface of the substrate;

forming a gate on the gate oxide layer;

A first doped region is formed in the substrate on a side of the second gate oxide layer far away from the first gate oxide layer, and a first part of the second gate oxide layer is far away from the first doped region. A second doped region is formed in one side of the substrate.

In some embodiments, the first portion of the second gate oxide layer and the first gate oxide layer are respectively located on adjacent two sides of the second doped region.

In some embodiments, the orthographic projection of the gate on the substrate is L-shaped.

In some embodiments, the orthographic area of the second doped region on the substrate is smaller than the orthographic area of the first doped region on the substrate.

In some embodiments, the sum of the length of the orthographic projection of the second doped region on the substrate along the second direction and the length of the first gate oxide layer in the second direction equal to the length of the second gate oxide layer in the second direction.

In some embodiments, the sum of the orthographic projection areas of the second doped region and the first gate oxide layer on the substrate is equal to the orthographic projection area of the second gate oxide layer on the substrate area.

In some embodiments, the manufacturing method also includes:

forming a word line, the word line is connected to the gate;

A bit line is formed, and the bit line is connected to the first doped region or the second doped region.

In some embodiments, the first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a drain region. area is the source area.

Embodiments of the present disclosure provide an antifuse device and a manufacturing method thereof. The antifuse device includes: a first doped region and a second doped region arranged in a substrate; a gate oxide layer located on the substrate, and the gate oxide layer includes A first gate oxide layer and a second gate oxide layer, the length of the second gate oxide layer along the second direction is greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer includes a first part located between the first doped region and the second doped region and a portion located between the first doped region and the second portion between the first gate oxide layer; the thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the The third direction is a direction perpendicular to the surface of the substrate; the gate on the gate oxide layer. In the embodiment of the present disclosure, by reducing the length of the first gate oxide layer, the length of the first gate oxide layer is smaller than the length of the second gate oxide layer; The first doped region is arranged in the bottom, and the second doped region is arranged in the substrate on the side of the first part of the second gate oxide layer away from the first doped region; rationally adjust the first doped region, the second doped region The positional relationship between the impurity region, the first gate oxide layer, the second gate oxide layer and the gate improves the structure of the antifuse device, thereby reducing the area of the antifuse device and further increasing the storage density of the antifuse device .

Description of drawings

FIG. 1 is a planar layout diagram of two antifuse units provided by an embodiment of the present disclosure;

FIG. 2 is a planar layout diagram of an antifuse unit provided by an embodiment of the present disclosure;

Fig. 3 is a schematic cross-sectional structure diagram of the antifuse unit in Fig. 2 along the line AA;

FIG. 4 is a planar layout diagram of two antifuse units provided by another embodiment of the present disclosure;

FIG. 5 is a plan layout diagram of an antifuse unit provided by another embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional structure diagram of the antifuse unit in FIG. 5 along line BB;

FIG. 7 is a schematic cross-sectional structure diagram of the antifuse unit in FIG. 5 along line CC;

FIG. 8 is a schematic flowchart of a method for manufacturing an antifuse device provided by an embodiment of the present disclosure;

9 is a schematic cross-sectional structure diagram of a process for forming a first gate oxide layer and a second gate oxide layer according to an embodiment of the present disclosure;

The figure includes: 101, 201, substrate; 102, 202, active region; 103, source; 203, second doped region; 104, drain; 204, first doped region; 105, 205, P Well region; 106, 206, gate oxide layer; 106a, thin gate oxide layer; 106b, thick gate oxide layer; 206a, first gate oxide layer; 206b, second gate oxide layer; 107, 207, gate; 208, Isolation layer; 209, silicide layer; 210, bit line contact pad; 301, channel region; 302, first gate oxide region; 303, second gate oxide region; 304, first oxide layer; 305 , The second oxide layer.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. Based on the implementation manners in the present disclosure, all other implementation manners obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment are not described here, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. , adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. Whereas a second element, component, region, layer or section is discussed, it does not indicate that the present disclosure necessarily presents a first element, component, region, layer or section.

Spatial terms such as "below...", "below...", "below", "below...", "on...", "above" and so on, can be used here for convenience are used in description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be provided in the following description, so as to explain the technical solution of the present disclosure. Preferred embodiments of the present disclosure are described in detail as follows, however, the present disclosure may have other embodiments besides these detailed descriptions.

Read Only Memory (ROM) stores fixed data and generally can only be read out. Once information is stored in read-only memory, it cannot be easily changed and will not be lost when power is turned off. ROM is a memory that only provides readout in a computer system. According to different data writing methods, ROM can be divided into fixed ROM and programmable ROM. The latter can be subdivided into programmable read-only memory (Programmable ROM, PROM), OTP read-only memory, programmable erasable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable programmable read-only memory ( ElectricallyErasable Programmable ROM, EEPROM) and flash memory (Flash ROM), etc.

OTP read-only memory can be programmed once by the user, which provides users with a certain degree of flexibility, but once programmed, the data cannot be erased by electricity, so the complexity of the design is simplified and the cost is reduced.

Currently, the OTP read-only memory includes a fuse type and an anti-fuse type. Among them, anti-fuse (Anti-fuse) memory, before programming, the anti-fuse is a high-resistance insulating medium equivalent to a capacitor, almost no current flows, and the data read by the memory cell is "0"; after programming, When the programming voltage is applied, the antifuse is broken down, which is equivalent to a low-resistance conductor, the circuit is turned on, and a certain current can pass through, and the data read out by the memory cell is "1". The punctured anti-fuse memory cell forms a permanent on-circuit, no matter how many times the subsequent read process is re-read, it will not affect the state of the anti-fuse.

The antifuse memory mainly includes upper and lower electrodes and an antifuse medium layer between the upper and lower electrodes. According to the different materials of the antifuse dielectric layer, the antifuse can be classified into oxide-nitride-oxide (Oxide-Nitride-Oxide, ONO) antifuse, amorphous silicon (Amorphous Silicon, A-Si) antifuse Fuses and Gate Oxide Antifuses.

Further, there are three main structures of antifuse devices based on gate oxide layer, which are three-transistor (3Transistor, 3T) structure, 1.5-transistor (1.5Transistor, 1.5T) structure and single-transistor (1Transistor, 1T) structure. The principle of data is to rely on the breakdown of the gate oxide layer of the MOS transistor to realize data storage, and the main difference lies in the number of MOS transistors in the storage unit. Among them, the 3T anti-fuse memory cell structure uses three MOS transistors to store one bit of data, and the three MOS transistors are respectively a storage transistor, a high-voltage blocking transistor and a word line gating transistor. The 1.5T antifuse memory cell structure uses two MOS transistors to store one bit of data, but the thickness of the gate oxide layer of the two MOS transistors is different, and the source electrode of the thick gate oxide layer MOS transistor and the thin gate oxide layer MOS transistor Drain coincidence; Among them, the thick gate oxide MOS tube is used for word line control and high voltage protection, which is equivalent to the high voltage blocking tube and word line gating tube in the 3T antifuse memory cell structure, and the thin gate oxide layer MOS tube is used for storing data . The 1T antifuse memory cell structure is to make transistors with gate oxide layers of different thicknesses into a single transistor.

The structure of the antifuse unit provided by an embodiment of the present disclosure will be described in detail below with reference to FIG. 1 , FIG. 2 and FIG. 3 . Here, the antifuse unit provided by an embodiment of the present disclosure is a 1T antifuse unit structure.

It should be noted that the direction perpendicular to the surface of the substrate is the Z direction. An X direction and a Y direction intersecting each other are defined on the top or bottom surface of the substrate perpendicular to the Z direction, and the top or bottom surface of the substrate perpendicular to the Z direction can be determined based on the X and Y directions. For example, the X direction and the Y direction have a certain angle. For another example, the X direction and the Y direction are perpendicular to each other, thus, the X direction, the Y direction and the Z direction are perpendicular to each other.

As shown in Fig. 1, Fig. 2 and Fig. 3, the antifuse device includes: a P well region 105 arranged in a substrate 101, an active region 102 arranged in a P well region 105, and the active region 102 includes a source 103 and drain 104; a gate oxide layer 106 on the substrate 101, the gate oxide layer 106 includes a thin gate oxide layer 106a and a thick gate oxide layer 106b arranged side by side; a gate 107 on the gate oxide layer 106. The dashed-line box in FIG. 1 and FIG. 2 shows the active region 102 , and the solid-line box in FIG. 1 and FIG. 2 shows the antifuse unit.

It should be noted that, in order to illustrate the positional relationship between the thin gate oxide layer 106a and the thick gate oxide layer 106b, FIG. 1 and FIG. It means that the composition materials of the thin gate oxide layer 106a and the thick gate oxide layer 106b are different, but the thin gate oxide layer 106a and the thick gate oxide layer 106b can still be made of the same material. FIG. 3 shows that the thin gate oxide layer 106a and the thick gate oxide layer 106b are composed of the same material.

In addition, in order to illustrate the positional relationship between the thin gate oxide layer 106a and the thick gate oxide layer 106b, and to avoid the gate 107 from covering the thin gate oxide layer 106a and the thick gate oxide layer 106b, FIG. 1 and FIG. The perspective view of the thin gate oxide layer 106a and the thick gate oxide layer 106b observed from the electrode 107, that is, the thin gate oxide layer 106a and the thick gate oxide layer 106b cover the gate 107, which does not represent the thin gate oxide layer 106a and the thick gate oxide layer 106b in practical applications. A thick gate oxide layer 106b is located on the gate 107 .

Here, forming active regions (ie, source and drain) within the substrate may use an ion implantation process. The particles that need to be doped are incident on the substrate through ion beams, and through a series of physical and chemical interactions, the doped particles will gradually lose energy and stay in it to form the source or drain. Embodiments of the present disclosure do not specifically limit the doping types of the source and the drain, for example, the source and the drain may be N-type doped.

Here, the orthographic projection areas of the source and the drain on the substrate may be equal.

Still referring to FIG. 1 and FIG. 2, the gate oxide layer 106 is located between the source electrode 103 and the drain electrode 104, the gate oxide layer 106 includes a thin gate oxide layer 106a and a thick gate oxide layer 106b, and the thin gate oxide layer 106a and the thick gate oxide layer 106b are juxtaposed along the X direction, and the sidewalls of the thin gate oxide layer 106a and the thick gate oxide layer 106b are in direct contact. Wherein, the composition materials of the thin gate oxide layer 106a and the thick gate oxide layer 106b may be the same.

Here, the thin gate oxide is located between the thick gate oxide and the source, and the thick gate oxide is located between the drain and the thin gate oxide.

Here, the thin gate oxide layer and the thick gate oxide layer may have the same width along the X direction, and/or, the thin gate oxide layer and the thick gate oxide layer may have the same length along the Y direction.

Here, the orthographic projection areas of the thin gate oxide layer and the thick gate oxide layer on the substrate may be equal.

Here, the thickness of the thin gate oxide layer along the Z direction is smaller than the thickness of the thick gate oxide layer along the Z direction. The thin gate oxide layer and the thick gate oxide layer shown in FIG. 3 can be made of the same material, and there is no contact interface between the thin gate oxide layer and the thick gate oxide layer.

Here, the gate oxide layer includes a thin gate oxide layer and a thick gate oxide layer, and the thin gate oxide layer breaks down at high voltage, creating a conductive channel connecting the gate and channel regions (ie, between the source and drain ); while the thick gate oxide can withstand high voltages without damage at programming voltages.

For the antifuse cell structure shown in Figures 1 to 3 above, the orthographic projection areas of the source and drain on the substrate are equal, the gate oxide layer is located on the substrate and between the source and drain, and the thin gate oxide layer and thick gate oxide have equal orthographic areas on the substrate. In this way, the area of the active region of the antifuse unit structure is larger, and the area of the antifuse unit structure is larger, and the antifuse unit structure needs to be further improved.

In view of this, embodiments of the present disclosure provide an antifuse device and a manufacturing method thereof.

The structure of the anti-fuse unit provided by another embodiment of the present disclosure will be described in detail below with reference to FIG. 4 , FIG. 5 , FIG. 6 and FIG. 7 . Here, the antifuse unit provided by another embodiment of the present disclosure is a 1T antifuse unit structure.

It should be noted that the first direction is the X direction, the second direction is the Y direction, and both the first direction and the second direction are parallel to the substrate surface; the third direction is the Z direction, and the third direction is perpendicular to the substrate surface. Wherein, the first direction and the second direction may be perpendicular to each other, so that the first direction, the second direction and the third direction are perpendicular to each other.

As shown in FIG. 4, FIG. 5, FIG. 6 and FIG. 7, the antifuse device includes: an active region 202 (ie, a second doped region 203 and a first doped region 204) disposed in a substrate 201; A gate oxide layer 206 located on the substrate 201, the gate oxide layer 206 includes a first gate oxide layer 206a and a second gate oxide layer 206b adjacently arranged along a first direction (ie, the X direction), and the second gate oxide layer 206b is arranged along the The length of the second direction (ie, Y direction) is greater than the length of the first gate oxide layer 206a along the second direction (ie, Y direction); the second gate oxide layer 206b includes The first part between the impurity regions 203 and the second part between the first doped region 204 and the first gate oxide layer 206a; the thickness of the first gate oxide layer 206a along the third direction (ie, the Z direction) is less than The thickness of the second gate oxide layer 206b along the third direction (ie, the Z direction); the gate electrode 207 on the gate oxide layer 206 . The dashed-line boxes in FIG. 4 and FIG. 5 indicate the active region 202 , and the solid-line boxes in FIG. 4 and FIG. 5 indicate the antifuse unit.

It should be noted that, in order to illustrate the positional relationship between the first gate oxide layer 206a and the second gate oxide layer 206b, FIG. 4 and FIG. 5 illustrate that the filling patterns of the first gate oxide layer 206a and the second gate oxide layer 206b are different. , this does not mean that the composition materials of the first gate oxide layer 206a and the second gate oxide layer 206b are different, and the first gate oxide layer 206a and the second gate oxide layer 206b can still be made of the same material. FIG. 6 shows that the composition materials of the first gate oxide layer 206 a and the second gate oxide layer 206 b are the same.

In addition, in order to illustrate the positional relationship between the first gate oxide layer 206a and the second gate oxide layer 206b, to prevent the gate 207 from covering the first gate oxide layer 206a and the second gate oxide layer 206b, FIG. 4 and FIG. 5 can be seen A perspective view of the first gate oxide layer 206a and the second gate oxide layer 206b is observed through the gate 207, that is, the first gate oxide layer 206a and the second gate oxide layer 206b cover the gate 207, which does not represent the actual In application, the first gate oxide layer 206 a and the second gate oxide layer 206 b are located on the gate 207 .

Here, the formation of the P well region 205 , the second doped region 203 and the first doped region 204 in the substrate 201 can all use an ion implantation process. The embodiments of the present disclosure do not specifically limit the doping types of the first doping region and the second doping region, for example, the first doping region and the second doping region may be N-type doping.

In some embodiments, the first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a source region.

Here, the first doped region may be a drain region, and the second doped region may be a source region, so that the first part of the second gate oxide layer is located between the source region and the drain region, and the second gate oxide layer The second portion is located between the first gate oxide layer and the drain region. Here, the first doped region is the source region, and the second doped region is the drain region. In this way, the first part of the second gate oxide layer is located between the source region and the drain region, and the first part of the second gate oxide layer is located between the source region and the drain region. The second part is located between the source region and the first gate oxide layer.

In the embodiment of the present disclosure, the substrate may be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (such as is a gallium nitride (GaN) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or known in the art Other semiconductor materials can also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, and the like.

In some embodiments, the orthographic area of the second doped region on the substrate is smaller than the orthographic area of the first doped region on the substrate.

Here, as shown in FIG. 5 , the length of the orthographic projection of the second doped region 203 on the substrate along the Y direction is between the length _L2 of the second gate oxide layer and the length _L1 of the first gate oxide layer along the Y direction. Poor, that is (L ₂ -L ₁ ); the width of the orthographic projection of the second doped region 203 on the substrate along the X direction is the width of the first gate oxide layer along the X direction, that is, W ₁ ; the second doped region The orthographic area of 203 on the substrate is (L ₂ −L ₁ )*W ₁ . The length of the orthographic projection of the first doped region 204 on the substrate along the Y direction is the length of the second gate oxide layer along the Y direction, namely _L2 ; the orthographic projection of the first doped region 204 on the substrate is along the X direction The width is W ₃ ; the orthographic area of the first doped region 204 on the substrate is L ₂ *W ₃ . By reducing the area of the orthographic projection of the second doped region on the substrate, the area of the orthographic projection of the active region on the substrate can be reduced, which is conducive to reducing the area of the antifuse unit, thereby achieving higher storage capacity. density.

In an embodiment of the present disclosure, the gate oxide layer is located on the substrate, and the gate oxide layer includes a first gate oxide layer and a second gate oxide layer adjacently arranged along the X direction; the length L of the second gate oxide layer along the Y direction _is greater than The length L ₁ of the first gate oxide layer along the Y direction.

In an embodiment of the present disclosure, the width W ₂ of the second gate oxide layer along the X direction may be the same as the width W ₁ of the first gate oxide layer along the X direction, that is, W ₁ =W ₂ .

Here, the area of the first gate oxide layer is L ₁ *W ₁ , the area of the second gate oxide layer is L ₂ *W ₂ , and the area of the first gate oxide layer is smaller than the area of the second gate oxide layer. Reducing the length of the first gate oxide layer can reduce the area of the first gate oxide layer, which is beneficial to reduce the area of the antifuse unit, thereby achieving higher storage density.

In the embodiments of the present disclosure, the material of the gate oxide layer may be, for example, silicon dioxide.

Here, the bottom surface of the gate oxide layer (i.e., the first gate oxide layer and the second gate oxide layer) is in direct contact with the substrate; adjacently disposed along the X direction means that the first gate oxide layer and the second gate oxide layer are arranged along the X direction. The directions are arranged side by side, and the sidewalls of the first gate oxide layer and the second gate oxide layer are in direct contact. The first gate oxide layer and the second gate oxide layer shown in FIG. 6 can be made of the same material, and there is no contact interface between the first gate oxide layer and the second gate oxide layer.

Here, the thickness of the first gate oxide layer along the Z direction is smaller than the thickness of the second gate oxide layer along the Z direction. The first gate oxide layer is a thin gate oxide layer, and the second gate oxide layer is a thick gate oxide layer. Embodiments of the present disclosure do not specifically limit the specific thickness ranges of the first gate oxide layer and the second gate oxide layer, as long as the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer.

As shown in FIG. 5 , the first gate oxide layer 206a includes two sidewalls parallel to the X direction and oppositely disposed, and two sidewalls parallel to the Y direction oppositely disposed; the second gate oxide layer 206b also includes Two side walls opposite to each other in the X direction, and two side walls parallel to the Y direction and opposite to each other. The length _L1 of the first gate oxide layer 206a along the Y direction refers to the length of the sidewall parallel to the Y direction, and the length _L2 of the second gate oxide layer 206b along the Y direction refers to the length of the sidewall parallel to the Y direction. length. The sidewalls of the first gate oxide layer 206a parallel to the Y direction are in direct contact with the sidewalls of the second gate oxide layer 206b parallel to the Y direction. The lengths are different, and part of the sidewall of the second gate oxide layer 206b is still exposed at this time, and the length of the exposed part of the sidewall is (L ₂ −L ₁ ).

In an embodiment of the present disclosure, the second gate oxide layer may include a first portion and a second portion along the Y direction, the first portion of the second gate oxide layer is located between the first doped region and the second doped region, and the second gate oxide layer A second portion of the layer is located between the first doped region and the first gate oxide layer.

Here, the first doped region is set in the substrate on the side of the second gate oxide layer away from the first gate oxide layer, and the second doped region is set in the substrate on the side of the second gate oxide layer close to the first gate oxide layer. a doped region, or a second doped region is provided in the substrate on the side of the first part of the second gate oxide layer away from the first doped region. The length of the orthographic projection of the second doped region on the substrate along the Y direction (ie (L ₂ -L ₁ )) is smaller than the length of the orthographic projection of the first doped region on the substrate along the Y direction (ie L ₂ ) , the orthographic area of the second doped region on the substrate is smaller than the orthographic area of the first doped region on the substrate.

FIG. 6 is a schematic cross-sectional structure diagram of the anti-fuse unit in FIG. 5 along line BB, and FIG. 7 is a schematic cross-sectional structural diagram of the anti-fuse unit in FIG. 5 along line CC. FIG. 7 schematically shows the cross-sectional structure of the first part of the second gate oxide layer 206 b, and the first part of the second gate oxide layer 206 b is located between the second doped region 203 and the first doped region 204 . FIG. 6 schematically shows a cross-sectional structure of a second portion of the second gate oxide layer 206b, and the second portion of the second gate oxide layer 206b is located between the first doped region 204 and the first gate oxide layer 206a.

Here, the area of the first gate oxide layer is reduced, and the area of the second doped region is reduced, and the first doped region, the second doped region, the first gate oxide layer and the second gate oxide layer are reasonably adjusted The positional relationship between them improves the structure of the anti-fuse device, so that in the plan layout, the first gate oxide layer and the second doped region are arranged side by side along the Y direction, thereby reducing the area of the anti-fuse device and further improving the anti-fuse device. Storage density of fuse devices.

In some embodiments, the gate covers the gate oxide layer (ie, the first gate oxide layer and the second gate oxide layer), and the orthographic projection of the gate on the substrate is L-shaped. Here, considering that the thicknesses of the first gate oxide layer and the second gate oxide layer are different along the Z direction, the thicknesses of the part of the gate located on the first gate oxide layer and the part of the gate located on the second gate oxide layer along the Z direction Can be the same, therefore, the surface of the gate away from the substrate is not flat. More specifically, the gate surface on the first gate oxide layer is lower than the gate surface on the second gate oxide layer.

In the embodiment of the present disclosure, the material of the gate may include but not limited to metal material and polysilicon. In this embodiment, since the formation process of the active region, the gate oxide layer and the gate is the same as the process for forming the active region, the gate oxide layer and the gate of the MOS transistor in the prior art, it is compatible with the existing process and will not Add additional process costs.

In some embodiments, the first portion of the second gate oxide layer and the first gate oxide layer are respectively located on adjacent two sides of the second doped region.

In some embodiments, the sum of the length of the orthographic projection of the second doped region 203 on the substrate along the Y direction and the length of the first gate oxide layer 206a along the Y direction is equal to the length of the second gate oxide layer 206b along the Y direction .

Here, the length of the first gate oxide layer along the Y direction is reduced, and the length of the orthographic projection of the second doped region on the substrate along the Y direction is reduced, and the first doped region and the second doped region are reasonably adjusted. region, the first gate oxide layer and the second gate oxide layer, so that the sum of the length of the orthographic projection of the second doped region on the substrate along the Y direction and the length of the first gate oxide layer along the Y direction Equal to the length of the second gate oxide layer along the Y direction, the structure of the antifuse device is improved, thereby reducing the area of the antifuse device, and further increasing the storage density of the antifuse device.

In some embodiments, the sum of the orthographic projection areas of the second doped region and the first gate oxide layer on the substrate is equal to the orthographic projection area of the second gate oxide layer on the substrate.

Here, the area of the first gate oxide layer is reduced, and the area of the orthographic projection of the second doped region on the substrate is reduced, the length of the first gate oxide layer along the Y direction and the area of the second doped region on the substrate The sum of the lengths of the orthographic projection along the Y direction is equal to the length of the second gate oxide layer along the Y direction, and the width of the first gate oxide layer along the X direction is the same as the width of the second gate oxide layer along the X direction. Thus, the second doped The sum of the area of the orthographic projection of the region and the first gate oxide layer on the substrate is equal to the area of the orthographic projection of the second gate oxide layer on the substrate, which effectively reduces the area of the antifuse device, thereby enabling higher storage density.

As shown in FIGS. 6 and 7 , the antifuse device further includes: an isolation layer 208 covering the sidewalls of the second gate oxide layer 206b close to the first doped region 204 and close to the second doped region 203 , the first gate oxide The layer 206 a is away from the sidewall of the first doped region 204 and the gate 207 is close to the sidewall of the first doped region 204 and away from the sidewall of the first doped region 204 .

In the embodiments of the present disclosure, the material of the isolation layer includes but is not limited to silicon dioxide.

As shown in FIG. 5 , the antifuse device further includes: a bit line contact pad 210 electrically connected to the first doped region 204 . Here, two adjacent antifuse units share the same bit line contact pad.

As shown in Figure 5, the antifuse device also includes: a word line (not shown in the figure), the word line is connected to the gate 207; a bit line (not shown in the figure), the bit line and the first doped region 204 connection, specifically, the bit line is electrically connected to the first doped region 204 through the bit line contact pad 210 . Here, the word lines extend along the Y direction, and the Y direction is the word line direction; the bit lines extend along the X direction, and the X direction is the bit line direction.

Here, the bit line may be connected to the first doped region or the second doped region. In a specific example, the first doped region is a drain region, and the bit line is electrically connected to the drain region through a bit line contact pad.

Here, the word line read current applied to the gate may be sensed through the channel of the antifuse memory cell through the bit line connected to the drain.

As shown in FIG. 6 , the antifuse device further includes: a silicide layer 209 , which can be located between the first doped region 204 and the bit line contact pad 210 for reducing contact resistance. Here, the silicide layer may be located between any metal and semiconductor for reducing contact resistance between metal and semiconductor.

In an embodiment of the present disclosure, the antifuse device may be a single antifuse memory unit, that is, the antifuse device is a single antifuse transistor; the antifuse device may also be an antifuse array, that is, the antifuse device It includes a plurality of antifuse transistors arranged in an array.

In an embodiment of the present disclosure, the antifuse device includes a first gate oxide layer (that is, a thin gate oxide layer) and a second gate oxide layer (that is, a thick gate oxide layer), and gate oxide layers with different thicknesses are made into a transistor ; Among them, the first gate oxide layer breaks down under high voltage, and a conductive path is generated to connect the gate and the channel region, which can be used as a storage part; the second gate oxide layer can withstand high voltage, and no shock will occur under the programming voltage It can be used as an input/output (Input/Output, I/O) control part.

If a voltage lower than the breakdown voltage is applied to the gate, the first gate oxide layer is not broken down, no current is detected on the bit line, the device is equivalent to a capacitor, and the data read on the bit line is "0"; If a programming voltage is applied to the gate, the first gate oxide layer is broken down, the circuit is turned on, and data storage is realized. The reading process of the anti-fuse device is as follows: if the first gate oxide layer in the anti-fuse device is not broken down, the leakage current through the anti-fuse memory cell that is not broken down is small (that is, nanoampere level), The output terminal of the current comparator is in a low level state; if the first gate oxide layer in the antifuse device has been broken down, when a read voltage is applied to the gate, a current is generated between the word line and the bit line, and the current comparator The output of the device is in a high state.

In the embodiment of the present disclosure, the area of the first gate oxide layer is reduced, the area of the second doped region (that is, the source region or the drain region) is reduced, and the second doped region and the first gate oxide are recombined. The positional relationship between the layers improves the structure of the antifuse memory unit, so that the area of the antifuse memory unit is reduced to 0.8 times of the original, thereby achieving higher storage density.

In the embodiment of the present disclosure, the orthographic projection of the gate on the substrate is adjusted to be L-shaped, and the area of the source is moved and reduced to reduce the area of the active region, so that the area of the chip is reduced to about 2/3 of the original, Increase the chip density, further increase the storage capacity, so as to achieve higher storage density.

An embodiment of the present disclosure also provides a manufacturing method of an antifuse device, the manufacturing method including:

Step S801: providing a substrate;

Step S802: forming a gate oxide layer on the substrate; the gate oxide layer includes a first gate oxide layer and a second gate oxide layer adjacently arranged along the first direction, and the length of the second gate oxide layer along the second direction is longer than that of the first gate oxide layer. The length of the oxide layer along the second direction, wherein the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer includes a first part and a second part in contact with the first gate oxide layer along the second direction ; The thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the substrate surface;

Step S803: forming a gate on the gate oxide layer;

Step S804: forming a first doped region in the substrate on the side of the second gate oxide layer away from the first gate oxide layer, and forming a first doped region in the substrate on the side of the second gate oxide layer far away from the first doped region A second doped region is formed therein.

The steps of forming the first gate oxide layer and the second gate oxide layer will be described in detail below with reference to FIG. 9 .

As shown in FIG. 9( a ), a first oxide layer 304 is formed on the substrate, more specifically, the first oxide layer 304 is formed above the channel region 301 . As shown in Figure 9(b), the channel region includes a first gate oxide region 302 and a second gate oxide region 303, the first oxide layer 304 is removed from the first gate oxide region 302, and only the The first oxide layer 304 of the second gate oxide region 303 . As shown in FIG. 9(c), a second oxide layer is again formed over the channel region. That is to say, the second oxide layer 305 located in the first gate oxide region 302 forms the first gate oxide layer, and the remaining first oxide layer 304 and the second oxide layer located in the second gate oxide region 303 Layers 305 collectively form a second gate oxide layer.

Embodiments of the present disclosure may use processes including but not limited to thermal oxide growth to form the first gate oxide layer and the second gate oxide layer. The embodiment of the present disclosure makes no special limitation on the process of forming the first gate oxide layer and the second gate oxide layer.

In some embodiments, the first portion of the second gate oxide layer and the first gate oxide layer are respectively located on adjacent two sides of the second doped region.

In some embodiments, the orthographic projection of the gate on the substrate is L-shaped.

In some embodiments, the orthographic area of the second doped region on the substrate is smaller than the orthographic area of the first doped region on the substrate.

In some embodiments, the sum of the length of the orthographic projection of the second doped region on the substrate along the second direction and the length of the first gate oxide layer along the second direction is equal to the length of the second gate oxide layer along the second direction on the length.

In some embodiments, the sum of the orthographic projection areas of the second doped region and the first gate oxide layer on the substrate is equal to the orthographic projection area of the second gate oxide layer on the substrate.

In some embodiments, the above manufacturing method further includes: forming an isolation layer, the isolation layer covers the sidewalls of the second gate oxide layer close to the first doped region and the sidewalls close to the second doped region, the first gate oxide layer is far away from the first doped region, The sidewalls of the impurity region and the sidewalls of the gate close to the first doped region and away from the first doped region.

In some embodiments, the above manufacturing method further includes: forming a bit line contact pad, and the bit line contact pad is electrically connected to the first doped region or the second doped region.

In some embodiments, the above manufacturing method further includes: forming a word line, connecting the word line to the gate; forming a bit line, connecting the bit line to the first doped region or the second doped region.

In some embodiments, the above-mentioned first doped region is a source region, and the second doped region is a drain region; or, the first doped region is a drain region, and the second doped region is a source region.

Embodiments of the present disclosure provide an antifuse device and a manufacturing method thereof. The antifuse device includes: a first doped region and a second doped region arranged in the substrate; a gate oxide layer on the substrate, the gate oxide layer includes A first gate oxide layer and a second gate oxide layer, the length of the second gate oxide layer along the second direction is greater than the length of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the substrate surface; the second gate oxide layer includes a first portion located between the first doped region and the second doped region and a portion located between the first doped region region and the second portion between the first gate oxide layer; the thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the The third direction is a direction perpendicular to the surface of the substrate; the gate on the gate oxide layer. In the embodiment of the present disclosure, by reducing the length of the first gate oxide layer, the length of the first gate oxide layer is smaller than the length of the second gate oxide layer; The first doped region is arranged in the bottom, and the second doped region is arranged in the substrate on the side of the first part of the second gate oxide layer away from the first doped region; rationally adjust the first doped region, the second doped region The positional relationship between the impurity region, the first gate oxide layer, the second gate oxide layer and the gate improves the structure of the antifuse device, thereby reducing the area of the antifuse device and further increasing the storage density of the antifuse device .

It should be understood that reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of the processes should be determined by their functions and internal logic, rather than by the embodiments of the present disclosure. The implementation process constitutes any limitation. The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.

The above is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. Under the inventive concept of the present disclosure, the equivalent structural transformation made by using the contents of the present disclosure and the accompanying drawings, or direct/indirect application All other relevant technical fields are included in the patent protection scope of the present disclosure.

Claims (16)

1. An antifuse device, the antifuse device comprising:

the first doped region and the second doped region are arranged in the substrate;

the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer which are arranged in close proximity along a first direction, and the length of the second gate oxide layer along a second direction is larger than that of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the surface of the substrate; the second gate oxide layer includes a first portion between the first doped region and the second doped region and a second portion between the first doped region and the first gate oxide layer; the thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate;

and a gate electrode positioned on the gate oxide layer.

2. The antifuse device of claim 1, wherein the first portion of the second gate oxide and the first gate oxide are located on adjacent sides of the second doped region, respectively.

3. The antifuse device of claim 1, wherein an orthographic projection of the gate on the substrate is L-shaped.

4. The antifuse device of claim 1, wherein an orthographic projected area of the second doped region on the substrate is smaller than an orthographic projected area of the first doped region on the substrate.

5. The antifuse device of claim 1, wherein a sum of a length of the orthographic projection of the second doped region on the substrate along the second direction and a length of the first gate oxide layer along the second direction is equal to a length of the second gate oxide layer along the second direction.

6. The antifuse device of claim 1, wherein a sum of orthographic projected areas of the second doped region and the first gate oxide layer on the substrate is equal to orthographic projected areas of the second gate oxide layer on the substrate.

7. The antifuse device of claim 1, further comprising:

a word line connected to the gate electrode;

and the bit line is connected with the first doped region or the second doped region.

8. The antifuse device of claim 1, wherein the fuse element is formed of a metal,

the first doped region is a source region, and the second doped region is a drain region; or alternatively, the first and second heat exchangers may be,

the first doped region is a drain region and the second doped region is a source region.

9. A method of manufacturing an antifuse device, the method comprising:

providing a substrate;

forming a gate oxide layer on the substrate; the gate oxide layer comprises a first gate oxide layer and a second gate oxide layer which are arranged in close proximity along a first direction, and the length of the second gate oxide layer along a second direction is larger than that of the first gate oxide layer along the second direction, wherein the first direction and the second direction are parallel to the surface of the substrate; the second gate oxide layer includes a first portion and a second portion in contact with the first gate oxide layer along the second direction; the thickness of the first gate oxide layer along the third direction is smaller than the thickness of the second gate oxide layer along the third direction, wherein the third direction is a direction perpendicular to the surface of the substrate;

forming a gate electrode on the gate oxide layer;

a first doped region is formed in the substrate on the side of the second gate oxide layer away from the first gate oxide layer, and a second doped region is formed in the substrate on the side of the first portion of the second gate oxide layer away from the first doped region.

10. The method of manufacturing an antifuse device of claim 9, wherein the first portion of the second gate oxide and the first gate oxide are located on adjacent sides of the second doped region, respectively.

11. The method of manufacturing an antifuse device of claim 9, wherein an orthographic projection of the gate on the substrate is L-shaped.

12. The method of manufacturing an antifuse device of claim 9, wherein an orthographic projection area of the second doped region on the substrate is smaller than an orthographic projection area of the first doped region on the substrate.

13. The method of manufacturing an antifuse device of claim 9, wherein a sum of a length of the second doped region in the second direction and a length of the first gate oxide layer in the second direction is equal to a length of the second gate oxide layer in the second direction.

14. The method of manufacturing an antifuse device of claim 9, wherein a sum of orthographic projected areas of the second doped region and the first gate oxide layer on the substrate is equal to orthographic projected areas of the second gate oxide layer on the substrate.

15. The method of manufacturing an antifuse device of claim 9, further comprising:

forming a word line, the word line being connected to the gate;

and forming a bit line, wherein the bit line is connected with the first doped region or the second doped region.

16. The method of manufacturing an antifuse device according to claim 9, wherein,

the first doped region is a source region, and the second doped region is a drain region; or alternatively, the first and second heat exchangers may be,

the first doped region is a drain region and the second doped region is a source region.

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