CN116136805A - Memory channel fault detection method and device, memory system and computer system - Google Patents

Abstract

The application discloses a memory channel fault detection method and device, a memory system and a computer system, which belong to the field of computer technology. The control device obtains the ECC error statistics information of the memory controller for the memory channel. When the number of ECC errors in the memory channel exceeds the first number threshold, the control device controls the memory controller to perform CRC transmission check on the memory channel link in the memory channel, so as to determine whether the memory channel link fails. The control device can determine whether the memory channel has frequent errors based on the memory controller's ECC error statistics for the memory channel. The control device can trigger the CRC transmission verification process of the memory channel link in the memory channel where frequent errors occur, so as to determine whether the memory channel link is faulty, and then it can be determined that the fault point in the memory channel is on the memory channel link It is also on the memory module, which improves the efficiency of fault location.

Description

Memory channel fault detection method and device, memory system and computer system

technical field

The present application relates to the field of computer technology, in particular to a memory channel fault detection method and device, a memory system and a computer system.

Background technique

The memory system includes a memory controller and a memory channel. A memory controller can control one or more memory channels. Each memory channel includes a memory channel link and one or more memory modules. Wherein, the memory channel link is a physical link, one end of the memory channel link is connected to the memory controller, and the other end is connected to one or more memory modules, so as to realize the electrical connection between the memory controller and the memory modules. The memory controller can write data to and read data from the memory modules through the memory channel link.

Because errors may occur when data is transmitted on the memory channel link or stored in the memory module, corresponding error detection and error correction functions are usually designed on the memory module and memory controller. Currently, an error checking and correction (ECC) check technology is usually used to check and correct data. The memory controller calculates the ECC code for the data transmitted to the memory module, and when writing the data to the memory module, the ECC code will be stored together with the data in the memory module. When the memory controller reads data from the memory module, it reads the stored ECC code together with it, and uses the ECC code to verify the correctness of the read data and try to correct any errors that occur.

However, the ECC verification technology can only detect data errors during the entire process of data transmission and storage, but cannot distinguish whether data errors occur during transmission or storage. Therefore, manual further investigation of the fault location in the memory channel is required. Fault location efficiency is low.

Contents of the invention

The present application provides a memory channel fault detection method and device, a memory system and a computer system, which can solve the problem of low fault location efficiency of the current memory channel.

In a first aspect, a memory channel fault detection method is provided. The method includes: controlling the device to acquire ECC error statistics information of the memory controller on the memory channel. The ECC error statistics are used to reflect the number of ECC errors that occur on the memory channel. When the number of ECC errors in the memory channel exceeds the first number threshold, the control device controls the memory controller to perform a cyclic redundancy check (cyclic redundancy check, CRC) transmission check on the memory channel link in the memory channel to determine Whether the memory channel link has failed.

In the present application, the control device can determine whether errors occur frequently in the memory channel based on the memory controller's ECC error statistics for the memory channel. If an error occurs frequently in a memory channel, the control device can trigger the CRC transmission verification process of the memory channel link in the memory channel to determine whether the memory channel link is faulty, and then can clarify the fault point in the memory channel On the memory channel link or on the memory module, there is no need to manually check the fault location in the memory channel, which improves the fault location efficiency.

Optionally, the ECC error statistics information includes the number of ECC errors that occur on the memory channel or a state indication that the number of ECC errors that occur on the memory channel exceeds a first number threshold.

Optionally, the memory controller performs a CRC transmission check on the memory channel link in the memory channel, including: the memory controller performs a CRC transmission check on the memory channel link in the direction of writing memory; and/or, the memory channel link The memory module has the ability to calculate the CRC transmission check code, and the memory controller controls the memory module to perform the CRC transmission check on the memory channel link in the direction of reading the memory.

Optionally, in response to a failure of the memory channel link, or when the duration for the memory controller to perform CRC transmission verification on the memory channel link reaches a duration threshold, the control device controls the memory controller to stop performing CRC transmission on the memory channel link check. When the number of CRC transmission check errors that occur on the memory channel link exceeds the second threshold, it can be determined that the memory channel link is faulty. Optionally, the number of CRC transmission verification errors that occur on the memory channel link is the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory, and the number of times that CRC transmission verification errors occur on the memory channel link in the direction of reading memory. The number of times or the total number of times that CRC transmission check errors occur on the memory channel link in the direction of writing memory and the direction of reading memory.

In this application, by setting the end mechanism of the memory controller for CRC transmission verification, the memory controller can stop the CRC transmission verification in time during the operation of the memory system, so as to avoid continuously reducing the performance of the memory system. While locating the fault, the performance impact on the memory system is reduced as much as possible, and the availability of the memory system is improved.

Optionally, the control device outputs the first fault detection result after determining that the memory channel link is faulty. The first fault detection result indicates that the memory channel link is faulty.

In the present application, when the memory channel fails, the control device can output the specific location of the failure point. By providing operation and maintenance personnel with more accurate alarm information, it is convenient for operation and maintenance personnel to repair faults, thereby shortening the fault recovery time and improving system availability.

Optionally, the ECC error statistics information includes memory addresses where ECC errors occur in the memory channel. The control device outputs a second fault detection result after determining that no fault occurs in the memory channel link. The second fault detection result indicates that the memory module corresponding to the memory address is faulty.

In the present application, when the memory channel fails, the control device can output the specific location of the failure point. By providing operation and maintenance personnel with more accurate alarm information, it is convenient for operation and maintenance personnel to repair faults, thereby shortening the fault recovery time and improving system availability.

Optionally, when the number of ECC errors that occur on the memory channel exceeds the first number threshold, the control device outputs a fault indication, where the fault indication is used to indicate that the memory channel is faulty. The control device controls the memory controller to perform CRC transmission verification on the memory channel link in the memory channel, including: in response to the memory channel link diagnostic command for the memory channel, the control device controls the memory controller to the memory channel link CRC transmission check.

In this application, the control device can output a fault indication, and the user decides whether to trigger the memory controller to perform CRC transmission check on the memory channel link in the memory channel.

Optionally, the memory channel link diagnosis command includes a second times threshold and/or a duration threshold, where the second times threshold is used for: when the number of CRC transmission check errors that occur on the memory channel link exceeds the second times threshold, It is determined that the memory channel link is faulty; the duration threshold is the maximum allowable duration for performing CRC transmission check on the memory channel link.

In a second aspect, a control device is provided. The control device includes a plurality of functional modules, and the plurality of functional modules interact to implement the methods in the above first aspect and various implementation manners thereof. The multiple functional modules can be implemented based on software, hardware or a combination of software and hardware, and the multiple functional modules can be combined or divided arbitrarily based on specific implementations.

In a third aspect, a control device is provided, including: a processor and a memory;

The memory is used to store a computer program, and the computer program includes program instructions;

The processor is configured to invoke the computer program to implement the methods in the above first aspect and various implementation manners thereof.

In a fourth aspect, a memory system is provided, including: a memory controller and a memory channel. The memory controller is used to perform ECC verification on the memory channel and record the number of ECC errors that occur on the memory channel. The memory controller is further configured to perform a CRC transmission check on the memory channel link in the memory channel after receiving the CRC transmission check command for the memory channel.

Optionally, the memory controller is further configured to record a status indication after the number of ECC errors occurring on the memory channel exceeds the first number threshold, and the status indication is used to indicate that the number of ECC errors occurring on the memory channel exceeds the first number threshold .

Optionally, the memory controller performs a CRC transmission check on the memory channel link in the memory channel, including: the memory controller performs a CRC transmission check on the memory channel link in a memory writing direction. And/or, the memory module in the memory channel has the ability to calculate the CRC transmission check code, and the memory controller controls the memory module to perform the CRC transmission check in the direction of reading the memory on the memory channel link.

Optionally, the memory controller is also used to record the number of times CRC transmission check errors occur in the memory channel link. The memory controller is also used to stop the memory channel link after the number of CRC transmission verification errors occurring on the memory channel link exceeds the second threshold, or after the time for performing CRC transmission verification on the memory channel link reaches the duration threshold. Perform CRC transmission check.

In this application, when the memory controller determines that the memory channel link satisfies the end condition of the CRC transmission verification, the memory controller can actively stop the CRC transmission verification of the memory channel link, so as to avoid continuously reducing the performance of the memory system and ensure Availability of the memory system.

Optionally, the memory controller is used to perform CRC transmission verification in the memory writing direction on the memory channel link. The memory module is used to record the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory, and stop when the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory exceeds the second threshold Check the CRC transmission check code received through the memory channel link.

In this application, when the memory controller performs CRC transmission verification on the memory channel link in the direction of writing memory, the number of times that the memory module can generate CRC transmission verification errors in the direction of writing memory on the memory channel link exceeds the second number of times When the threshold is exceeded, it actively stops checking the CRC transmission check code received through the memory channel link, so as to release its own memory resources in time and improve the availability of the memory system.

A fifth aspect provides a computer system, including: the control device as described in the third aspect and the memory system as described in the fourth aspect.

According to a sixth aspect, a computer-readable storage medium is provided. Instructions are stored on the computer-readable storage medium. When the instructions are executed by a processor, the above-mentioned first aspect and the methods in each implementation manner thereof are implemented.

In a seventh aspect, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method in the above first aspect and each implementation manner thereof is realized.

In an eighth aspect, a chip is provided, and the chip includes a programmable logic circuit and/or program instructions, and when the chip is running, implements the method in the above first aspect and its various implementation manners.

Description of drawings

FIG. 1 is a schematic diagram of the basic architecture of a computer system provided by an embodiment of the present application;

Fig. 2 is a schematic flow chart of a memory channel fault detection method provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of the implementation flow of the fault detection triggering process provided by the embodiment of the present application;

FIG. 4 is a schematic diagram of the implementation flow of the fault detection process provided by the embodiment of the present application;

FIG. 5 is a schematic diagram of the implementation flow of the fault detection end process provided by the embodiment of the present application;

FIG. 6 is a schematic structural diagram of a control device provided by an embodiment of the present application;

Fig. 7 is a schematic structural diagram of another control device provided by the embodiment of the present application;

Fig. 8 is a block diagram of a control device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

At present, the ECC verification technology can only detect errors during the entire process of data transmission and storage, and errors may occur when data is transmitted on the memory channel link or stored in the memory module. Since the ECC verification technology cannot distinguish whether data errors occur in the transmission process or the storage process, it can only determine the fault point in the memory channel, but cannot locate the fault location in the memory channel. When the memory system issues a fault alarm, it can only report that a certain memory channel has failed when reading and writing a certain memory module. Operation and maintenance personnel usually try to replace the corresponding memory module to troubleshoot the fault. However, if the fault point is on the memory channel link, the operation and maintenance personnel may have to replace the memory module several times to determine that the fault point is on the memory channel link instead of the memory module. It is inefficient to determine the location of the fault in the memory channel by manual investigation, which will cause a long time for fault recovery and reduce the availability of the system.

In order to determine whether the fault point in the memory channel is on the memory channel link or on the memory module, a CRC transmission check function is also designed on the memory controller and the memory module in related technologies to determine whether the fault is caused by the memory channel link Fault. The CRC transmission check usually generates a CRC transmission check code in units of a group of memory read and write burst transmissions. Each burst transfer will uninterruptedly read and write memory 8 times or 16 times in order of addresses to form a data frame. The memory controller or the memory module can generate an 8-bit CRC transmission check code for a data frame of a burst transmission, which is dedicated to verifying the correctness of this data burst transmission. The CRC transmission check code will be transmitted from the memory controller or memory module to the peer end in two additional clock cycles after the burst transmission data frame is completed. This CRC transmission check code will not be stored in the memory module, nor will it be passed out of the memory controller, and is only used to verify the correctness of the transmission process. Therefore, if the CRC transmission check fails, it can be accurately judged that the data is wrong during transmission. By adding the CRC transmission check code during the data transmission process, it can accurately determine whether the memory channel link is faulty, thereby providing more accurate alarm information for operation and maintenance personnel.

Although the CRC transmission verification technology can help accurately locate memory channel link faults, because the transmission of the CRC transmission verification code requires additional clock cycles, the time-consuming of each burst transmission after the CRC transmission verification function is enabled is higher than that without the CRC. The transmission check function is time-consuming, and the calculation of the CRC transmission check code by the memory controller or the memory module will generate additional delay, which will seriously degrade the performance of the memory system. In the current computer system, the CRC transmission verification function of the memory system is usually used as an optional function before the computer system is started, and it is up to the user to decide whether to enable it. If the user chooses to enable the CRC transmission check function, there will always be a problem of performance degradation of the memory system during the operation of the computer system. If the user chooses not to enable the CRC transmission verification function, it is still impossible to locate the fault location in the memory channel.

Based on this, the present application proposes a technical solution that combines the ECC verification technology with the CRC transmission verification technology. When the number of ECC errors that occur on a certain memory channel in the memory system exceeds the number threshold, the memory controller starts to perform CRC transmission check on the memory channel link in the memory channel. Wherein, the memory controller performs a CRC transmission check on the memory channel link in the memory channel, including: the memory controller performs a CRC transmission check on the memory channel link in the memory channel in the direction of writing memory, and/or, the memory The memory module in the channel has the ability to calculate the CRC transmission check code, and the memory controller controls the memory module in the memory channel to perform the CRC transmission check in the direction of reading the memory on the memory channel link in the memory channel. The CRC transmission check in the direction of writing memory means that when the memory system executes the write memory command, the memory controller calculates the CRC transmission check code for the transmitted data and sends it to the memory module, and the memory module transmits it based on the received CRC. The check code checks the transmission process. The CRC transmission check in the direction of reading memory means that when the memory system executes the read memory command, the memory module calculates the CRC transmission check code for the transmitted data and sends it to the memory controller, and the memory controller based on the received CRC The transmission verification code verifies the transmission process.

In this application, when ECC errors occur frequently on the memory channel, the control device triggers the CRC transmission verification process of the memory channel link in the memory channel to determine whether the memory channel link is faulty, and then it is possible to determine the error in the memory channel. Whether the fault point is on the memory channel link or the memory module, there is no need to manually check the fault location in the memory channel, which improves the fault location efficiency. In addition, the present application can provide operation and maintenance personnel with more accurate alarm information when the memory channel fails, so that the operation and maintenance personnel can perform fault repair, thereby shortening the fault recovery time and improving system availability.

In some embodiments, in the process of the memory controller performing CRC transmission verification on the memory channel link, once it is determined that the memory channel link has failed, or the memory controller performs the CRC transmission verification on the memory channel link If the time length of the verification reaches the time length threshold, the memory controller stops performing the CRC transmission verification on the memory channel link. Wherein, when the number of CRC transmission check errors occurring on a memory channel link exceeds a set number threshold, it can be determined that the memory channel link is faulty. This application sets the end mechanism for the memory controller to perform CRC transmission verification, so that the memory controller can stop the CRC transmission verification in time during the operation of the memory system, avoiding continuous degradation of the performance of the memory system, and realizing memory channel failure While positioning, the performance impact on the memory system is reduced as much as possible, and the availability of the memory system is improved.

The solution of this application will be introduced in detail below from multiple perspectives such as system, hardware device, method flow, and software device.

The solution of the present application can be applied to memory channel fault detection scenarios in various general-purpose computing scenarios and special-purpose computing scenarios. For example, it can be applied to computer systems including processors and memory, such as general servers, storage controllers, network controllers, and graphics workstations. For example, FIG. 1 is a schematic diagram of a basic architecture of a computer system provided by an embodiment of the present application. As shown in FIG. 1 , the computer system includes: a control device 11 and a memory system. The memory system is integrated on a baseboard or processor package 12 . The substrate can also be referred to as the motherboard. The memory system includes a memory controller 121 and a memory channel 122 . The memory channel 122 includes a memory channel link 122a and a memory module 122b.

The control device 11 is a computer device independent of the substrate or processor package 12 . The control device 11 is connected to the substrate or the processor package 12 through an intelligent platform management interface (intelligent platform management interface, IPMI) through a physical connection bus such as an inter-integrated circuit (I2C) bus. The outside world can indirectly control the substrate or processor package 12 by operating the control device 11 .

The control device 11 is also called a management unit (mangement unit), and may be, for example, a baseboard management controller (baseboard management controller, BMC). The control device 11 is used to monitor and record the working status of the substrate or processor package 12, including hardware health and performance status, hardware failure alarm and power supply status, etc. The control device 11 can also perform basic control operations on the substrate or the processor package 12, such as powering on and off, restarting, and querying the working status of the hardware.

The substrate or processor package 12 includes a processor and memory. Optionally, the processor includes but is not limited to a central processing unit (central processing unit, CPU), a graphics processing unit (graphic processing unit, GPU) or a neural network processor (neural network processing unit, NPU) under various architectures. one or more. Memory includes basic input and output system (basic input and output system, BIOS) read only memory (read only memory, ROM) and random access memory (random access memory, RAM). BIOS ROM is used to store BIOS programs. When the processor starts, it will read the BIOS program from the BIOS ROM and run it. The BIOS program is responsible for providing the underlying operation interface of the substrate or processor package 12 .

The processor includes or is externally connected to one or more memory controllers 121 . Each memory controller 121 is used to control one or more memory channels 122 . Each memory channel 122 includes a memory channel link 122a and one or more memory modules 122b. The memory controller 121 is a bus circuit controller for managing and planning the transmission speed between the memory and the processor. Memory access commands, addresses and data can be transmitted on the memory channel link 122a. The memory module 122b is a printed circuit board equipped with a memory integrated circuit, and the memory module 122b is usually a RAM. Optionally, each memory module 122b includes one or more memory chips. For example, the memory module 122b may be a double data rate (double data-rate, DDR) synchronous dynamic random-access memory (synchronous dynamic random-access memory, SDRAM) chip or a high-bandwidth memory (high-bandwidth memory, HBM) chip Alternatively, the memory module may also be a dual in-line memory module (dual in-line memory module, DIMM) composed of multiple memory chips.

The embodiment of the present application describes the functions supported by the memory controller and memory modules in the memory system.

The memory controller is capable of calculating ECC codes for data transferred to the memory modules. When the memory controller writes data to the memory module, the ECC code calculated for the data will be stored in the memory module together with the data. Optionally, the ECC code and the data are stored in the same memory chip. Alternatively, the data is stored in a memory chip on the memory module, and the ECC code is stored in a memory chip dedicated to storing the ECC code on the memory module. Wherein, the structure of the memory chip used to store the ECC code on the memory module and the memory chip used to store data may be the same or different.

When the memory controller reads data from the memory module, it will read the corresponding ECC code together, and use the ECC code to verify the correctness of the read data and try to correct the errors that occur. The memory controller has a set of registers that can store information about ECC errors that occur when reading data, including but not limited to the number of ECC errors that occur in each memory channel, the memory address where the ECC error occurred in the memory channel, and whether the ECC error was successfully corrected. Wherein, the memory address may be a physical address and a system address of the memory module. Optionally, the memory controller has a count register that can be accessed by the control device, and the memory controller can record the number of ECC errors that occur in each memory channel in the count register. And/or, the memory controller has a status register that can be accessed by the control device. When the number of ECC errors that occur on a certain memory channel exceeds a set threshold, the memory controller marks the state that exceeds the threshold in the corresponding status register. .

Optionally, the memory system provided in the embodiment of the present application supports CRC transmission check in the direction of writing memory and/or CRC transmission check in the direction of reading memory.

In the case where the memory system supports CRC transmission check in the write memory direction:

The memory controller has the ability to calculate the CRC transmission check code. When the memory controller executes the memory write command, it can calculate the CRC transmission check code for the data transmitted to the memory module. After the memory controller transmits the data to be saved in the memory module, it sends the CRC transmission check code to the memory module in several additional transmission cycles. Correspondingly, the memory module has a CRC transmission verification capability. When the memory module executes the write memory command, after receiving the data transmitted from the memory controller and the CRC transmission check code, the CRC transmission check code can be used to verify the correctness of the transmission process. If the verification result is wrong (that is, a CRC transmission verification error occurs), the memory module can change the level of a physical connection line, or save the verification result to the memory module and be read by the memory controller. The method of taking a certain register to notify the memory controller that an error occurred during this transmission.

In the first implementation manner, the memory module can record the number of times CRC transmission check errors occur in the direction of writing to the memory.

Optionally, the memory module has a count register that can be accessed by the memory controller, and the memory module can record in the count register the number of times CRC transmission check errors occur in the direction of writing to the memory. And/or, the memory module has a status register that can be accessed by the memory controller. When the number of CRC transmission check errors in the direction of writing to the memory exceeds a set threshold, the memory module marks the status exceeding the threshold in the status register. The memory module can notify the memory controller to read the corresponding register by changing the level of a certain physical connection line, or the memory module only passively waits for the memory controller to read the corresponding register. Optionally, when the number of CRC transmission check errors in the memory writing direction exceeds a set number threshold, the memory module can actively stop checking the received CRC transmission check code.

In the second implementation manner, the memory controller can record the number of times CRC transmission check errors occur in the direction of writing to the memory. Every time the memory module uses the CRC transmission check code to get the wrong check result, it will notify the memory controller that an error has occurred during the transmission process, and the memory controller will use the number of times the wrong check result is received as the occurrence of CRC in the direction of writing memory. The number of transmission parity errors. Optionally, the memory controller can use the counting register to record the number of times that CRC transmission verification errors occur in the direction of writing memory, or use the status register to mark whether the number of times of CRC transmission verification errors occurring in the direction of writing memory exceeds the set number of times threshold state.

The above-mentioned first implementation manner and the second implementation manner can also be used in combination, that is, both the memory module and the memory controller can record the number of CRC transmission check errors that occur in the direction of writing to the memory.

Optionally, when the memory controller determines that the number of CRC transmission check errors in the memory writing direction exceeds a set number threshold, the memory controller can actively stop calculating and transmitting the CRC transmission check code.

Optionally, by writing one or a group of commands to the memory controller to enable or disable the CRC transmission check function for the process of writing the memory, there is no need to re-initialize the memory system to make this function effective.

In the case where the memory system supports CRC transmission check in the direction of reading memory:

The memory module has the ability to calculate the CRC transmission check code. When the memory module executes the memory read command, it can calculate the CRC transmission check code for the data transmitted to the memory controller. After the memory module transmits the data read by the memory controller, it sends the CRC transmission check code to the memory controller in several additional transmission cycles. Correspondingly, the memory controller has a CRC transmission verification capability. When the memory controller executes the memory read command, after receiving the data transmitted from the memory module and the CRC transmission check code, it can use the CRC transmission check code to verify the correctness of the transmission process.

The memory controller can record the number of CRC transmission check errors in the direction of reading memory. Optionally, the memory controller has a counting register that can be accessed by the processor, and the memory controller can record in the counting register the number of times CRC transmission check errors occur in the memory reading direction. And/or, the memory controller has a status register that can be accessed by the processor. When the number of CRC transmission check errors in the direction of reading the memory exceeds a set threshold, the memory controller marks in the status register the number of times that exceeds the threshold. state. When the number of CRC transmission check errors in the direction of reading memory exceeds the set threshold, the memory controller can initiate an interrupt to notify the processor to execute the BIOS program to read the corresponding register, or just passively wait for the processor to read the corresponding register.

Optionally, when the memory controller determines that the number of CRC transmission check errors in the memory reading direction exceeds the set threshold, it can actively stop checking the received CRC transmission check code, and control the memory module to stop calculating and Transmission CRC transmission check code.

Optionally, by writing one or a group of commands to the memory controller to enable or disable the CRC transmission verification function for the process of reading the memory, the memory controller will also write the corresponding command to the memory module on the specified memory channel, Enables it to start or stop calculating and transmitting the CRC for reading memory without reinitializing the memory system for this function to take effect.

The embodiment of the present application describes the software functions that can be realized by the BIOS program. The BIOS program is responsible for providing the underlying operation interface of the substrate or processor package.

(1) The BIOS program contains a set of software interfaces. Calling this set of software interfaces can enable or disable the CRC transmission verification function of the memory controller and memory module, and query the switch status of the CRC transmission verification function. This group of software interfaces can be called repeatedly during the operation of the memory system. Calling this group of software interfaces will not interrupt the execution of other computer programs by the memory system, and there is no need to restart the memory system to make the change of the switch state of the CRC transmission verification function take effect .

(2) The BIOS program contains a set of software interfaces. Calling this set of software interfaces can read specific registers in the memory controller to query the number of ECC errors or the number of ECC errors of the specified memory module on the specified memory channel. Whether the number of times exceeds the set threshold, the memory address where the ECC error occurs, etc.

(3) The BIOS program contains a set of software interfaces. Calling this set of software interfaces can read specific registers in the memory controller and/or memory modules, so as to query the occurrence of memory writes in the specified memory channel on the specified memory module. Whether the number of times of CRC transmission verification errors or the number of times of CRC transmission verification errors in the direction of writing memory exceeds the set threshold.

(4) If the memory system supports CRC transmission verification in the direction of reading memory, the BIOS program contains a set of software interfaces, calling this set of software interfaces can read specific registers in the memory controller to query the specified memory channel is reading memory Whether the number of CRC transmission check errors in the direction or the number of CRC transmission check errors in the read memory direction exceeds the set threshold.

The embodiment of the present application describes the functions supported by the control device.

The control device can call the software interface in the above (1)-(4) provided by the BIOS program to enable or disable the CRC transmission verification function, query the switch status of the CRC transmission verification function, and read the ECC error count on the specified memory channel Or the state that the ECC error count exceeds the set threshold, reads ECC error address information, reads the CRC transmission check error count, or the state that the CRC transmission check error count exceeds the set threshold.

The control device can provide users with a user interface for viewing or diagnosing memory channel failure information, including but not limited to prompting users in the form of alarms or logs that a certain memory channel or a certain memory channel Memory channel link diagnostic commands for the channel.

FIG. 2 is a schematic flowchart of a memory channel fault detection method provided by an embodiment of the present application. The method can be applied to the control device 11 in the computer system as shown in FIG. 1 . As shown in Figure 2, the method includes:

Step 201 , acquiring ECC error statistics information of a memory controller for a memory channel.

ECC error statistics are used to reflect the number of ECC errors that occur on the memory channel. Optionally, if the memory controller controls multiple memory channels, the control device may obtain the ECC error statistics information of the memory controller for each memory channel.

Optionally, the ECC error statistics information includes the number of ECC errors that occur on the memory channel or a state indication that the number of ECC errors that occur on the memory channel exceeds a first number threshold. For example, the control device can read from a count register on the memory controller the number of times an ECC error has occurred for a memory channel, or, the control device can read from a status register on the memory controller that the number of times an ECC error has occurred for a memory channel exceeds the first Status indication of the number threshold. The value of the first number threshold is a positive integer. The size of the first number threshold may be preset in the system, or may be set or changed by the user through the control device. The embodiment of the present application does not limit the specific value of the first number threshold.

Optionally, the memory controller counts the number of ECC errors that occur on the memory channel within the time window. For example, the memory controller can always count the number of times the memory channel has experienced ECC errors in the past 5 minutes. The size of the time window may be preset in the memory controller, or may be set or changed by the user through a control device. The embodiment of the present application does not limit the specific value of the time window.

Optionally, the implementation manner for the control device to acquire the ECC error statistics information of the memory channel from the memory controller includes: the control device periodically queries the memory controller for the number of ECC errors that occur in the memory channel. Alternatively, when the number of ECC errors occurring on a certain memory channel exceeds the first threshold, the memory controller sends a status indication to the control device that the number of ECC errors occurring on the memory channel exceeds the first threshold.

Step 202: When the number of ECC errors in the memory channel exceeds the first number threshold, control the memory controller to perform CRC transmission check on the memory channel link in the memory channel to determine whether the memory channel link is faulty.

When the memory system starts running, the CRC transmission check function of the memory system is disabled. When the number of ECC errors in a memory channel exceeds the threshold of the first number, the control device will enable the CRC transmission verification function for the memory channel, that is, trigger the memory controller controlling the memory channel to check the ECC errors in the memory channel. The memory channel link performs CRC transmission verification, which can avoid the performance loss of the memory system caused by the CRC transmission verification function being turned on for a long time.

In the embodiment of the present application, the control device can determine whether errors occur frequently in the memory channel based on the memory controller's ECC error statistics for the memory channel. If an error occurs frequently in a memory channel, the control device can trigger the CRC transmission verification process of the memory channel link in the memory channel to determine whether the memory channel link is faulty, and then can clarify the fault point in the memory channel On the memory channel link or on the memory module, there is no need to manually check the fault location in the memory channel, which improves the fault location efficiency.

When the number of ECC errors that occur on the memory channel exceeds the first number threshold, the control device may determine that the memory channel is faulty. Optionally, when the number of times of ECC errors occurring on the memory channel exceeds the first number threshold, the control device may also output a fault indication, which is used to indicate that the memory channel is faulty. The implementation of step 202 includes: the control device controls the memory controller to perform CRC transmission check on the memory channel link in the memory channel in response to the memory channel link diagnosis command for the memory channel. Wherein, the control device outputting the fault indication may output the fault indication through a user interface, so as to display fault information on a corresponding display device for operation and maintenance personnel to view. After knowing that a memory channel is faulty, the operation and maintenance personnel can choose to trigger a memory channel link diagnosis command for the memory channel.

In the embodiment of the present application, after the control device determines that a certain memory channel fails, it can directly trigger the memory controller to perform CRC transmission verification on the memory channel link in the memory channel, or it can also output a fault indication, and the user can Determine whether to trigger the memory controller to perform CRC transmission check on the memory channel link in the memory channel.

Optionally, the memory channel link diagnosis command includes a second times threshold and/or a duration threshold. Wherein, the second times threshold is used to determine that the memory channel link is faulty when the number of CRC transmission check errors occurring on the memory channel link exceeds the second times threshold. The duration threshold is the maximum allowable duration for performing CRC transmission check on the memory channel link. Both the second times threshold and the duration threshold can be used as conditions for judging whether to end the CRC transmission check. When the number of CRC transmission check errors that occur on the memory channel link exceeds the second threshold, that is, when the memory channel link fails, it can be determined that the memory channel link satisfies the CRC transmission check end condition. When the duration for the memory controller to perform the CRC transmission check on the memory channel link reaches a duration threshold, it may also be determined that the memory channel link satisfies the end condition of the CRC transmission check. That is, the memory channel link satisfies the end condition of the CRC transmission verification, including: the memory channel link fails, or the duration for the memory controller to perform the CRC transmission verification on the memory channel link reaches a duration threshold.

Optionally, the second count threshold and duration threshold can be preset in the system, or can also be set or changed by the user through the control device, for example, carried in the memory channel link diagnosis command, the embodiment of the present application Specific values of the second count threshold and duration threshold are not limited.

In the embodiment of the present application, by setting the end mechanism of the memory controller to perform CRC transmission verification, the memory controller can stop the CRC transmission verification in time during the operation of the memory system, so as to avoid continuously reducing the performance of the memory system. While locating the fault, the performance impact on the memory system is reduced as much as possible, and the availability of the memory system is improved.

In one implementation manner, when the control device determines that the memory channel link satisfies the CRC transmission verification termination condition, the control device controls the memory controller to stop performing the CRC transmission verification on the memory channel link. That is, in response to a failure of the memory channel link, or when the duration for the memory controller to perform CRC transmission verification on the memory channel link reaches a duration threshold, the control device controls the memory controller to stop performing CRC transmission on the memory channel link check.

After the memory controller starts to perform CRC transmission verification on the memory channel link, the control device can obtain the CRC error statistics information of the memory controller and/or memory module on the memory channel link in real time or periodically until the memory channel link is determined to be A fault occurs or the duration of the CRC transmission check for the memory channel link reaches the duration threshold. Optionally, the CRC error statistics information includes the number of CRC transmission check errors that occur on the memory channel link or a status indication that the number of CRC transmission check errors that occur on the memory channel link exceeds a second threshold. If in step 202, only the memory controller performs CRC transmission verification on the memory channel link in the direction of writing to memory, the number of times that CRC transmission verification errors occur on the memory channel link is CRC occurred on the memory channel link in the direction of writing to memory The number of transmission parity errors. If in step 202, only the memory module performs CRC transmission verification on the memory channel link in the memory channel in the direction of reading memory, the number of times that the memory channel link has CRC transmission verification errors is the memory channel link in the direction of reading memory The number of times CRC transmission checksum errors occurred. If in step 202, the memory controller performs the CRC transmission verification of the memory channel link in the direction of writing memory, and the memory module performs the CRC transmission verification of the memory channel link in the memory channel in the direction of reading memory, then the memory The number of CRC transmission check errors that occur on the channel link may be the total number of CRC transmission check errors that occur on the memory channel link in the direction of writing memory and the direction of reading memory.

Optionally, the method for the control device to acquire CRC error statistics of the memory channel link by the memory controller includes: the control device queries the memory controller for the number of times CRC transmission check errors occur on the memory channel link. Or, when the number of CRC transmission check errors that occur on the memory channel link exceeds the second threshold, the memory controller sends a status to the control device that the number of CRC transmission check errors that occur on the memory channel link exceeds the second threshold instruct.

In another implementation manner, when the memory controller determines that the memory channel link meets the CRC transmission verification end condition, the memory controller actively stops performing the CRC transmission verification on the memory channel link. In this implementation manner, the control device can determine whether the memory channel link fails according to the status information of the CRC transmission check performed by the memory controller and/or the memory module. If the status information of the memory controller in the memory system with the CRC transmission verification function in the direction of writing memory is enabled indicates that the CRC transmission verification function has been stopped, or if the memory system in the memory system with the CRC transmission verification function in the direction of reading memory is enabled If the state information of the memory module indicates that the CRC transmission check has stopped, the control device can determine that the memory channel link has failed.

The memory controller pre-stores the second count threshold and duration threshold. The memory controller can record the number of CRC transmission check errors on the memory channel link, and the number of CRC transmission check errors on the memory channel link exceeds the second The number of times threshold, or, after the duration of performing CRC transmission verification on the memory channel link reaches the duration threshold, actively stop performing the CRC transmission verification on the memory channel link. Wherein, the memory controller performs transmission verification on the memory channel link, including: the memory controller performs CRC transmission verification on the memory channel link in the direction of writing memory, and/or controls the memory module to perform memory read on the memory channel link CRC transmission check for the direction. Correspondingly, the memory controller stops performing transmission verification on the memory channel link, including: the memory controller stops performing CRC transmission verification on the memory channel link in the direction of writing memory, and/or controls the memory module to stop performing verification on the memory channel link The way to perform CRC transmission check in the direction of reading memory.

In the first case, the memory controller is used to perform CRC transmission verification in the memory writing direction on the memory channel link. The memory module can record the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory, and when the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing to memory exceeds the second threshold, stop checking The CRC transmission check code received by the memory channel link is used for verification. In addition, the memory module may also notify the memory controller to finish calculating and transmitting the CRC transmission check code.

In the second case, the memory module is used to perform CRC transmission verification on the memory channel link in the direction of reading the memory. The memory controller can record the number of CRC transmission check errors that occur on the memory channel link in the direction of reading memory, and notify the memory module when the number of CRC transmission check errors that occur on the memory channel link in the direction of reading memory exceeds the second threshold End the calculation and transmission of the CRC transmission check code, and stop checking the CRC transmission check code received through the memory channel link.

In the third case, the memory controller is used to perform CRC transmission verification on the memory channel link in the direction of writing memory, and the memory module is used to perform CRC transmission verification on the memory channel link in the direction of reading memory. The memory controller can record the total number of CRC transmission check errors in the direction of writing memory and reading the memory of the memory channel link, and record the number of CRC transmission check errors in the direction of writing memory and reading memory of the memory channel link. When the total number of times exceeds the second threshold, stop calculating and transmitting the CRC transmission check code, stop verifying the CRC transmission check code received through the memory channel link, and notify the memory module to end the calculation and transmission of the CRC transmission check code. check code.

In the above third case, by counting the total number of CRC transmission check errors in the memory channel link in the direction of writing memory and reading the direction of memory, it is compared with the second threshold. Compared with the first case and the second case In this case, it can be judged faster that the memory channel link is faulty, and the fault detection efficiency is higher.

Optionally, after determining that the memory channel link is faulty, the control device may output a first fault detection result, where the first fault detection result indicates that the memory channel link is faulty. Alternatively, when the ECC error statistics information includes memory addresses where ECC errors occur in the memory channel, the control device may output a second fault detection result after determining that the memory channel link is not faulty, and the second fault detection result indicates that the memory channel The memory module corresponding to the address has failed.

In the embodiment of the present application, when the memory channel fails, the control device can output the specific location of the failure point. By providing operation and maintenance personnel with more accurate alarm information, it is convenient for operation and maintenance personnel to repair faults, thereby shortening the fault recovery time and improving system availability.

The memory channel fault detection method provided in the embodiment of the present application mainly includes a fault detection trigger process, a fault detection process, and a fault detection end process. The following embodiments of the present application illustrate the implementation flows of these three processes based on the interaction between the control device and the BIOS program. In the computer system shown in FIG. 1, the control device may be the control device 11, and the BIOS program may be a computer program stored in the BIOS ROM.

Fig. 3 is a schematic diagram of the implementation flow of the fault detection triggering process provided by the embodiment of the present application. As shown in Figure 3, the implementation process includes:

Step 301 , the control device sends a setting command to the BIOS program, and the setting command is used to instruct to set the ECC error counting time window and the ECC counting threshold corresponding to the memory channel.

Wherein, the ECC count threshold is the above-mentioned first count threshold. The ECC error counting time windows and ECC counting thresholds corresponding to different memory channels may be the same or different.

Step 302, the BIOS program sets the ECC error counting time window and the ECC counting threshold corresponding to the memory channel for the memory controller.

Step 303 , the control device periodically sends a query command to the BIOS program, and the query command is used to instruct to query the ECC error statistics information of the memory channel.

The ECC error statistics include ECC error counts (that is, the number of times an ECC error occurs on a memory channel) or a status indication that the ECC error count exceeds an ECC count threshold.

Step 304, the BIOS program reads the ECC error statistics information of the memory channel from the memory controller.

Here, the ECC error statistics information of the memory controller for the memory channel refers to the ECC error statistics information of the memory controller for the memory channel within the latest ECC error counting time window.

Step 305, the BIOS program sends the ECC error statistics information of the memory channel to the control device.

Step 306, the control device judges whether the ECC error count of any memory channel exceeds the ECC count threshold. If the ECC error count of any memory channel exceeds the ECC count threshold, then use the memory channel whose ECC error count exceeds the ECC count threshold as the memory channel to be verified and perform step 307; if the ECC error count of no memory channel exceeds the ECC count threshold, Then return to step 303.

Step 307, the control device sends a CRC transmission verification command for the memory channel to be verified to the BIOS program.

Step 308, the BIOS program detects whether the memory channel to be verified is in an idle state. If the memory channel to be checked is idle, execute step 309; if the memory channel to be checked is busy, execute step 311.

After the BIOS program receives the CRC transmission verification command, if the memory channel to be verified reads and writes the memory over a preset timeout period, the BIOS program determines that the memory channel to be verified is in a busy state.

Step 309 , the BIOS program sets the memory controller to start performing CRC transmission verification on the memory channel links in the memory channels to be verified.

In step 309, the BIOS program may set the memory controller to perform CRC transmission verification in the memory writing direction on the memory channel link in the memory channel to be verified. The BIOS program can also determine whether the memory module in the memory channel to be verified has the ability to calculate the CRC transmission check code. If the memory module has the ability to calculate the CRC transmission check code, the BIOS program can also set the memory controller to write commands to the memory module, so that the memory module performs CRC transmission in the direction of reading the memory for the memory channel link in the memory channel to be verified. check.

Optionally, if the memory controller supports the automatic stop of the CRC transmission check, the BIOS program can be set to enable the automatic stop function of the CRC transmission check of the memory controller, and set the CRC count threshold in the memory controller (that is, the above-mentioned second number of times) threshold). If the memory module supports automatic stop of CRC transmission check, the BIOS program can enable the function of automatic stop of CRC transmission check of the memory module, and set the CRC count threshold in the memory module.

Step 310, the BIOS program sends a CRC transmission verification startup success notification to the control device.

The CRC transmission verification startup success notification is used to indicate that the CRC transmission verification startup for the memory channel to be verified is successful.

Step 311 , the BIOS program sends a CRC transmission verification startup failure notification to the control device.

The CRC transmission verification start failure notification is used to indicate that the CRC transmission verification for the memory channel to be verified fails to start.

Step 312, the control device judges whether the CRC transmission check for the memory channel to be checked is started successfully. If the CRC transmission verification for the memory channel to be verified is successfully started, enter the fault detection process; if the CRC transmission verification for the memory channel to be verified fails, return to step 303 .

Fig. 4 is a schematic diagram of the implementation flow of the fault detection process provided by the embodiment of the present application. In this fault detection process, the memory controller is used to perform CRC transmission verification in the direction of writing memory to the memory channel link in the memory channel to be verified, and the memory module is used to read memory from the memory channel link in the memory channel to be verified. The CRC transmission check in the direction, and both the memory controller and the memory module support the automatic stop of the CRC transmission check will be described as an example. As shown in Figure 4, the implementation process includes:

Step 401 , the control device judges whether the CRC transmission verification duration for the memory channel to be verified reaches a duration threshold. If the CRC transmission verification duration for the memory channel to be verified does not reach the duration threshold, execute step 402; if the CRC transmission verification duration for the memory channel to be verified reaches the duration threshold, enter the fault detection end process.

Step 402, the control device sends a query command to the BIOS program, where the query command is used to instruct to query the fault detection result of the memory channel link in the memory channel to be verified.

Optionally, during the CRC transmission verification process of the memory channel link in the memory channel to be verified, the control device may periodically send a query command to the BIOS program to query the fault detection result.

Step 403, the BIOS program detects whether the memory channel to be verified is in an idle state. If the memory channel to be checked is idle, execute step 404; if the memory channel to be checked is busy, execute step 408.

After the BIOS program receives the query command, if the time for reading and writing the memory of the memory channel to be verified exceeds the preset timeout period, the BIOS program determines that the memory channel to be verified is in a busy state.

Step 404 , the BIOS program detects whether the memory controller has stopped performing CRC transmission verification in the direction of writing memory for the memory channel link in the memory channel to be verified. If the memory controller has not stopped the memory channel link in the memory channel to be verified to perform CRC transmission verification in the write memory direction, then perform step 405; if the memory controller has stopped the memory channel chain in the memory channel to be verified If the CRC transmission check is performed in the direction of writing memory, step 407 is performed.

Step 405 , the BIOS program detects whether the memory module has stopped performing CRC transmission verification in the memory reading direction on the memory channel link in the memory channel to be verified. If the memory module has not stopped performing the CRC transmission verification in the direction of reading the memory for the memory channel link in the memory channel to be verified, then perform step 406; if the memory module has stopped performing the memory channel link in the memory channel to be verified For the CRC transmission check in the direction of reading the memory, go to step 407.

Optionally, the execution order of the above step 404 and step 405 can be interchanged, or the above step 404 and step 405 can also be executed at the same time, the embodiment of the present application does not limit the execution sequence of step 404 and step 405.

Step 406, the BIOS program sends a non-fault notification to the control device.

The non-failure notification is used to indicate that the memory channel link in the memory channel to be verified is not faulty.

Step 407, the BIOS program sends a fault notification to the control device.

The fault notification is used to indicate that a memory channel link in the memory channel to be verified has failed.

Step 408, the BIOS program sends a query failure notification to the control device.

The query failure notification is used to indicate that the current query failure detection result fails.

Step 409, the control device judges whether the fault detection result of the memory channel link in the memory channel to be verified is found. If no fault detection result is found, return to step 401; if the fault detection result is found, execute step 410.

Step 410, the control device judges whether a memory channel link in the memory channel to be verified is faulty. If the memory channel link fails, execute step 411; if the memory channel link does not fail, return to execute step 401.

Step 411, the control device records the memory channel link failure event in the log.

Optionally, the control device may also output memory channel link fault events for display on the user interface. In the case that both the memory controller and the memory module support the automatic stop of CRC transmission verification, if the memory channel link fails, the memory controller and the memory module will automatically stop the CRC transmission verification, and there is no need to enter the fault detection end process .

FIG. 5 is a schematic diagram of the implementation flow of the fault detection end process provided by the embodiment of the present application. As shown in Figure 5, the implementation process includes:

Step 501 , the control device sends a CRC transmission check end command for the memory channel to the BIOS program.

Optionally, when the CRC transmission verification duration for a certain memory channel reaches the duration threshold, or it is determined that a memory channel link in a certain memory channel has failed, the control device may send a CRC transmission for the memory channel to the BIOS program. CRC transmission verification end command.

Step 502, the BIOS program detects whether the memory channel is in an idle state. If the memory channel is in an idle state, execute step 503; if the memory channel is in a busy state, execute step 505.

After the BIOS program receives the CRC transmission verification end command, if the memory channel reads and writes the memory for longer than the preset timeout period, the BIOS program determines that the memory channel is in a busy state.

Step 503 , the BIOS program sets the memory controller to stop performing CRC transmission check on the memory channel link in the memory channel.

In step 503, the BIOS program may set the memory controller to stop performing CRC transmission check in the memory writing direction on the memory channel link in the memory channel. The BIOS program can also determine whether the memory module in the memory channel has the ability to calculate the CRC transmission check code. If the memory module has the ability to calculate the CRC transmission check code, the BIOS program can also set the memory controller to write commands to the memory module, so that the memory module stops performing CRC transmission verification on the memory channel link in the memory channel in the direction of reading memory. .

Step 504, the BIOS program sends a notification that the CRC transmission check is closed successfully to the control device.

The CRC transmission verification closing success notification is used to indicate that the CRC transmission verification for the memory channel is successfully closed.

Step 505, the BIOS program sends a notification of failure to close the CRC transmission check to the control device.

The notification of failure to close the CRC transmission check is used to indicate that the close of the CRC transmission check for the memory channel fails.

Step 506, the control device judges whether the CRC transmission check for the memory channel is closed successfully. If the CRC transmission check for the memory channel is successfully closed, the process ends; if the CRC transmission check for the memory channel fails, return to step 501 .

The sequence of steps in the memory channel fault detection method provided in the embodiment of the present application can be adjusted appropriately, and the steps can also be increased or decreased accordingly according to the situation. Any person familiar with the technical field within the technical scope disclosed in this application can easily think of changing methods, which should be covered within the scope of protection of this application.

To sum up, in the memory channel fault detection method provided by the embodiment of the present application, the control device can judge whether the memory channel frequently has errors based on the ECC error statistics information of the memory controller for the memory channel. If an error occurs frequently in a memory channel, the control device can trigger the CRC transmission verification process of the memory channel link in the memory channel to determine whether the memory channel link is faulty, and then can clarify the fault point in the memory channel On the memory channel link or on the memory module, there is no need to manually check the fault location in the memory channel, which improves the fault location efficiency. In addition, by setting the end mechanism for the memory controller to perform CRC transmission verification, the memory controller can stop the CRC transmission verification in time during the operation of the memory system, avoiding continuous degradation of the performance of the memory system, and locating memory channel faults At the same time, the performance impact on the memory system is reduced as much as possible, and the availability of the memory system is improved. When the memory channel fails, the control device can output the specific location of the failure point. By providing operation and maintenance personnel with more accurate alarm information, it is convenient for operation and maintenance personnel to repair faults, thereby shortening the fault recovery time and improving system availability.

Fig. 6 is a schematic structural diagram of a control device provided by an embodiment of the present application. As shown in Figure 6, the control device 600 includes:

The acquiring module 601 is configured to acquire the ECC error statistics information of the memory channel from the memory controller, and the ECC error statistics information is used to reflect the number of times of ECC errors occurring on the memory channel.

The control module 602 is configured to control the memory controller to perform a cyclic redundancy check (CRC) transmission check on the memory channel link in the memory channel when the number of ECC errors occurring on the memory channel exceeds the first number threshold, so as to determine the memory channel Whether the link is down.

Optionally, the ECC error statistics information includes the number of ECC errors that occur on the memory channel or a state indication that the number of ECC errors that occur on the memory channel exceeds a first number threshold.

Optionally, the memory controller performs a CRC transmission check on the memory channel link in the memory channel, including: the memory controller performs a CRC transmission check on the memory channel link in a memory writing direction. And/or, the memory module in the memory channel has the ability to calculate the CRC transmission check code, and the memory controller controls the memory module to perform the CRC transmission check in the direction of reading the memory on the memory channel link.

Optionally, the control module 602 is also configured to control the memory controller to stop performing CRC transmission verification on the memory channel link in response to a failure of the memory channel link, or when the memory controller performs a CRC transmission check on the memory channel link. CRC transmission check.

Optionally, as shown in FIG. 7 , the control device 600 further includes: an output module 603 .

Optionally, the output module 603 is configured to output a first fault detection result after determining that the memory channel link is faulty, where the first fault detection result indicates that the memory channel link is faulty.

Optionally, the ECC error statistics information includes memory addresses where ECC errors occur in the memory channel. The output module 603 is configured to output a second fault detection result after it is determined that the memory channel link is not faulty, and the second fault detection result indicates that the memory module corresponding to the memory address is faulty.

Optionally, the output module 603 is configured to output a fault indication when the number of times of ECC errors occurring on the memory channel exceeds a first number threshold, where the fault indication is used to indicate that the memory channel is faulty. The control module 602 is configured to control the memory controller to perform CRC transmission check on the memory channel link in response to the memory channel link diagnosis command for the memory channel.

Optionally, the memory channel link diagnosis command includes a second times threshold and/or a duration threshold, where the second times threshold is used for: when the number of CRC transmission check errors that occur on the memory channel link exceeds the second times threshold, It is determined that the memory channel link is faulty; the duration threshold is the maximum allowable duration for performing CRC transmission check on the memory channel link.

Regarding the apparatus in the foregoing embodiments, the specific manner in which each module executes operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

Fig. 8 is a block diagram of a control device provided by an embodiment of the present application. As shown in FIG. 8 , the control device 800 includes: a processor 801 and a memory 802 .

memory 802, configured to store computer programs, the computer programs including program instructions;

The processor 801 is configured to call the computer program to implement the steps performed by the control device in the above method embodiments.

Wherein, the processor 801 includes one or more processing cores, and the processor 801 executes various functional applications and data processing by running computer programs.

Memory 802 may be used to store computer programs. Optionally, the memory may store an operating system and application program units required for at least one function. The operating system may be an operating system such as a real-time operating system (Real Time eXecutive, RTX), LINUX, UNIX, WINDOWS or OS X.

There may be multiple communication interfaces 804, and the communication interface 804 is used to communicate with other storage devices or network devices. For example, in the embodiment of the present application, the communication interface 804 may be used to communicate with a substrate or a processor package.

The memory 802 and the communication interface 804 are respectively connected to the processor 801 through the communication bus 803 .

An embodiment of the present application provides a memory system, including: a memory controller and a memory channel. The memory controller is used to perform ECC verification on the memory channel and record the number of ECC errors that occur on the memory channel. The memory controller is further configured to perform a CRC transmission check on the memory channel link in the memory channel after receiving the CRC transmission check command for the memory channel. The CRC transmission check command may be triggered by the control device instructing the BIOS program.

Optionally, the memory controller is further configured to record a status indication after the number of ECC errors occurring on the memory channel exceeds the first number threshold, where the status indication is used to indicate that the number of ECC errors occurring on the memory channel exceeds the first number threshold. The memory controller may use the status register to record whether the number of times of ECC errors on the memory channel exceeds the first number threshold.

Optionally, the memory controller performs a CRC transmission check on the memory channel link in the memory channel, including: the memory controller performs a CRC transmission check on the memory channel link in a memory writing direction. And/or, the memory module in the memory channel has the ability to calculate the CRC transmission check code, and the memory controller controls the memory module to perform the CRC transmission check in the direction of reading the memory on the memory channel link.

Optionally, the memory controller is also used to record the number of times CRC transmission check errors occur in the memory channel link. The memory controller is also used to stop the memory channel link after the number of CRC transmission verification errors occurring on the memory channel link exceeds the second threshold, or after the time for performing CRC transmission verification on the memory channel link reaches the duration threshold. Perform CRC transmission check.

Optionally, the memory controller is used to perform CRC transmission verification in the memory writing direction on the memory channel link. The memory module is used to record the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory, and stop when the number of CRC transmission verification errors that occur on the memory channel link in the direction of writing memory exceeds the second threshold Check the CRC transmission check code received through the memory channel link.

The memory system provided in the embodiment of the present application can adopt a memory module conforming to the DDR4 specification (JEDEC-JESD79-4 standard specification) (hereinafter referred to as: DDR4 memory module) or a memory module conforming to the DDR5 specification (JEDEC-JESD79-5 standard specification) ( Hereinafter referred to as: DDR5 memory module). The memory module may be, for example, a register buffered dual in-line memory module (registered DIMM, RDIMM). Memory modules conforming to the DDR4 or DDR5 specification all support the realization of the technical solution of the present application. It should be noted that the memory modules that can be used in the memory system provided by the embodiments of the present application include but are not limited to memory modules conforming to DDR4 or DDR5 specifications.

The DDR4 memory module has the capability of CRC transmission verification for memory write operations, but does not have the ability to calculate CRC transmission verification codes for memory read operations. When a CRC transmission check error occurs during memory writing, the DDR4 memory module can notify the memory controller of an error by pulling down the level of the ALERT_n pin. Based on the working state of the DDR4 memory module, when the DDR4 memory module does not perform read and write operations after entering the idle state, it can accept the setting command of the mode register at any time to realize the opening and closing of the CRC transmission verification function.

The DDR5 memory module has the capability of CRC transmission verification for memory write operations, and the ability to calculate CRC transmission verification codes for memory read operations. In a memory system using a DDR5 memory module, CRC transmission verification can be performed in both read and write directions. Based on the working state of the DDR5 memory module, when the DDR5 memory module does not perform read and write operations after entering the idle state, it can accept the setting command of the mode register at any time to realize the opening and closing of the CRC transmission verification function.

An embodiment of the present application further provides a computer system, including: a control device as shown in any one of FIG. 6 to FIG. 8 and the above-mentioned memory system. The basic architecture of the computer system can be shown in FIG. 1 .

An embodiment of the present application further provides a computer-readable storage medium, where instructions are stored on the computer-readable storage medium, and when the instructions are executed by a processor, the steps performed by the control device in the foregoing method embodiments are implemented.

An embodiment of the present application further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps performed by the control device in the foregoing method embodiments are implemented.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, and the like.

In the embodiments of the present application, the terms "first", "second" and "third" are used for description purposes only, and cannot be understood as indicating or implying relative importance.

The term "and/or" in this application is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and A and B exist alone. There are three cases of B. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

The above are only optional embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the concept and principles of the application shall be included in the protection of the application. within range.

Claims (25)

1. A method for detecting a memory channel failure, the method being applied to a control device, the method comprising:

Obtaining error checking and correction ECC error statistical information of a memory channel by a memory controller, wherein the ECC error statistical information is used for reflecting the times of ECC errors of the memory channel;

and when the number of times of ECC errors of the memory channel exceeds a first time threshold, controlling the memory controller to perform Cyclic Redundancy Check (CRC) transmission check on a memory channel link in the memory channel so as to determine whether the memory channel link fails.

2. The method of claim 1, wherein the ECC error statistics include a number of ECC errors occurred for the memory channel or a status indication that the number of ECC errors occurred for the memory channel exceeds a first threshold number.

3. The method according to claim 1 or 2, wherein the memory controller performs cyclic redundancy check, CRC, transmission check on a memory channel link in the memory channel, comprising:

the memory controller performs CRC transmission check of the writing memory direction on the memory channel link;

and/or, the memory module in the memory channel has the capability of calculating CRC transmission check codes, and the memory controller controls the memory module to carry out CRC transmission check in the memory reading direction on the memory channel link.

4. A method according to any one of claims 1 to 3, wherein the method further comprises:

and responding to the failure of the memory channel link, or controlling the memory controller to stop performing CRC transmission check on the memory channel link by controlling the memory controller when the duration of performing CRC transmission check on the memory channel link reaches a duration threshold.

5. The method according to any one of claims 1 to 4, further comprising:

and after determining that the memory channel link fails, outputting a first failure detection result, wherein the first failure detection result indicates that the memory channel link fails.

6. The method of any of claims 1-4, wherein the ECC error statistics include a memory address in the memory channel where an ECC error occurred, the method further comprising:

and after determining that the memory channel link fails, outputting a second failure detection result, wherein the second failure detection result indicates that the memory module corresponding to the memory address fails.

7. The method according to any one of claims 1 to 6, further comprising:

Outputting a fault indication when the number of times of ECC errors of the memory channel exceeds the first time threshold, wherein the fault indication is used for indicating that the memory channel has faults;

the controlling the memory controller to perform Cyclic Redundancy Check (CRC) transmission check on a memory channel link in the memory channel includes:

and responding to a memory channel link diagnosis command aiming at the memory channel, and controlling the memory controller to carry out CRC transmission check on the memory channel link.

8. The method of claim 7, wherein the memory channel link diagnostic command includes a second time threshold and/or a duration threshold, wherein the second time threshold is used to: when the number of times of CRC transmission check errors of the memory channel link exceeds the second time threshold, judging that the memory channel link fails; the time threshold is the maximum allowable time for performing CRC transmission check on the memory channel link.

9. A control apparatus, characterized in that the control apparatus comprises:

the acquisition module is used for acquiring error checking and correcting ECC error statistical information of the memory channel by the memory controller, wherein the ECC error statistical information is used for reflecting the times of ECC errors of the memory channel;

And the control module is used for controlling the memory controller to carry out Cyclic Redundancy Check (CRC) transmission check on a memory channel link in the memory channel when the number of times of ECC errors of the memory channel exceeds a first time threshold value so as to determine whether the memory channel link fails.

10. The control device of claim 9, wherein the ECC error statistics include a number of ECC errors occurred for the memory channel or a status indication that the number of ECC errors occurred for the memory channel exceeds a first threshold number.

11. The control device according to claim 9 or 10, wherein the memory controller performs Cyclic Redundancy Check (CRC) transmission check on a memory channel link in the memory channel, comprising:

the memory controller performs CRC transmission check of the writing memory direction on the memory channel link;

and/or, the memory module in the memory channel has the capability of calculating CRC transmission check codes, and the memory controller controls the memory module to carry out CRC transmission check in the memory reading direction on the memory channel link.

12. The control device according to any one of claims 9 to 11, characterized in that,

The control module is further configured to, in response to a failure of the memory channel link, or when a duration of performing CRC transmission check on the memory channel link by the memory controller reaches a duration threshold, control the memory controller to stop performing CRC transmission check on the memory channel link.

13. The control apparatus according to any one of claims 9 to 12, characterized in that the control apparatus further comprises:

and the output module is used for outputting a first fault detection result after determining that the memory channel link breaks down, wherein the first fault detection result indicates that the memory channel link breaks down.

14. The control apparatus according to any one of claims 9 to 12, wherein the ECC error statistic information includes a memory address in the memory channel where an ECC error occurred, the control apparatus further comprising:

and the output module is used for outputting a second fault detection result after determining that the memory channel link does not fail, wherein the second fault detection result indicates that the memory module corresponding to the memory address fails.

15. The control apparatus according to any one of claims 9 to 14, characterized in that the control apparatus further comprises:

The output module is used for outputting a fault indication when the number of times of ECC errors of the memory channel exceeds the first time threshold value, wherein the fault indication is used for indicating the memory channel to fail;

the control module is configured to control the memory controller to perform CRC transmission check on the memory channel link in response to a memory channel link diagnosis command for the memory channel.

16. The control device of claim 15, wherein the memory channel link diagnostic command includes a second time threshold and/or a duration threshold, wherein the second time threshold is used to: when the number of times of CRC transmission check errors of the memory channel link exceeds the second time threshold, judging that the memory channel link fails; the time threshold is the maximum allowable time for performing CRC transmission check on the memory channel link.

17. A control apparatus, characterized by comprising: a processor and a memory;

the memory is used for storing a computer program, and the computer program comprises program instructions;

the processor is configured to invoke the computer program to implement the memory channel failure detection method according to any one of claims 1 to 8.

18. A memory system, comprising: a memory controller and a memory channel;

the memory controller is used for performing error checking and ECC correction checking on the memory channel and recording the times of ECC errors of the memory channel;

the memory controller is further configured to perform a CRC transmission check on a memory channel link in the memory channel after receiving a CRC transmission check command for the memory channel.

19. The memory system of claim 18, wherein,

the memory controller is further configured to record a status indication after the number of times of ECC errors occurring in the memory channel exceeds a first time threshold, where the status indication is used to indicate that the number of times of ECC errors occurring in the memory channel exceeds the first time threshold.

20. The memory system according to claim 18 or 19, wherein the memory controller performs a cyclic redundancy check, CRC, transmission check on a memory channel link in the memory channel, comprising:

the memory controller performs CRC transmission check of the writing memory direction on the memory channel link;

and/or, the memory module in the memory channel has the capability of calculating CRC transmission check codes, and the memory controller controls the memory module to carry out CRC transmission check in the memory reading direction on the memory channel link.

21. The memory system according to any one of claims 18 to 20, wherein,

the memory controller is further configured to record the number of times that the CRC transmission check error occurs on the memory channel link;

the memory controller is further configured to stop performing CRC transmission check on the memory channel link after the number of times that the CRC transmission check error occurs on the memory channel link exceeds a second number of times threshold, or after a duration of performing CRC transmission check on the memory channel link reaches a duration threshold.

22. The memory system of claim 20, wherein,

the memory controller is used for performing CRC transmission check of the writing memory direction on the memory channel link;

the memory module is used for recording the times of the CRC transmission check errors of the memory channel link in the memory writing direction, and stopping checking the CRC transmission check code received by the memory channel link when the times of the CRC transmission check errors of the memory channel link in the memory writing direction exceed a second time threshold.

23. A computer system, comprising: a control apparatus as claimed in any one of claims 9 to 17 and a memory system as claimed in any one of claims 18 to 22.

24. A computer readable storage medium having instructions stored thereon which, when executed by a processor, implement the memory channel failure detection method of any of claims 1 to 8.

25. A computer program product comprising a computer program which, when executed by a processor, implements the memory channel failure detection method of any of claims 1 to 8.

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